Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18201555	1			T1	68176		T2	2295		T3	40411
all_values[1]	18201555	1			T1	68176		T2	2295		T3	40411
all_values[2]	18201555	1			T1	68176		T2	2295		T3	40411

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270945

1

T2

36

T3

322

T5

110

auto[1]

54333720

1

T1

204528

T2

6849

T3

120911

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46480224

1

T1

182120

T2

5960

T3

104570

auto[1]

8124441

1

T1

22408

T2

925

T3

16663

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	75339	1			T3	104		T5	53		T15	6
all_values[0]	auto[0]	auto[1]	327	1			T3	2		T5	2		T15	1
all_values[0]	auto[1]	auto[0]	18106118	1			T1	68151		T2	2264		T3	40289
all_values[0]	auto[1]	auto[1]	19771	1			T1	25		T2	31		T3	16
all_values[1]	auto[0]	auto[0]	105069	1			T2	18		T3	110		T15	3
all_values[1]	auto[0]	auto[1]	193	1			T15	1		T10	1		T67	1
all_values[1]	auto[1]	auto[0]	18095963	1			T1	68176		T2	2274		T3	40301
all_values[1]	auto[1]	auto[1]	330	1			T2	3		T14	2		T15	1
all_values[2]	auto[0]	auto[0]	51186	1			T2	4		T3	106		T5	55
all_values[2]	auto[0]	auto[1]	38831	1			T2	14		T15	500		T10	4
all_values[2]	auto[1]	auto[0]	10046549	1			T1	45793		T2	1400		T3	23660
all_values[2]	auto[1]	auto[1]	8064989	1			T1	22383		T2	877		T3	16645