Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144755

1

T2

510

T4

6

T5

12

auto[1]

124382

1

T1

70

T2

868

T3

58

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	105748	1			T1	17		T2	584		T3	14
len_1026_2046	5403	1			T2	73		T14	58		T15	2
len_514_1022	4315	1			T2	7		T14	19		T15	4
len_2_510	2937	1			T2	3		T14	14		T15	1
len_2056	201	1			T1	2		T10	4		T53	7
len_2048	405	1			T1	1		T5	2		T15	2
len_2040	224	1			T5	2		T15	2		T10	1
len_1032	184	1			T5	6		T10	1		T25	3
len_1024	1775	1			T2	1		T14	2		T10	4
len_1016	342	1			T5	4		T10	6		T25	3
len_520	179	1			T5	3		T10	10		T43	1
len_512	364	1			T2	1		T5	2		T14	1
len_504	185	1			T5	2		T25	3		T43	1
len_8	1106	1			T1	15		T3	15		T10	8
len_0	11202	1			T2	20		T6	1		T14	12

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

133

1

T2

2

T16

2

T10

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	57306	1			T2	179		T4	3		T6	11
auto[0]	len_1026_2046	2678	1			T2	66		T14	27		T15	2
auto[0]	len_514_1022	2785	1			T2	5		T14	17		T15	1
auto[0]	len_2_510	1987	1			T2	3		T14	12		T10	10
auto[0]	len_2056	105	1			T10	1		T53	5		T8	3
auto[0]	len_2048	217	1			T5	2		T15	1		T16	1
auto[0]	len_2040	102	1			T5	1		T15	2		T25	2
auto[0]	len_1032	111	1			T5	1		T10	1		T25	1
auto[0]	len_1024	252	1			T2	1		T14	1		T10	3
auto[0]	len_1016	148	1			T10	4		T25	3		T43	1
auto[0]	len_520	97	1			T10	7		T43	1		T122	2
auto[0]	len_512	232	1			T2	1		T5	1		T14	1
auto[0]	len_504	110	1			T5	1		T43	1		T53	2
auto[0]	len_8	29	1			T58	1		T122	1		T123	1
auto[0]	len_0	6220	1			T6	1		T14	12		T15	3
auto[1]	len_2050_plus	48442	1			T1	17		T2	405		T3	14
auto[1]	len_1026_2046	2725	1			T2	7		T14	31		T10	26
auto[1]	len_514_1022	1530	1			T2	2		T14	2		T15	3
auto[1]	len_2_510	950	1			T14	2		T15	1		T10	26
auto[1]	len_2056	96	1			T1	2		T10	3		T53	2
auto[1]	len_2048	188	1			T1	1		T15	1		T25	1
auto[1]	len_2040	122	1			T5	1		T10	1		T39	1
auto[1]	len_1032	73	1			T5	5		T25	2		T53	1
auto[1]	len_1024	1523	1			T14	1		T10	1		T26	1
auto[1]	len_1016	194	1			T5	4		T10	2		T34	1
auto[1]	len_520	82	1			T5	3		T10	3		T53	3
auto[1]	len_512	132	1			T5	1		T10	2		T26	1
auto[1]	len_504	75	1			T5	1		T25	3		T53	2
auto[1]	len_8	1077	1			T1	15		T3	15		T10	8
auto[1]	len_0	4982	1			T2	20		T15	4		T10	141

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

72

1

T2

2

T16

2

T10

1

auto[1]

len_upper

61

1

T26

1

T68

1

T52

2