Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18201555	1			T1	68176		T2	2295		T3	40411
all_pins[1]	18201555	1			T1	68176		T2	2295		T3	40411
all_pins[2]	18201555	1			T1	68176		T2	2295		T3	40411

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46518670	1			T1	182115		T2	5967		T3	104569
values[0x1]	8085995	1			T1	22413		T2	918		T3	16664
transitions[0x0=>0x1]	8085835	1			T1	22413		T2	918		T3	16664
transitions[0x1=>0x0]	8085851	1			T1	22413		T2	918		T3	16664

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18180908	1			T1	68146		T2	2259		T3	40392
all_pins[0]	values[0x1]	20647	1			T1	30		T2	36		T3	19
all_pins[0]	transitions[0x0=>0x1]	20572	1			T1	30		T2	36		T3	19
all_pins[0]	transitions[0x1=>0x0]	8064930	1			T1	22383		T2	877		T3	16645
all_pins[1]	values[0x0]	18201196	1			T1	68176		T2	2290		T3	40411
all_pins[1]	values[0x1]	359	1			T2	5		T14	3		T15	1
all_pins[1]	transitions[0x0=>0x1]	317	1			T2	5		T14	3		T15	1
all_pins[1]	transitions[0x1=>0x0]	20605	1			T1	30		T2	36		T3	19
all_pins[2]	values[0x0]	10136566	1			T1	45793		T2	1418		T3	23766
all_pins[2]	values[0x1]	8064989	1			T1	22383		T2	877		T3	16645
all_pins[2]	transitions[0x0=>0x1]	8064946	1			T1	22383		T2	877		T3	16645
all_pins[2]	transitions[0x1=>0x0]	316	1			T2	5		T14	3		T15	1