Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 908 1 T15 7 T10 7 T25 4
all_values[1] 908 1 T15 7 T10 7 T25 4
all_values[2] 908 1 T15 7 T10 7 T25 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1381 1 T15 7 T10 15 T25 6
auto[1] 1343 1 T15 14 T10 6 T25 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 981 1 T15 10 T10 4 T25 4
auto[1] 1743 1 T15 11 T10 17 T25 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1546 1 T15 13 T10 9 T25 7
auto[1] 1178 1 T15 8 T10 12 T25 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 196 1 T15 3 T10 2 T25 1
all_values[0] auto[0] auto[0] auto[1] 95 1 T10 1 T25 1 T67 1
all_values[0] auto[0] auto[1] auto[0] 171 1 T15 1 T59 5 T8 11
all_values[0] auto[0] auto[1] auto[1] 73 1 T10 1 T8 1 T81 3
all_values[0] auto[1] auto[0] auto[1] 183 1 T15 2 T10 3 T25 1
all_values[0] auto[1] auto[1] auto[1] 190 1 T15 1 T25 1 T59 2
all_values[1] auto[0] auto[0] auto[0] 138 1 T15 1 T10 2 T25 1
all_values[1] auto[0] auto[0] auto[1] 116 1 T15 1 T10 1 T67 1
all_values[1] auto[0] auto[1] auto[0] 141 1 T15 3 T25 1 T8 2
all_values[1] auto[0] auto[1] auto[1] 109 1 T10 1 T25 1 T59 2
all_values[1] auto[1] auto[0] auto[1] 190 1 T10 1 T67 1 T59 2
all_values[1] auto[1] auto[1] auto[1] 214 1 T15 2 T10 2 T25 1
all_values[2] auto[0] auto[0] auto[0] 169 1 T25 1 T59 4 T8 7
all_values[2] auto[0] auto[0] auto[1] 97 1 T10 1 T59 3 T8 1
all_values[2] auto[0] auto[1] auto[0] 166 1 T15 2 T67 2 T59 1
all_values[2] auto[0] auto[1] auto[1] 75 1 T15 2 T25 1 T67 1
all_values[2] auto[1] auto[0] auto[1] 197 1 T10 4 T25 1 T59 6
all_values[2] auto[1] auto[1] auto[1] 204 1 T15 3 T10 2 T25 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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