Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4176	1			T1	4		T2	1		T3	6
sha2_none	4308	1			T1	4		T2	5		T3	7
sha2_512	7749	1			T1	17		T2	14		T3	11
sha2_384	7430	1			T1	9		T2	8		T3	4
sha2_256	6327	1			T1	11		T2	9		T3	6

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18925

1

T1

28

T2

19

T3

20

auto[1]

11446

1

T1

18

T2

18

T3

15

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11365

1

T1

18

T2

20

T3

16

auto[1]

19006

1

T1

28

T2

17

T3

19

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15809

1

T1

46

T2

17

T3

35

disabled

14562

1

T2

20

T4

4

T5

11

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4690	1			T1	10		T2	7		T3	2
key_none	7808	1			T1	7		T2	4		T3	6
key_1024	4321	1			T1	7		T2	3		T3	1
key_512	3791	1			T1	2		T2	4		T3	5
key_384	3426	1			T1	4		T2	5		T3	6
key_256	3239	1			T1	5		T2	8		T3	7
key_128	3018	1			T1	11		T2	6		T3	8

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18920

1

T1

21

T2

20

T3

14

auto[1]

11451

1

T1

25

T2

17

T3

21

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30176

1

T1

46

T2

37

T3

35

disabled

195

1

T25

2

T30

2

T7

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1585

1

T1

8

T2

3

T3

4

enabled

auto[0]

auto[0]

auto[1]

1634

1

T1

5

T2

2

T3

3

enabled

auto[0]

auto[1]

auto[0]

1624

1

T1

1

T2

4

T3

2

enabled

auto[0]

auto[1]

auto[1]

1632

1

T1

4

T2

3

T3

7

enabled

auto[1]

auto[0]

auto[0]

4336

1

T1

6

T2

2

T3

5

enabled

auto[1]

auto[0]

auto[1]

1593

1

T1

9

T3

8

T5

3

enabled

auto[1]

auto[1]

auto[0]

1757

1

T1

6

T2

2

T3

3

enabled

auto[1]

auto[1]

auto[1]

1648

1

T1

7

T2

1

T3

3

disabled

auto[0]

auto[0]

auto[0]

1218

1

T2

1

T5

2

T6

3

disabled

auto[0]

auto[0]

auto[1]

1263

1

T2

2

T6

4

T14

3

disabled

auto[0]

auto[1]

auto[0]

1187

1

T2

4

T6

1

T14

2

disabled

auto[0]

auto[1]

auto[1]

1222

1

T2

1

T5

1

T14

4

disabled

auto[1]

auto[0]

auto[0]

6041

1

T2

4

T4

2

T5

2

disabled

auto[1]

auto[0]

auto[1]

1255

1

T2

5

T4

2

T5

1

disabled

auto[1]

auto[1]

auto[0]

1172

1

T5

3

T15

8

T10

12

disabled

auto[1]

auto[1]

auto[1]

1204

1

T2

3

T5

2

T6

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15723

1

T1

46

T2

17

T3

35

enabled

disabled

86

1

T25

2

T30

2

T46

1

disabled

disabled

109

1

T7

1

T46

1

T59

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14453

1

T2

20

T4

4

T5

11

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1083	1			T1	1		T2	1		T5	1
key_invalid	sha2_none	879	1			T2	1		T4	1		T5	1
key_invalid	sha2_512	878	1			T1	4		T2	2		T6	1
key_invalid	sha2_384	871	1			T1	2		T2	2		T5	1
key_invalid	sha2_256	886	1			T1	2		T2	1		T3	2
key_none	sha2_invalid	540	1			T3	1		T5	1		T14	1
key_none	sha2_none	559	1			T1	1		T2	1		T5	1
key_none	sha2_512	2548	1			T1	4		T2	1		T3	2
key_none	sha2_384	2545	1			T1	1		T2	2		T3	2
key_none	sha2_256	1574	1			T1	1		T3	1		T5	1
key_1024	sha2_invalid	529	1			T1	1		T5	2		T14	1
key_1024	sha2_none	549	1			T5	3		T6	1		T15	3
key_1024	sha2_512	1745	1			T1	2		T2	2		T5	2
key_1024	sha2_384	889	1			T1	1		T6	1		T14	4
key_512	sha2_invalid	503	1			T3	2		T5	1		T15	3
key_512	sha2_none	575	1			T2	1		T3	1		T14	3
key_512	sha2_512	660	1			T2	1		T3	2		T4	2
key_512	sha2_384	1187	1			T1	2		T5	1		T6	1
key_512	sha2_256	825	1			T2	2		T6	1		T14	2
key_384	sha2_invalid	476	1			T3	1		T5	1		T15	3
key_384	sha2_none	571	1			T3	2		T5	1		T6	1
key_384	sha2_512	592	1			T1	1		T2	2		T3	2
key_384	sha2_384	660	1			T1	1		T2	1		T3	1
key_384	sha2_256	1080	1			T1	2		T2	2		T5	1
key_256	sha2_invalid	517	1			T1	1		T3	2		T5	1
key_256	sha2_none	616	1			T1	1		T2	2		T3	2
key_256	sha2_512	667	1			T1	2		T2	3		T3	1
key_256	sha2_384	629	1			T2	2		T5	1		T15	1
key_256	sha2_256	764	1			T1	1		T2	1		T3	1
key_128	sha2_invalid	510	1			T1	1		T5	1		T14	1
key_128	sha2_none	543	1			T1	2		T3	2		T4	1
key_128	sha2_512	638	1			T1	4		T2	3		T3	4
key_128	sha2_384	644	1			T1	2		T2	1		T3	1
key_128	sha2_256	625	1			T1	2		T2	2		T3	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

557

1

T1

3

T2

1

T3

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1083	1			T1	1		T2	1		T5	1
key_invalid	sha2_none	879	1			T2	1		T4	1		T5	1
key_invalid	sha2_512	878	1			T1	4		T2	2		T6	1
key_invalid	sha2_384	871	1			T1	2		T2	2		T5	1
key_invalid	sha2_256	886	1			T1	2		T2	1		T3	2
key_none	sha2_invalid	540	1			T3	1		T5	1		T14	1
key_none	sha2_none	559	1			T1	1		T2	1		T5	1
key_none	sha2_512	2548	1			T1	4		T2	1		T3	2
key_none	sha2_384	2545	1			T1	1		T2	2		T3	2
key_none	sha2_256	1574	1			T1	1		T3	1		T5	1
key_1024	sha2_invalid	529	1			T1	1		T5	2		T14	1
key_1024	sha2_none	549	1			T5	3		T6	1		T15	3
key_1024	sha2_512	1745	1			T1	2		T2	2		T5	2
key_1024	sha2_384	889	1			T1	1		T6	1		T14	4
key_1024	sha2_256	557	1			T1	3		T2	1		T3	1
key_512	sha2_invalid	503	1			T3	2		T5	1		T15	3
key_512	sha2_none	575	1			T2	1		T3	1		T14	3
key_512	sha2_512	660	1			T2	1		T3	2		T4	2
key_512	sha2_384	1187	1			T1	2		T5	1		T6	1
key_512	sha2_256	825	1			T2	2		T6	1		T14	2
key_384	sha2_invalid	476	1			T3	1		T5	1		T15	3
key_384	sha2_none	571	1			T3	2		T5	1		T6	1
key_384	sha2_512	592	1			T1	1		T2	2		T3	2
key_384	sha2_384	660	1			T1	1		T2	1		T3	1
key_384	sha2_256	1080	1			T1	2		T2	2		T5	1
key_256	sha2_invalid	517	1			T1	1		T3	2		T5	1
key_256	sha2_none	616	1			T1	1		T2	2		T3	2
key_256	sha2_512	667	1			T1	2		T2	3		T3	1
key_256	sha2_384	629	1			T2	2		T5	1		T15	1
key_256	sha2_256	764	1			T1	1		T2	1		T3	1
key_128	sha2_invalid	510	1			T1	1		T5	1		T14	1
key_128	sha2_none	543	1			T1	2		T3	2		T4	1
key_128	sha2_512	638	1			T1	4		T2	3		T3	4
key_128	sha2_384	644	1			T1	2		T2	1		T3	1
key_128	sha2_256	625	1			T1	2		T2	2		T3	1