Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 657
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T78 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1319290271 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:58 PM PDT 24 385695426 ps
T531 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1750231526 Aug 06 07:10:20 PM PDT 24 Aug 06 07:10:22 PM PDT 24 870431560 ps
T532 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1181101383 Aug 06 07:10:00 PM PDT 24 Aug 06 07:10:02 PM PDT 24 369335515 ps
T62 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1624603699 Aug 06 07:09:54 PM PDT 24 Aug 06 07:09:57 PM PDT 24 341990466 ps
T102 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1482781453 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:17 PM PDT 24 53066561 ps
T533 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4224695269 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:58 PM PDT 24 32554068 ps
T121 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.515870627 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 63698537 ps
T534 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4165452908 Aug 06 07:10:27 PM PDT 24 Aug 06 07:10:28 PM PDT 24 13449635 ps
T112 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3967294894 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:20 PM PDT 24 58569093 ps
T535 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4266083807 Aug 06 07:10:30 PM PDT 24 Aug 06 07:10:31 PM PDT 24 50739139 ps
T114 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1886154632 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:19 PM PDT 24 470629438 ps
T536 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2896624221 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 14246923 ps
T537 /workspace/coverage/cover_reg_top/10.hmac_intr_test.175299016 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:14 PM PDT 24 25644044 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3560766286 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:57 PM PDT 24 21926910 ps
T538 /workspace/coverage/cover_reg_top/47.hmac_intr_test.625589202 Aug 06 07:10:34 PM PDT 24 Aug 06 07:10:35 PM PDT 24 137011979 ps
T539 /workspace/coverage/cover_reg_top/8.hmac_intr_test.54000974 Aug 06 07:09:58 PM PDT 24 Aug 06 07:09:59 PM PDT 24 48966803 ps
T89 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.844240440 Aug 06 07:10:00 PM PDT 24 Aug 06 07:10:00 PM PDT 24 36050481 ps
T540 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2420818729 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:16 PM PDT 24 37841916 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2731770386 Aug 06 07:10:01 PM PDT 24 Aug 06 07:10:02 PM PDT 24 108956838 ps
T541 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.884940024 Aug 06 07:10:22 PM PDT 24 Aug 06 07:10:24 PM PDT 24 308499611 ps
T120 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2164471250 Aug 06 07:09:57 PM PDT 24 Aug 06 07:10:02 PM PDT 24 286002524 ps
T542 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2988199108 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:13 PM PDT 24 19150971 ps
T543 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2652228041 Aug 06 07:10:30 PM PDT 24 Aug 06 07:10:30 PM PDT 24 82650708 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3359680781 Aug 06 07:09:53 PM PDT 24 Aug 06 07:09:56 PM PDT 24 1050031414 ps
T117 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2137511811 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:19 PM PDT 24 59914670 ps
T545 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2080129957 Aug 06 07:09:58 PM PDT 24 Aug 06 07:10:04 PM PDT 24 4387679731 ps
T90 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3563865971 Aug 06 07:10:19 PM PDT 24 Aug 06 07:10:19 PM PDT 24 18178280 ps
T546 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1079882216 Aug 06 07:10:30 PM PDT 24 Aug 06 07:10:31 PM PDT 24 47338501 ps
T547 /workspace/coverage/cover_reg_top/35.hmac_intr_test.4205759040 Aug 06 07:10:31 PM PDT 24 Aug 06 07:10:32 PM PDT 24 44933803 ps
T91 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.365325279 Aug 06 07:10:21 PM PDT 24 Aug 06 07:10:22 PM PDT 24 115454678 ps
T548 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1394533695 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:30 PM PDT 24 41974746 ps
T118 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3017020779 Aug 06 07:10:01 PM PDT 24 Aug 06 07:10:04 PM PDT 24 570846247 ps
T549 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2335367736 Aug 06 07:10:14 PM PDT 24 Aug 06 07:10:15 PM PDT 24 129823329 ps
T550 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3014747063 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:30 PM PDT 24 26822939 ps
T551 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1345564234 Aug 06 07:10:20 PM PDT 24 Aug 06 07:10:22 PM PDT 24 100702530 ps
T552 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1878604175 Aug 06 07:10:34 PM PDT 24 Aug 06 07:10:34 PM PDT 24 33126183 ps
T105 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2112550822 Aug 06 07:10:03 PM PDT 24 Aug 06 07:10:04 PM PDT 24 1239159772 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3249377503 Aug 06 07:10:01 PM PDT 24 Aug 06 07:10:02 PM PDT 24 18996106 ps
T553 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2981217259 Aug 06 07:09:58 PM PDT 24 Aug 06 07:10:00 PM PDT 24 38546872 ps
T554 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3280360143 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:16 PM PDT 24 88777508 ps
T106 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2418236177 Aug 06 07:10:24 PM PDT 24 Aug 06 07:10:24 PM PDT 24 43108588 ps
T555 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1534524529 Aug 06 07:10:20 PM PDT 24 Aug 06 07:10:21 PM PDT 24 76904140 ps
T107 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1575360647 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:14 PM PDT 24 19833129 ps
T556 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.54242311 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:58 PM PDT 24 100883231 ps
T557 /workspace/coverage/cover_reg_top/42.hmac_intr_test.435723665 Aug 06 07:10:32 PM PDT 24 Aug 06 07:10:33 PM PDT 24 12154380 ps
T558 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1568606128 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:59 PM PDT 24 103059579 ps
T559 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3301411319 Aug 06 07:10:14 PM PDT 24 Aug 06 07:10:15 PM PDT 24 25500982 ps
T560 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2222269788 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:17 PM PDT 24 51746617 ps
T561 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2867978354 Aug 06 07:10:32 PM PDT 24 Aug 06 07:10:32 PM PDT 24 44814833 ps
T562 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4191711768 Aug 06 07:10:20 PM PDT 24 Aug 06 07:27:49 PM PDT 24 222407768193 ps
T563 /workspace/coverage/cover_reg_top/7.hmac_intr_test.135922954 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:56 PM PDT 24 21909393 ps
T564 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2775121139 Aug 06 07:10:34 PM PDT 24 Aug 06 07:10:35 PM PDT 24 18691108 ps
T565 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1969797911 Aug 06 07:10:32 PM PDT 24 Aug 06 07:10:32 PM PDT 24 47479304 ps
T566 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1350702252 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:56 PM PDT 24 65017555 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3861511117 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 35050730 ps
T567 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3843392778 Aug 06 07:10:19 PM PDT 24 Aug 06 07:10:22 PM PDT 24 398522890 ps
T119 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1559545459 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:03 PM PDT 24 127215048 ps
T568 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1694434457 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:55 PM PDT 24 35914677 ps
T569 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.912810242 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:58 PM PDT 24 85335510 ps
T570 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4162493194 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:30 PM PDT 24 27546918 ps
T571 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.902815808 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:57 PM PDT 24 194292949 ps
T572 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2256362019 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:18 PM PDT 24 24143871 ps
T94 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3265014515 Aug 06 07:10:19 PM PDT 24 Aug 06 07:10:19 PM PDT 24 39919040 ps
T95 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3069192601 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:58 PM PDT 24 197245005 ps
T573 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3020548459 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 14462342 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3119234452 Aug 06 07:10:00 PM PDT 24 Aug 06 07:10:09 PM PDT 24 1228443849 ps
T574 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2996063547 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:02 PM PDT 24 164964696 ps
T575 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1885902103 Aug 06 07:10:12 PM PDT 24 Aug 06 07:10:16 PM PDT 24 64801112 ps
T576 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2058015345 Aug 06 07:10:16 PM PDT 24 Aug 06 07:10:16 PM PDT 24 28037886 ps
T577 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3262607622 Aug 06 07:09:58 PM PDT 24 Aug 06 07:09:59 PM PDT 24 101929973 ps
T578 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4084500698 Aug 06 07:10:31 PM PDT 24 Aug 06 07:10:32 PM PDT 24 37588558 ps
T579 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.425877500 Aug 06 07:10:16 PM PDT 24 Aug 06 07:10:18 PM PDT 24 160076497 ps
T580 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1126626263 Aug 06 07:09:58 PM PDT 24 Aug 06 07:10:00 PM PDT 24 116874933 ps
T581 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2142932535 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:57 PM PDT 24 92888813 ps
T582 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2193207101 Aug 06 07:10:00 PM PDT 24 Aug 06 07:10:00 PM PDT 24 15825082 ps
T583 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2536437356 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:56 PM PDT 24 63155541 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2425721539 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 59658604 ps
T584 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1140579517 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:02 PM PDT 24 1792041176 ps
T585 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1937058460 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:30 PM PDT 24 27035995 ps
T586 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2408585777 Aug 06 07:10:12 PM PDT 24 Aug 06 07:10:13 PM PDT 24 24432235 ps
T587 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3558909617 Aug 06 07:09:55 PM PDT 24 Aug 06 07:10:00 PM PDT 24 426284709 ps
T588 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2754033062 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:19 PM PDT 24 305020561 ps
T589 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1909240452 Aug 06 07:10:30 PM PDT 24 Aug 06 07:10:31 PM PDT 24 105601845 ps
T590 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.627619203 Aug 06 07:09:58 PM PDT 24 Aug 06 07:10:01 PM PDT 24 102783838 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3343023181 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:45 PM PDT 24 73442461181 ps
T592 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1207436914 Aug 06 07:10:00 PM PDT 24 Aug 06 07:10:01 PM PDT 24 24656159 ps
T593 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2549912442 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 35187709 ps
T594 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3548757877 Aug 06 07:10:12 PM PDT 24 Aug 06 07:10:14 PM PDT 24 36451251 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.439405080 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:59 PM PDT 24 162519666 ps
T596 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1971251459 Aug 06 07:09:57 PM PDT 24 Aug 06 07:10:03 PM PDT 24 373142322 ps
T597 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1344713013 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 15531058 ps
T598 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3929225020 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:30 PM PDT 24 37712808 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2026012421 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 64788614 ps
T599 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1314760713 Aug 06 07:09:55 PM PDT 24 Aug 06 07:09:56 PM PDT 24 13476051 ps
T600 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4064560807 Aug 06 07:10:14 PM PDT 24 Aug 06 07:10:16 PM PDT 24 33449340 ps
T601 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1066729782 Aug 06 07:10:34 PM PDT 24 Aug 06 07:10:35 PM PDT 24 21569996 ps
T602 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3416944698 Aug 06 07:10:20 PM PDT 24 Aug 06 07:10:21 PM PDT 24 50279049 ps
T603 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.274183369 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:22 PM PDT 24 779057329 ps
T604 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1633072751 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:15 PM PDT 24 391604452 ps
T605 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2181866162 Aug 06 07:10:12 PM PDT 24 Aug 06 07:10:14 PM PDT 24 157393781 ps
T606 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2998550783 Aug 06 07:09:56 PM PDT 24 Aug 06 07:10:01 PM PDT 24 242263020 ps
T607 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2497434160 Aug 06 07:10:31 PM PDT 24 Aug 06 07:10:32 PM PDT 24 18015868 ps
T608 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2074691728 Aug 06 07:10:31 PM PDT 24 Aug 06 07:10:32 PM PDT 24 22262531 ps
T609 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1545396067 Aug 06 07:09:57 PM PDT 24 Aug 06 07:10:00 PM PDT 24 1308484607 ps
T610 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3671905834 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:22 PM PDT 24 964468301 ps
T611 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.444134106 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:59 PM PDT 24 237008236 ps
T612 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2075623155 Aug 06 07:10:19 PM PDT 24 Aug 06 07:10:19 PM PDT 24 31889823 ps
T613 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1973942389 Aug 06 07:10:21 PM PDT 24 Aug 06 07:10:23 PM PDT 24 49474724 ps
T115 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4083232659 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:21 PM PDT 24 274948667 ps
T116 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3620495972 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:59 PM PDT 24 655735939 ps
T614 /workspace/coverage/cover_reg_top/19.hmac_intr_test.805934431 Aug 06 07:10:21 PM PDT 24 Aug 06 07:10:22 PM PDT 24 11761093 ps
T615 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3977527903 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:18 PM PDT 24 1021080856 ps
T616 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3403823193 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:20 PM PDT 24 47514782 ps
T617 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3094390673 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:30 PM PDT 24 58900472 ps
T618 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4028364675 Aug 06 07:10:16 PM PDT 24 Aug 06 07:10:17 PM PDT 24 60493137 ps
T619 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3352105187 Aug 06 07:10:30 PM PDT 24 Aug 06 07:10:30 PM PDT 24 68323804 ps
T620 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2538539206 Aug 06 07:09:57 PM PDT 24 Aug 06 07:18:24 PM PDT 24 253887363619 ps
T621 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3650849048 Aug 06 07:10:33 PM PDT 24 Aug 06 07:10:33 PM PDT 24 61728436 ps
T622 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.588403089 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:17 PM PDT 24 404760086 ps
T623 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3662726562 Aug 06 07:10:01 PM PDT 24 Aug 06 07:10:03 PM PDT 24 423997619 ps
T624 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1711243343 Aug 06 07:10:12 PM PDT 24 Aug 06 07:10:14 PM PDT 24 85561455 ps
T625 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3006172806 Aug 06 07:09:58 PM PDT 24 Aug 06 07:10:01 PM PDT 24 139541849 ps
T626 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3008868573 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:20 PM PDT 24 148599112 ps
T627 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1657965768 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:01 PM PDT 24 168011783 ps
T628 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2786950363 Aug 06 07:10:22 PM PDT 24 Aug 06 07:10:22 PM PDT 24 13868232 ps
T629 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3675967201 Aug 06 07:10:14 PM PDT 24 Aug 06 07:10:15 PM PDT 24 23898073 ps
T630 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2630436254 Aug 06 07:09:57 PM PDT 24 Aug 06 07:10:03 PM PDT 24 431760326 ps
T100 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4236615806 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:14 PM PDT 24 211616838 ps
T631 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2546289553 Aug 06 07:10:22 PM PDT 24 Aug 06 07:10:23 PM PDT 24 115869131 ps
T632 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2236316779 Aug 06 07:10:33 PM PDT 24 Aug 06 07:10:34 PM PDT 24 13887011 ps
T633 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2909148927 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:19 PM PDT 24 50781357 ps
T634 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3329446374 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:19 PM PDT 24 36500427 ps
T635 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2125499406 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:01 PM PDT 24 55283444 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2367101304 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:18 PM PDT 24 231689682 ps
T113 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1747645669 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:19 PM PDT 24 314538764 ps
T637 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4094065653 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:18 PM PDT 24 447910437 ps
T638 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1369775530 Aug 06 07:10:13 PM PDT 24 Aug 06 07:10:15 PM PDT 24 154872797 ps
T639 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3128333022 Aug 06 07:10:31 PM PDT 24 Aug 06 07:10:32 PM PDT 24 90412287 ps
T640 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2895300997 Aug 06 07:10:12 PM PDT 24 Aug 06 07:10:14 PM PDT 24 120726046 ps
T641 /workspace/coverage/cover_reg_top/41.hmac_intr_test.596750140 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:29 PM PDT 24 56283047 ps
T642 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1555598732 Aug 06 07:10:16 PM PDT 24 Aug 06 07:25:17 PM PDT 24 62793850845 ps
T643 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1172599588 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:59 PM PDT 24 70508549 ps
T644 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.644296922 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:59 PM PDT 24 261792294 ps
T645 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2483474613 Aug 06 07:09:58 PM PDT 24 Aug 06 07:09:59 PM PDT 24 14486396 ps
T646 /workspace/coverage/cover_reg_top/0.hmac_intr_test.249645699 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:58 PM PDT 24 10768670 ps
T647 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3507011510 Aug 06 07:10:18 PM PDT 24 Aug 06 07:10:21 PM PDT 24 93051424 ps
T648 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3213247856 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:57 PM PDT 24 58445728 ps
T649 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2317442831 Aug 06 07:09:56 PM PDT 24 Aug 06 07:09:58 PM PDT 24 88830174 ps
T650 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2938155461 Aug 06 07:10:17 PM PDT 24 Aug 06 07:10:18 PM PDT 24 47501903 ps
T651 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3620675532 Aug 06 07:09:57 PM PDT 24 Aug 06 07:09:58 PM PDT 24 56729684 ps
T652 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1189054578 Aug 06 07:10:01 PM PDT 24 Aug 06 07:10:12 PM PDT 24 1936292993 ps
T653 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3643569888 Aug 06 07:09:59 PM PDT 24 Aug 06 07:10:00 PM PDT 24 132867364 ps
T99 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.744331235 Aug 06 07:09:58 PM PDT 24 Aug 06 07:10:01 PM PDT 24 162545495 ps
T654 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1171923413 Aug 06 07:10:20 PM PDT 24 Aug 06 07:10:22 PM PDT 24 53235268 ps
T655 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.809881293 Aug 06 07:10:15 PM PDT 24 Aug 06 07:10:18 PM PDT 24 699885869 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4212098496 Aug 06 07:09:56 PM PDT 24 Aug 06 07:10:03 PM PDT 24 751610610 ps
T657 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4065206039 Aug 06 07:10:29 PM PDT 24 Aug 06 07:10:29 PM PDT 24 18612520 ps

Test location /workspace/coverage/default/26.hmac_datapath_stress.2646856580
Short name T1
Test name
Test status
Simulation time 5743460049 ps
CPU time 1152.13 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:34:47 PM PDT 24
Peak memory 739912 kb
Host smart-143a2ef3-9930-4f2f-904c-db034354944b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646856580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2646856580
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_stress_all.4040759114
Short name T10
Test name
Test status
Simulation time 17069827590 ps
CPU time 955.41 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:31:04 PM PDT 24
Peak memory 744940 kb
Host smart-d44f2916-b845-4318-b152-2865f902b66a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040759114 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4040759114
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.4270932575
Short name T18
Test name
Test status
Simulation time 54262233559 ps
CPU time 1550.01 seconds
Started Aug 06 07:14:19 PM PDT 24
Finished Aug 06 07:40:09 PM PDT 24
Peak memory 711964 kb
Host smart-d3f37db9-8435-4c94-a9e8-d97f513a4e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270932575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.4270932575
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3481816461
Short name T8
Test name
Test status
Simulation time 391229362352 ps
CPU time 1579.08 seconds
Started Aug 06 07:14:47 PM PDT 24
Finished Aug 06 07:41:06 PM PDT 24
Peak memory 447712 kb
Host smart-8d725f92-53df-4f07-a318-25d7f3533aa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481816461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3481816461
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.121112007
Short name T60
Test name
Test status
Simulation time 238245063 ps
CPU time 3.26 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 200184 kb
Host smart-afdd96be-a192-4a53-aef4-389defcbb073
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121112007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.121112007
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3688552072
Short name T49
Test name
Test status
Simulation time 282821948 ps
CPU time 0.78 seconds
Started Aug 06 07:14:25 PM PDT 24
Finished Aug 06 07:14:26 PM PDT 24
Peak memory 218368 kb
Host smart-686af224-2ccb-4554-91c1-1952f626a07d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688552072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3688552072
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3249377503
Short name T92
Test name
Test status
Simulation time 18996106 ps
CPU time 0.9 seconds
Started Aug 06 07:10:01 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 199920 kb
Host smart-327cd584-8b1a-4971-a59f-95c0dca40558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249377503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3249377503
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3188359738
Short name T11
Test name
Test status
Simulation time 6256151422 ps
CPU time 87.58 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:17:57 PM PDT 24
Peak memory 216348 kb
Host smart-f1c9be0c-4da0-4daa-97fb-a821c0714fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188359738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3188359738
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2782941448
Short name T63
Test name
Test status
Simulation time 45401400158 ps
CPU time 3403.28 seconds
Started Aug 06 07:14:33 PM PDT 24
Finished Aug 06 08:11:16 PM PDT 24
Peak memory 789352 kb
Host smart-e9390920-0290-4622-850c-a22d4c934c2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782941448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2782941448
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.422850313
Short name T54
Test name
Test status
Simulation time 95524329 ps
CPU time 0.6 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:09 PM PDT 24
Peak memory 196600 kb
Host smart-64182f94-53dd-42f1-aa7f-57472e529485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422850313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.422850313
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1559545459
Short name T119
Test name
Test status
Simulation time 127215048 ps
CPU time 4.04 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:03 PM PDT 24
Peak memory 200428 kb
Host smart-d1bf5a33-0d7f-414a-9293-701ea0c57a05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559545459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1559545459
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3620495972
Short name T116
Test name
Test status
Simulation time 655735939 ps
CPU time 3 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 199420 kb
Host smart-9da1d33b-afa7-4742-bf1c-75b7900b30ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620495972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3620495972
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1502378342
Short name T144
Test name
Test status
Simulation time 6943181213 ps
CPU time 650.69 seconds
Started Aug 06 07:14:53 PM PDT 24
Finished Aug 06 07:25:44 PM PDT 24
Peak memory 695980 kb
Host smart-dd73bd4c-3f24-4fee-91cb-d210cd54fa90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1502378342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1502378342
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2643136344
Short name T126
Test name
Test status
Simulation time 761862041 ps
CPU time 39.19 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 199884 kb
Host smart-8baa43c6-ba22-47f1-b641-0a4a7b918a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643136344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2643136344
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.606818914
Short name T61
Test name
Test status
Simulation time 99162266 ps
CPU time 1.74 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 200232 kb
Host smart-619dbb7b-520a-4e84-ad25-702a891a0666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606818914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.606818914
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3295037342
Short name T64
Test name
Test status
Simulation time 404191849367 ps
CPU time 6185.61 seconds
Started Aug 06 07:14:26 PM PDT 24
Finished Aug 06 08:57:33 PM PDT 24
Peak memory 851244 kb
Host smart-88344dcd-b986-419b-bccd-ff3021107ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295037342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3295037342
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4212098496
Short name T656
Test name
Test status
Simulation time 751610610 ps
CPU time 6.42 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:10:03 PM PDT 24
Peak memory 200132 kb
Host smart-937f5b08-4147-454a-87f9-7da29f7a7d40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212098496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4212098496
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2080129957
Short name T545
Test name
Test status
Simulation time 4387679731 ps
CPU time 6.13 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:10:04 PM PDT 24
Peak memory 199716 kb
Host smart-519ecbaf-ada8-483c-8ffb-4373e0a8797b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080129957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2080129957
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2425721539
Short name T97
Test name
Test status
Simulation time 59658604 ps
CPU time 0.76 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 198088 kb
Host smart-b25e4028-8d9a-42c3-b1a6-d9b37e3ec2e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425721539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2425721539
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2981217259
Short name T553
Test name
Test status
Simulation time 38546872 ps
CPU time 1.33 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 200136 kb
Host smart-817a6848-8610-412e-af7f-82f179897c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981217259 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2981217259
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.249645699
Short name T646
Test name
Test status
Simulation time 10768670 ps
CPU time 0.57 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 195020 kb
Host smart-8268e4e1-60bc-4b8d-86a1-a239ac721371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249645699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.249645699
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2731770386
Short name T104
Test name
Test status
Simulation time 108956838 ps
CPU time 1.22 seconds
Started Aug 06 07:10:01 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 198516 kb
Host smart-89c2c968-e835-43d3-8b9c-beb1a44467cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731770386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2731770386
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3006172806
Short name T625
Test name
Test status
Simulation time 139541849 ps
CPU time 2.96 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 200152 kb
Host smart-34d8ad05-280e-43fe-9508-8440c441a22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006172806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3006172806
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3119234452
Short name T96
Test name
Test status
Simulation time 1228443849 ps
CPU time 9.19 seconds
Started Aug 06 07:10:00 PM PDT 24
Finished Aug 06 07:10:09 PM PDT 24
Peak memory 200108 kb
Host smart-d534fe6e-4a60-4d92-9c36-338d7abc77dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119234452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3119234452
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1971251459
Short name T596
Test name
Test status
Simulation time 373142322 ps
CPU time 6.01 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:10:03 PM PDT 24
Peak memory 200168 kb
Host smart-1b8085a0-aefd-45c7-b280-a2584be2cc74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971251459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1971251459
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3069192601
Short name T95
Test name
Test status
Simulation time 197245005 ps
CPU time 0.85 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 199960 kb
Host smart-44bf8980-4213-43ce-a30e-bc4b088a5a5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069192601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3069192601
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.444134106
Short name T611
Test name
Test status
Simulation time 237008236 ps
CPU time 1.64 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 200240 kb
Host smart-eea5be1f-6cc7-42b6-83e4-5242c32a37de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444134106 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.444134106
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2026012421
Short name T98
Test name
Test status
Simulation time 64788614 ps
CPU time 0.7 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 198324 kb
Host smart-cef9ec0b-011c-446b-984d-19430dd821c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026012421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2026012421
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2193207101
Short name T582
Test name
Test status
Simulation time 15825082 ps
CPU time 0.65 seconds
Started Aug 06 07:10:00 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 195004 kb
Host smart-2d9a707a-b445-400d-8941-2be6dce41518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193207101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2193207101
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3662726562
Short name T623
Test name
Test status
Simulation time 423997619 ps
CPU time 2.33 seconds
Started Aug 06 07:10:01 PM PDT 24
Finished Aug 06 07:10:03 PM PDT 24
Peak memory 200168 kb
Host smart-ed18d89d-9146-4a49-9879-241857872b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662726562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3662726562
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3359680781
Short name T544
Test name
Test status
Simulation time 1050031414 ps
CPU time 2.94 seconds
Started Aug 06 07:09:53 PM PDT 24
Finished Aug 06 07:09:56 PM PDT 24
Peak memory 200116 kb
Host smart-4b4a41a9-806e-4eb4-a59c-ef75e9bf3a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359680781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3359680781
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1624603699
Short name T62
Test name
Test status
Simulation time 341990466 ps
CPU time 2.87 seconds
Started Aug 06 07:09:54 PM PDT 24
Finished Aug 06 07:09:57 PM PDT 24
Peak memory 200084 kb
Host smart-0ac7df03-d8a6-49f7-940b-7fbb5efceb82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624603699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1624603699
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2754033062
Short name T588
Test name
Test status
Simulation time 305020561 ps
CPU time 1.18 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 199992 kb
Host smart-8ea5542c-966f-44e0-9420-7c0dced92031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754033062 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2754033062
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3265014515
Short name T94
Test name
Test status
Simulation time 39919040 ps
CPU time 0.8 seconds
Started Aug 06 07:10:19 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 199648 kb
Host smart-b663c753-b169-4294-a189-ce6b0c1043de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265014515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3265014515
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.175299016
Short name T537
Test name
Test status
Simulation time 25644044 ps
CPU time 0.61 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 194988 kb
Host smart-4a9bca1d-7a84-43fa-9899-00a79bba07f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175299016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.175299016
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1482781453
Short name T102
Test name
Test status
Simulation time 53066561 ps
CPU time 1.12 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:17 PM PDT 24
Peak memory 198700 kb
Host smart-64ef7dec-a767-472c-9de9-0ff3ae47a148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482781453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1482781453
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1633072751
Short name T604
Test name
Test status
Simulation time 391604452 ps
CPU time 1.8 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 200144 kb
Host smart-0822d18b-a5ea-4df2-b8bd-46f3d1e32d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633072751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1633072751
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1886154632
Short name T114
Test name
Test status
Simulation time 470629438 ps
CPU time 4.19 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 199948 kb
Host smart-1ad4fd74-1e13-4050-ad2d-72dda349b495
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886154632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1886154632
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1750231526
Short name T531
Test name
Test status
Simulation time 870431560 ps
CPU time 2.44 seconds
Started Aug 06 07:10:20 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 208316 kb
Host smart-860f20e7-12ff-4593-be4b-f513dfafa3af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750231526 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1750231526
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3563865971
Short name T90
Test name
Test status
Simulation time 18178280 ps
CPU time 0.66 seconds
Started Aug 06 07:10:19 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 197868 kb
Host smart-bfb2fb4b-2f2e-433d-a3c1-45a3243efa21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563865971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3563865971
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2988199108
Short name T542
Test name
Test status
Simulation time 19150971 ps
CPU time 0.63 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:13 PM PDT 24
Peak memory 195248 kb
Host smart-9cb62d0c-9df5-4f44-863f-a4140894a938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988199108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2988199108
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3301411319
Short name T559
Test name
Test status
Simulation time 25500982 ps
CPU time 1.11 seconds
Started Aug 06 07:10:14 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 200152 kb
Host smart-852d3db0-5d7d-497a-b77b-75781c606b57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301411319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3301411319
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3843392778
Short name T567
Test name
Test status
Simulation time 398522890 ps
CPU time 2.03 seconds
Started Aug 06 07:10:19 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 200120 kb
Host smart-b8ff5022-b2b8-49ae-8aa3-b79e30609277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843392778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3843392778
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3977527903
Short name T615
Test name
Test status
Simulation time 1021080856 ps
CPU time 3.07 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 200096 kb
Host smart-779c3aec-2c99-4ca5-9ce3-059235111b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977527903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3977527903
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2335367736
Short name T549
Test name
Test status
Simulation time 129823329 ps
CPU time 1.42 seconds
Started Aug 06 07:10:14 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 200204 kb
Host smart-fc77b774-5c3a-42db-affe-c45cc2723675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335367736 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2335367736
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4236615806
Short name T100
Test name
Test status
Simulation time 211616838 ps
CPU time 0.68 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 197796 kb
Host smart-842fe68f-61bd-4831-96e4-e9a85dd4f2ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236615806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4236615806
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2938155461
Short name T650
Test name
Test status
Simulation time 47501903 ps
CPU time 0.58 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 195024 kb
Host smart-8d7480fe-789c-42ab-ae20-4cf742880e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938155461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2938155461
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.588403089
Short name T622
Test name
Test status
Simulation time 404760086 ps
CPU time 1.77 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:17 PM PDT 24
Peak memory 200204 kb
Host smart-492bc9a2-3b07-413d-aee1-0957e96481e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588403089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.588403089
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1345564234
Short name T551
Test name
Test status
Simulation time 100702530 ps
CPU time 2.14 seconds
Started Aug 06 07:10:20 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 200044 kb
Host smart-106ca974-f22e-44dc-8ea1-b1c1c30cbd6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345564234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1345564234
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2909148927
Short name T633
Test name
Test status
Simulation time 50781357 ps
CPU time 1.76 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 200128 kb
Host smart-995bd9bc-6072-4001-93c3-076141984eed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909148927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2909148927
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3847880499
Short name T65
Test name
Test status
Simulation time 133727744 ps
CPU time 2.55 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 200132 kb
Host smart-2df50527-dfae-48ac-a23a-618079aef465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847880499 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3847880499
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1575360647
Short name T107
Test name
Test status
Simulation time 19833129 ps
CPU time 0.73 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 198400 kb
Host smart-3c74829b-3263-4767-ae9b-d755d50e9f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575360647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1575360647
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2075623155
Short name T612
Test name
Test status
Simulation time 31889823 ps
CPU time 0.61 seconds
Started Aug 06 07:10:19 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 195032 kb
Host smart-c537ed13-1ab3-4d5c-85d7-21bdc24ac1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075623155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2075623155
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3008868573
Short name T626
Test name
Test status
Simulation time 148599112 ps
CPU time 2.37 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:20 PM PDT 24
Peak memory 200052 kb
Host smart-0d87a7e4-18dd-4aa6-a637-f31f9e5a7532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008868573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3008868573
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1885902103
Short name T575
Test name
Test status
Simulation time 64801112 ps
CPU time 3.5 seconds
Started Aug 06 07:10:12 PM PDT 24
Finished Aug 06 07:10:16 PM PDT 24
Peak memory 200164 kb
Host smart-f4c4188d-6ba3-48a8-96ba-2cfce85d7275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885902103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1885902103
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1747645669
Short name T113
Test name
Test status
Simulation time 314538764 ps
CPU time 1.84 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 200196 kb
Host smart-822c1cf3-83b5-412d-aaea-8c2f530ea77c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747645669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1747645669
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.274183369
Short name T603
Test name
Test status
Simulation time 779057329 ps
CPU time 3.28 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 215648 kb
Host smart-6c7b2bb7-cae0-44cb-80a0-b05337c7107d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274183369 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.274183369
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2408585777
Short name T586
Test name
Test status
Simulation time 24432235 ps
CPU time 0.82 seconds
Started Aug 06 07:10:12 PM PDT 24
Finished Aug 06 07:10:13 PM PDT 24
Peak memory 199100 kb
Host smart-c79149c1-3d06-48ab-bd74-55deb98bcf8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408585777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2408585777
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1534524529
Short name T555
Test name
Test status
Simulation time 76904140 ps
CPU time 0.6 seconds
Started Aug 06 07:10:20 PM PDT 24
Finished Aug 06 07:10:21 PM PDT 24
Peak memory 195092 kb
Host smart-de5eaf4c-a01c-461d-808e-05c9e2de3bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534524529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1534524529
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3329446374
Short name T634
Test name
Test status
Simulation time 36500427 ps
CPU time 1.74 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 200140 kb
Host smart-2aa83eaa-1e43-48d0-825d-e27fc8f0c385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329446374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3329446374
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.4094065653
Short name T637
Test name
Test status
Simulation time 447910437 ps
CPU time 2.77 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 200124 kb
Host smart-b3e155cf-debc-4300-8ad3-3bd62d161ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094065653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.4094065653
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1171923413
Short name T654
Test name
Test status
Simulation time 53235268 ps
CPU time 1.84 seconds
Started Aug 06 07:10:20 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 200040 kb
Host smart-ea678794-7f76-475a-856a-ff7349773a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171923413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1171923413
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4191711768
Short name T562
Test name
Test status
Simulation time 222407768193 ps
CPU time 1048.84 seconds
Started Aug 06 07:10:20 PM PDT 24
Finished Aug 06 07:27:49 PM PDT 24
Peak memory 216548 kb
Host smart-703b4e04-d4fa-42bf-9829-84b0f37bc8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191711768 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4191711768
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2418236177
Short name T106
Test name
Test status
Simulation time 43108588 ps
CPU time 0.7 seconds
Started Aug 06 07:10:24 PM PDT 24
Finished Aug 06 07:10:24 PM PDT 24
Peak memory 198456 kb
Host smart-b9df4793-531a-4867-83a3-8e854ad873b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418236177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2418236177
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2420818729
Short name T540
Test name
Test status
Simulation time 37841916 ps
CPU time 0.56 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:16 PM PDT 24
Peak memory 195076 kb
Host smart-63071302-c6ad-4c81-908f-544da255322d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420818729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2420818729
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4064560807
Short name T600
Test name
Test status
Simulation time 33449340 ps
CPU time 1.64 seconds
Started Aug 06 07:10:14 PM PDT 24
Finished Aug 06 07:10:16 PM PDT 24
Peak memory 199760 kb
Host smart-cd30803d-cde1-4be0-8dd3-72567b934d52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064560807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4064560807
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.809881293
Short name T655
Test name
Test status
Simulation time 699885869 ps
CPU time 3.72 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 200036 kb
Host smart-223d64d9-4647-4b6b-bf91-16cb75dc4a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809881293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.809881293
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4083232659
Short name T115
Test name
Test status
Simulation time 274948667 ps
CPU time 4.01 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:21 PM PDT 24
Peak memory 200224 kb
Host smart-7c019474-ea2c-4a58-995f-07990fc50e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083232659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4083232659
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1555598732
Short name T642
Test name
Test status
Simulation time 62793850845 ps
CPU time 900.58 seconds
Started Aug 06 07:10:16 PM PDT 24
Finished Aug 06 07:25:17 PM PDT 24
Peak memory 216728 kb
Host smart-847f09fe-1489-4673-81eb-041797947ad5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555598732 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1555598732
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2256362019
Short name T572
Test name
Test status
Simulation time 24143871 ps
CPU time 0.72 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 198240 kb
Host smart-d86cc677-4562-4a05-92f6-ff32a628da08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256362019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2256362019
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2058015345
Short name T576
Test name
Test status
Simulation time 28037886 ps
CPU time 0.62 seconds
Started Aug 06 07:10:16 PM PDT 24
Finished Aug 06 07:10:16 PM PDT 24
Peak memory 195020 kb
Host smart-61d8c46f-2b5c-4f08-ac42-4f2556de4d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058015345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2058015345
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2367101304
Short name T636
Test name
Test status
Simulation time 231689682 ps
CPU time 1.27 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 199984 kb
Host smart-56b90c50-7807-4abd-bbcc-1291dd498c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367101304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2367101304
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1677027847
Short name T529
Test name
Test status
Simulation time 57080449 ps
CPU time 2.88 seconds
Started Aug 06 07:10:16 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 200124 kb
Host smart-5ce3b587-1cd9-4f31-b561-586455b56c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677027847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1677027847
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3967294894
Short name T112
Test name
Test status
Simulation time 58569093 ps
CPU time 1.67 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:20 PM PDT 24
Peak memory 200096 kb
Host smart-0bc3c1d2-ed2f-4a44-8611-50b7d7635484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967294894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3967294894
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.884940024
Short name T541
Test name
Test status
Simulation time 308499611 ps
CPU time 2.37 seconds
Started Aug 06 07:10:22 PM PDT 24
Finished Aug 06 07:10:24 PM PDT 24
Peak memory 200176 kb
Host smart-8e48916b-dcbd-4164-9d2b-a321e44a4d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884940024 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.884940024
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3416944698
Short name T602
Test name
Test status
Simulation time 50279049 ps
CPU time 0.7 seconds
Started Aug 06 07:10:20 PM PDT 24
Finished Aug 06 07:10:21 PM PDT 24
Peak memory 198188 kb
Host smart-0abbda6d-2625-47e6-a25a-6a331cf16178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416944698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3416944698
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4028364675
Short name T618
Test name
Test status
Simulation time 60493137 ps
CPU time 0.59 seconds
Started Aug 06 07:10:16 PM PDT 24
Finished Aug 06 07:10:17 PM PDT 24
Peak memory 195024 kb
Host smart-6d05eab0-cb11-423b-b5eb-4baa52ea28c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028364675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4028364675
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3507011510
Short name T647
Test name
Test status
Simulation time 93051424 ps
CPU time 2.24 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:21 PM PDT 24
Peak memory 200060 kb
Host smart-27dc2846-8407-4d17-87d4-0e2329621f96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507011510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3507011510
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2222269788
Short name T560
Test name
Test status
Simulation time 51746617 ps
CPU time 1.46 seconds
Started Aug 06 07:10:15 PM PDT 24
Finished Aug 06 07:10:17 PM PDT 24
Peak memory 200228 kb
Host smart-446a07f1-f40c-4c7d-b252-0c0b111dbe9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222269788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2222269788
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.425877500
Short name T579
Test name
Test status
Simulation time 160076497 ps
CPU time 1.99 seconds
Started Aug 06 07:10:16 PM PDT 24
Finished Aug 06 07:10:18 PM PDT 24
Peak memory 200176 kb
Host smart-967b6235-b3f7-4a0e-acf2-4b3c62f37cab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425877500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.425877500
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1369775530
Short name T638
Test name
Test status
Simulation time 154872797 ps
CPU time 1.27 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 200260 kb
Host smart-0b2afa11-3bd7-4a01-9cf6-13a0b7983c79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369775530 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1369775530
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.365325279
Short name T91
Test name
Test status
Simulation time 115454678 ps
CPU time 0.82 seconds
Started Aug 06 07:10:21 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 199736 kb
Host smart-087c147a-19d7-4375-bf95-18c582237c14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365325279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.365325279
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2786950363
Short name T628
Test name
Test status
Simulation time 13868232 ps
CPU time 0.59 seconds
Started Aug 06 07:10:22 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 195096 kb
Host smart-d5c989d1-a5fb-430b-9051-47538ab8c040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786950363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2786950363
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3403823193
Short name T616
Test name
Test status
Simulation time 47514782 ps
CPU time 2.23 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:20 PM PDT 24
Peak memory 200152 kb
Host smart-05548071-538c-4427-8652-eb9cc3ce0c5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403823193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3403823193
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3548757877
Short name T594
Test name
Test status
Simulation time 36451251 ps
CPU time 1.77 seconds
Started Aug 06 07:10:12 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 200428 kb
Host smart-ed67486d-1af0-4722-8e34-93928e3e1484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548757877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3548757877
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2137511811
Short name T117
Test name
Test status
Simulation time 59914670 ps
CPU time 1.78 seconds
Started Aug 06 07:10:17 PM PDT 24
Finished Aug 06 07:10:19 PM PDT 24
Peak memory 200156 kb
Host smart-6939e8a6-ba17-4193-891b-e13de5ad9369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137511811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2137511811
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2181866162
Short name T605
Test name
Test status
Simulation time 157393781 ps
CPU time 1.21 seconds
Started Aug 06 07:10:12 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 200068 kb
Host smart-e964df49-8884-404c-85b2-4abbe5105209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181866162 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2181866162
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2546289553
Short name T631
Test name
Test status
Simulation time 115869131 ps
CPU time 0.81 seconds
Started Aug 06 07:10:22 PM PDT 24
Finished Aug 06 07:10:23 PM PDT 24
Peak memory 199588 kb
Host smart-22dddf07-937f-482e-bdcd-2f7d0ed3dca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546289553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2546289553
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.805934431
Short name T614
Test name
Test status
Simulation time 11761093 ps
CPU time 0.58 seconds
Started Aug 06 07:10:21 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 194996 kb
Host smart-8cf59eb1-20db-4574-a7b3-8272c10ce7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805934431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.805934431
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1973942389
Short name T613
Test name
Test status
Simulation time 49474724 ps
CPU time 2.12 seconds
Started Aug 06 07:10:21 PM PDT 24
Finished Aug 06 07:10:23 PM PDT 24
Peak memory 200064 kb
Host smart-e48589ed-9acb-4b74-a1fb-bfd5b152bd5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973942389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1973942389
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3671905834
Short name T610
Test name
Test status
Simulation time 964468301 ps
CPU time 4.27 seconds
Started Aug 06 07:10:18 PM PDT 24
Finished Aug 06 07:10:22 PM PDT 24
Peak memory 200128 kb
Host smart-bbba245d-1ebb-4071-ba18-91e782b1744f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671905834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3671905834
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3280360143
Short name T554
Test name
Test status
Simulation time 88777508 ps
CPU time 2.76 seconds
Started Aug 06 07:10:13 PM PDT 24
Finished Aug 06 07:10:16 PM PDT 24
Peak memory 200148 kb
Host smart-2563f0e5-605d-4919-8b82-dbd8ddf2e360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280360143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3280360143
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.744331235
Short name T99
Test name
Test status
Simulation time 162545495 ps
CPU time 3.06 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 199892 kb
Host smart-e0e44f18-601d-4a00-8bb0-5e80d1cd6714
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744331235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.744331235
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3558909617
Short name T587
Test name
Test status
Simulation time 426284709 ps
CPU time 5.31 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 200100 kb
Host smart-55e482f1-d730-486d-bae9-bc8bfad378d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558909617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3558909617
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3861511117
Short name T93
Test name
Test status
Simulation time 35050730 ps
CPU time 0.74 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 198476 kb
Host smart-d365b4d6-562c-4e98-a9b2-49518e1b1b5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861511117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3861511117
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1899096964
Short name T530
Test name
Test status
Simulation time 53615768 ps
CPU time 3.41 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 208380 kb
Host smart-880815b6-b7db-4867-bcc9-c9a523b65cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899096964 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1899096964
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2142932535
Short name T581
Test name
Test status
Simulation time 92888813 ps
CPU time 0.81 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:57 PM PDT 24
Peak memory 199392 kb
Host smart-698c647e-6204-4d93-9395-cb1429406c14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142932535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2142932535
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1694434457
Short name T568
Test name
Test status
Simulation time 35914677 ps
CPU time 0.56 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:55 PM PDT 24
Peak memory 194956 kb
Host smart-b14c2b37-a1a5-4fec-98ff-9b0a4aff7adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694434457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1694434457
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1657965768
Short name T627
Test name
Test status
Simulation time 168011783 ps
CPU time 1.8 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 200372 kb
Host smart-a30a20d5-9bc1-4a0c-9e36-df2fe0c82079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657965768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1657965768
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3620675532
Short name T651
Test name
Test status
Simulation time 56729684 ps
CPU time 1.54 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 200208 kb
Host smart-1c234c1f-61bb-4033-9144-e0e28d0bfd9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620675532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3620675532
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2996063547
Short name T574
Test name
Test status
Simulation time 164964696 ps
CPU time 3.19 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 200112 kb
Host smart-194534eb-abe4-453a-b636-36f3e2536ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996063547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2996063547
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1394533695
Short name T548
Test name
Test status
Simulation time 41974746 ps
CPU time 0.57 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 195036 kb
Host smart-d190bd7c-6700-447b-8c43-6637080fd6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394533695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1394533695
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4165452908
Short name T534
Test name
Test status
Simulation time 13449635 ps
CPU time 0.6 seconds
Started Aug 06 07:10:27 PM PDT 24
Finished Aug 06 07:10:28 PM PDT 24
Peak memory 195192 kb
Host smart-8799e00f-8478-4add-b7cd-72c2dab9e573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165452908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4165452908
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3014747063
Short name T550
Test name
Test status
Simulation time 26822939 ps
CPU time 0.62 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 195080 kb
Host smart-c409e443-f2af-425b-915f-132104d6cd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014747063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3014747063
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4266083807
Short name T535
Test name
Test status
Simulation time 50739139 ps
CPU time 0.6 seconds
Started Aug 06 07:10:30 PM PDT 24
Finished Aug 06 07:10:31 PM PDT 24
Peak memory 195052 kb
Host smart-4a7891f5-60ba-4467-b0ec-60bb8a631c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266083807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4266083807
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3094390673
Short name T617
Test name
Test status
Simulation time 58900472 ps
CPU time 0.66 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 195212 kb
Host smart-35f24104-e763-4756-a259-7ff8b37ae9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094390673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3094390673
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4084500698
Short name T578
Test name
Test status
Simulation time 37588558 ps
CPU time 0.61 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 195136 kb
Host smart-97d3b516-134b-43f8-9662-290c7629f362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084500698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4084500698
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1066729782
Short name T601
Test name
Test status
Simulation time 21569996 ps
CPU time 0.6 seconds
Started Aug 06 07:10:34 PM PDT 24
Finished Aug 06 07:10:35 PM PDT 24
Peak memory 195232 kb
Host smart-f5f89aff-64f6-41b9-83a5-6d5be9359ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066729782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1066729782
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4065206039
Short name T657
Test name
Test status
Simulation time 18612520 ps
CPU time 0.58 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:29 PM PDT 24
Peak memory 195144 kb
Host smart-1c488a9f-1e71-4ae1-aa9a-170280dcf6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065206039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4065206039
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3929225020
Short name T598
Test name
Test status
Simulation time 37712808 ps
CPU time 0.59 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 194876 kb
Host smart-dba6bcab-53b0-4601-a19a-898018d7d4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929225020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3929225020
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1937058460
Short name T585
Test name
Test status
Simulation time 27035995 ps
CPU time 0.61 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 195116 kb
Host smart-a4f6436f-b3d0-4335-9a0c-639ecc1c48fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937058460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1937058460
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1319290271
Short name T78
Test name
Test status
Simulation time 385695426 ps
CPU time 3.37 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 200024 kb
Host smart-c5576a5d-9061-4b9b-8a89-e5dd15660ff2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319290271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1319290271
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1189054578
Short name T652
Test name
Test status
Simulation time 1936292993 ps
CPU time 10.92 seconds
Started Aug 06 07:10:01 PM PDT 24
Finished Aug 06 07:10:12 PM PDT 24
Peak memory 200084 kb
Host smart-8bb2fe9f-7f37-43d2-8ac7-c2d018932320
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189054578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1189054578
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3262607622
Short name T577
Test name
Test status
Simulation time 101929973 ps
CPU time 0.86 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 199252 kb
Host smart-a1c514d2-3dac-4c63-9c86-f181c082ce70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262607622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3262607622
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2125499406
Short name T635
Test name
Test status
Simulation time 55283444 ps
CPU time 1.59 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 200132 kb
Host smart-c5a184d9-9cdf-4f5e-90a6-54baaf883ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125499406 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2125499406
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.844240440
Short name T89
Test name
Test status
Simulation time 36050481 ps
CPU time 0.69 seconds
Started Aug 06 07:10:00 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 198028 kb
Host smart-65f48ad4-9813-4655-bea9-f7058c1348f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844240440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.844240440
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2896624221
Short name T536
Test name
Test status
Simulation time 14246923 ps
CPU time 0.55 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 195028 kb
Host smart-b6ead4bb-54cb-4896-99b0-f6c311b9abb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896624221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2896624221
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.54242311
Short name T556
Test name
Test status
Simulation time 100883231 ps
CPU time 1.86 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 200092 kb
Host smart-1694981a-38a5-4b32-b678-779b70df9ca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54242311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_o
utstanding.54242311
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.439405080
Short name T595
Test name
Test status
Simulation time 162519666 ps
CPU time 4.59 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 200220 kb
Host smart-af5bd1dc-1ecc-4252-a545-247b60e1ed03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439405080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.439405080
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1545396067
Short name T609
Test name
Test status
Simulation time 1308484607 ps
CPU time 3.08 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 200172 kb
Host smart-16b092a8-d4f6-4bf3-997c-3b023b19b9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545396067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1545396067
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4162493194
Short name T570
Test name
Test status
Simulation time 27546918 ps
CPU time 0.59 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 194956 kb
Host smart-8bf9ec0e-f91a-4f7c-b41e-83fd7636bba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162493194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4162493194
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3352105187
Short name T619
Test name
Test status
Simulation time 68323804 ps
CPU time 0.61 seconds
Started Aug 06 07:10:30 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 195052 kb
Host smart-915a0b10-8b71-4e20-8efe-7a05980801e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352105187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3352105187
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3128333022
Short name T639
Test name
Test status
Simulation time 90412287 ps
CPU time 0.62 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 195004 kb
Host smart-f09bc9b7-1eda-43b9-997b-7ae61419e652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128333022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3128333022
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1079882216
Short name T546
Test name
Test status
Simulation time 47338501 ps
CPU time 0.58 seconds
Started Aug 06 07:10:30 PM PDT 24
Finished Aug 06 07:10:31 PM PDT 24
Peak memory 194964 kb
Host smart-704d0a71-ec93-49d6-a59b-e9dfafd028a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079882216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1079882216
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3650849048
Short name T621
Test name
Test status
Simulation time 61728436 ps
CPU time 0.64 seconds
Started Aug 06 07:10:33 PM PDT 24
Finished Aug 06 07:10:33 PM PDT 24
Peak memory 195140 kb
Host smart-33d7d427-4556-4ba9-816b-4372fd59a9d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650849048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3650849048
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.4205759040
Short name T547
Test name
Test status
Simulation time 44933803 ps
CPU time 0.61 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 195132 kb
Host smart-a2735ef5-0a69-4e80-931a-2abc3af3ea5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205759040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.4205759040
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2775121139
Short name T564
Test name
Test status
Simulation time 18691108 ps
CPU time 0.58 seconds
Started Aug 06 07:10:34 PM PDT 24
Finished Aug 06 07:10:35 PM PDT 24
Peak memory 195068 kb
Host smart-d0e0bd07-c7c9-4b8c-93f0-fd28861d320d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775121139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2775121139
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1969797911
Short name T565
Test name
Test status
Simulation time 47479304 ps
CPU time 0.59 seconds
Started Aug 06 07:10:32 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 194776 kb
Host smart-3355ac3a-5e0d-42e4-a794-60d746b2d3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969797911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1969797911
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1909240452
Short name T589
Test name
Test status
Simulation time 105601845 ps
CPU time 0.68 seconds
Started Aug 06 07:10:30 PM PDT 24
Finished Aug 06 07:10:31 PM PDT 24
Peak memory 195148 kb
Host smart-de72d6eb-313b-489e-84d7-fce963683317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909240452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1909240452
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3286795774
Short name T528
Test name
Test status
Simulation time 52721784 ps
CPU time 0.62 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 195084 kb
Host smart-36de3fcb-17d3-46a7-9386-cae2c9f81413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286795774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3286795774
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2998550783
Short name T606
Test name
Test status
Simulation time 242263020 ps
CPU time 5.22 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 199880 kb
Host smart-976717e8-fa0f-4a29-909a-8d00c79dba64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998550783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2998550783
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2630436254
Short name T630
Test name
Test status
Simulation time 431760326 ps
CPU time 5.21 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:10:03 PM PDT 24
Peak memory 200124 kb
Host smart-90adc663-99f6-477f-97b2-0cc76f22528e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630436254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2630436254
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3643569888
Short name T653
Test name
Test status
Simulation time 132867364 ps
CPU time 0.97 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 199936 kb
Host smart-cbecdce8-948c-4567-a1fb-3c5efd89f3eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643569888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3643569888
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3343023181
Short name T591
Test name
Test status
Simulation time 73442461181 ps
CPU time 46.1 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:45 PM PDT 24
Peak memory 216564 kb
Host smart-35f39540-6d77-4bb0-8033-f9618b380d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343023181 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3343023181
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3560766286
Short name T103
Test name
Test status
Simulation time 21926910 ps
CPU time 0.69 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:57 PM PDT 24
Peak memory 198008 kb
Host smart-12ba163a-3eb0-4ca7-935d-9d7a419b0b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560766286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3560766286
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3213247856
Short name T648
Test name
Test status
Simulation time 58445728 ps
CPU time 0.61 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:57 PM PDT 24
Peak memory 194988 kb
Host smart-e7d520d5-5054-49b6-996b-1d8c444174cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213247856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3213247856
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1140579517
Short name T584
Test name
Test status
Simulation time 1792041176 ps
CPU time 2.38 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 200196 kb
Host smart-d88b2d53-d201-44c9-b8aa-96595b124370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140579517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1140579517
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1568606128
Short name T558
Test name
Test status
Simulation time 103059579 ps
CPU time 2.29 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 200208 kb
Host smart-64fa1a6d-ecca-4503-8363-5d0f7c845232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568606128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1568606128
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3017020779
Short name T118
Test name
Test status
Simulation time 570846247 ps
CPU time 3.07 seconds
Started Aug 06 07:10:01 PM PDT 24
Finished Aug 06 07:10:04 PM PDT 24
Peak memory 200104 kb
Host smart-7a43e4a0-8e00-4090-9535-fd03c4b1ce65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017020779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3017020779
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2652228041
Short name T543
Test name
Test status
Simulation time 82650708 ps
CPU time 0.61 seconds
Started Aug 06 07:10:30 PM PDT 24
Finished Aug 06 07:10:30 PM PDT 24
Peak memory 195024 kb
Host smart-383d52b3-17bb-442e-9c31-a2af0da65d47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652228041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2652228041
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.596750140
Short name T641
Test name
Test status
Simulation time 56283047 ps
CPU time 0.61 seconds
Started Aug 06 07:10:29 PM PDT 24
Finished Aug 06 07:10:29 PM PDT 24
Peak memory 195060 kb
Host smart-d911ec9d-1869-4d61-aaff-0fcc91865340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596750140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.596750140
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.435723665
Short name T557
Test name
Test status
Simulation time 12154380 ps
CPU time 0.58 seconds
Started Aug 06 07:10:32 PM PDT 24
Finished Aug 06 07:10:33 PM PDT 24
Peak memory 195084 kb
Host smart-1b01b332-1569-4d10-9df1-1715588fb78d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435723665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.435723665
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2497434160
Short name T607
Test name
Test status
Simulation time 18015868 ps
CPU time 0.55 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 194964 kb
Host smart-950d11b5-e5d2-4676-b89c-fbde5e2a3b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497434160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2497434160
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2310157033
Short name T527
Test name
Test status
Simulation time 43418516 ps
CPU time 0.62 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 195052 kb
Host smart-4eb8ff23-ce16-4f9e-b34f-f0d31e99ec98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310157033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2310157033
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1878604175
Short name T552
Test name
Test status
Simulation time 33126183 ps
CPU time 0.59 seconds
Started Aug 06 07:10:34 PM PDT 24
Finished Aug 06 07:10:34 PM PDT 24
Peak memory 195080 kb
Host smart-3ef13016-42b4-4de0-acf2-f9badaac67ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878604175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1878604175
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2236316779
Short name T632
Test name
Test status
Simulation time 13887011 ps
CPU time 0.59 seconds
Started Aug 06 07:10:33 PM PDT 24
Finished Aug 06 07:10:34 PM PDT 24
Peak memory 195020 kb
Host smart-87c65067-76d8-434e-b660-503bc60ca653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236316779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2236316779
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.625589202
Short name T538
Test name
Test status
Simulation time 137011979 ps
CPU time 0.6 seconds
Started Aug 06 07:10:34 PM PDT 24
Finished Aug 06 07:10:35 PM PDT 24
Peak memory 195180 kb
Host smart-29211a45-56ab-4c6d-8111-d05c80b47730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625589202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.625589202
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2074691728
Short name T608
Test name
Test status
Simulation time 22262531 ps
CPU time 0.58 seconds
Started Aug 06 07:10:31 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 195044 kb
Host smart-a9699a20-33b0-4f48-9f15-742f95018549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074691728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2074691728
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2867978354
Short name T561
Test name
Test status
Simulation time 44814833 ps
CPU time 0.59 seconds
Started Aug 06 07:10:32 PM PDT 24
Finished Aug 06 07:10:32 PM PDT 24
Peak memory 194828 kb
Host smart-de554d63-9412-4427-8e87-b5dc2ab90696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867978354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2867978354
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.644296922
Short name T644
Test name
Test status
Simulation time 261792294 ps
CPU time 1.57 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 200148 kb
Host smart-8ad97df3-1731-419c-a1a3-d377ff7e23e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644296922 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.644296922
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1350702252
Short name T566
Test name
Test status
Simulation time 65017555 ps
CPU time 0.71 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:56 PM PDT 24
Peak memory 198544 kb
Host smart-d42e5ddb-ecb6-4c84-bee5-58c80f97f206
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350702252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1350702252
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3020548459
Short name T573
Test name
Test status
Simulation time 14462342 ps
CPU time 0.6 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 195120 kb
Host smart-6ecfecab-ba6b-4dee-bc86-c41517cbedc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020548459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3020548459
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2112550822
Short name T105
Test name
Test status
Simulation time 1239159772 ps
CPU time 1.7 seconds
Started Aug 06 07:10:03 PM PDT 24
Finished Aug 06 07:10:04 PM PDT 24
Peak memory 200128 kb
Host smart-cceb8295-9cb8-4956-8e99-7a07916bbb75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112550822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2112550822
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1126626263
Short name T580
Test name
Test status
Simulation time 116874933 ps
CPU time 1.6 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 200184 kb
Host smart-60e2eace-0de5-4115-b433-1e3122360064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126626263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1126626263
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4224695269
Short name T533
Test name
Test status
Simulation time 32554068 ps
CPU time 2.17 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 200020 kb
Host smart-44979c60-d069-4c09-b447-4f82297d2c3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224695269 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4224695269
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2536437356
Short name T583
Test name
Test status
Simulation time 63155541 ps
CPU time 0.69 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:56 PM PDT 24
Peak memory 198160 kb
Host smart-04934014-92b9-4f06-96f1-370cf55514d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536437356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2536437356
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1344713013
Short name T597
Test name
Test status
Simulation time 15531058 ps
CPU time 0.61 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 195068 kb
Host smart-18ea0507-fe5f-425e-a0f2-6b62e9d39503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344713013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1344713013
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.156161277
Short name T101
Test name
Test status
Simulation time 371301812 ps
CPU time 1.71 seconds
Started Aug 06 07:10:02 PM PDT 24
Finished Aug 06 07:10:04 PM PDT 24
Peak memory 200112 kb
Host smart-98ce7226-67e6-4d02-9276-7766212a7d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156161277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.156161277
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1172599588
Short name T643
Test name
Test status
Simulation time 70508549 ps
CPU time 1.68 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 200120 kb
Host smart-818e57f2-6a72-4da8-abcb-7de687b552dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172599588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1172599588
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1207436914
Short name T592
Test name
Test status
Simulation time 24656159 ps
CPU time 1.39 seconds
Started Aug 06 07:10:00 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 200200 kb
Host smart-a3f548cc-3ec1-480a-8ae3-65067dbfba2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207436914 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1207436914
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2549912442
Short name T593
Test name
Test status
Simulation time 35187709 ps
CPU time 0.69 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 197908 kb
Host smart-7be109bc-3452-4c63-b14c-29445258eed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549912442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2549912442
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.135922954
Short name T563
Test name
Test status
Simulation time 21909393 ps
CPU time 0.58 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:56 PM PDT 24
Peak memory 194992 kb
Host smart-40e53d4f-38eb-4205-91e9-1abb44685a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135922954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.135922954
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.912810242
Short name T569
Test name
Test status
Simulation time 85335510 ps
CPU time 1.13 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 199812 kb
Host smart-ff47f406-7a89-412e-9d95-9febf1d5c8e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912810242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.912810242
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1181101383
Short name T532
Test name
Test status
Simulation time 369335515 ps
CPU time 2.19 seconds
Started Aug 06 07:10:00 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 200128 kb
Host smart-622cb4ff-aa91-4f27-9f30-d2c625ad2231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181101383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1181101383
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2164471250
Short name T120
Test name
Test status
Simulation time 286002524 ps
CPU time 4.41 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:10:02 PM PDT 24
Peak memory 200040 kb
Host smart-29d62c48-add1-458f-83fd-bd8c78f8c1f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164471250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2164471250
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2538539206
Short name T620
Test name
Test status
Simulation time 253887363619 ps
CPU time 507.06 seconds
Started Aug 06 07:09:57 PM PDT 24
Finished Aug 06 07:18:24 PM PDT 24
Peak memory 216196 kb
Host smart-f18ebc04-4f6c-4b4d-a889-4769781fc45e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538539206 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2538539206
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1314760713
Short name T599
Test name
Test status
Simulation time 13476051 ps
CPU time 0.71 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:56 PM PDT 24
Peak memory 198080 kb
Host smart-b2fd6959-eed5-4c22-b97b-3e68e20dce5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314760713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1314760713
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.54000974
Short name T539
Test name
Test status
Simulation time 48966803 ps
CPU time 0.58 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 194960 kb
Host smart-840c04ab-ab7f-4a9e-99ed-896dc82964d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54000974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.54000974
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.902815808
Short name T571
Test name
Test status
Simulation time 194292949 ps
CPU time 2.25 seconds
Started Aug 06 07:09:55 PM PDT 24
Finished Aug 06 07:09:57 PM PDT 24
Peak memory 200056 kb
Host smart-21b115f2-50d5-40ef-8231-95fed98c9e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902815808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.902815808
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2317442831
Short name T649
Test name
Test status
Simulation time 88830174 ps
CPU time 2.2 seconds
Started Aug 06 07:09:56 PM PDT 24
Finished Aug 06 07:09:58 PM PDT 24
Peak memory 200144 kb
Host smart-4a91110e-c2c1-4c75-9419-67317d77dab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317442831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2317442831
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2895300997
Short name T640
Test name
Test status
Simulation time 120726046 ps
CPU time 2.25 seconds
Started Aug 06 07:10:12 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 200240 kb
Host smart-edba9acd-1554-4028-ab6d-976e8ec98f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895300997 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2895300997
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3675967201
Short name T629
Test name
Test status
Simulation time 23898073 ps
CPU time 0.7 seconds
Started Aug 06 07:10:14 PM PDT 24
Finished Aug 06 07:10:15 PM PDT 24
Peak memory 197692 kb
Host smart-6721d6cd-6f81-45be-9ebf-5dfbccd100b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675967201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3675967201
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2483474613
Short name T645
Test name
Test status
Simulation time 14486396 ps
CPU time 0.6 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:09:59 PM PDT 24
Peak memory 195028 kb
Host smart-a0dceb7e-d8b1-490b-a577-ad5dded7b4d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483474613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2483474613
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1711243343
Short name T624
Test name
Test status
Simulation time 85561455 ps
CPU time 1.81 seconds
Started Aug 06 07:10:12 PM PDT 24
Finished Aug 06 07:10:14 PM PDT 24
Peak memory 200172 kb
Host smart-a4756f32-0600-417b-a235-a94cb9b0b24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711243343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1711243343
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.627619203
Short name T590
Test name
Test status
Simulation time 102783838 ps
CPU time 2.22 seconds
Started Aug 06 07:09:58 PM PDT 24
Finished Aug 06 07:10:01 PM PDT 24
Peak memory 200144 kb
Host smart-4775afa5-bf53-44a0-b4b4-f1314dc0ceab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627619203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.627619203
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.515870627
Short name T121
Test name
Test status
Simulation time 63698537 ps
CPU time 1.67 seconds
Started Aug 06 07:09:59 PM PDT 24
Finished Aug 06 07:10:00 PM PDT 24
Peak memory 199996 kb
Host smart-2cb71b15-d285-49aa-bb54-fe52ae397437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515870627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.515870627
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2930341725
Short name T309
Test name
Test status
Simulation time 90966693 ps
CPU time 0.59 seconds
Started Aug 06 07:14:26 PM PDT 24
Finished Aug 06 07:14:27 PM PDT 24
Peak memory 196112 kb
Host smart-ab943ad9-7150-4424-90b8-7f58efcd768b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930341725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2930341725
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3750211152
Short name T517
Test name
Test status
Simulation time 5961071359 ps
CPU time 30.94 seconds
Started Aug 06 07:14:18 PM PDT 24
Finished Aug 06 07:14:49 PM PDT 24
Peak memory 199992 kb
Host smart-49a1e397-97b7-496e-9bea-f5244bfca05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750211152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3750211152
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.164563617
Short name T436
Test name
Test status
Simulation time 7998820620 ps
CPU time 59.33 seconds
Started Aug 06 07:14:22 PM PDT 24
Finished Aug 06 07:15:21 PM PDT 24
Peak memory 199960 kb
Host smart-bb03187c-8b66-4b8d-b110-5b0c2579c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164563617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.164563617
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.535634924
Short name T343
Test name
Test status
Simulation time 10366078267 ps
CPU time 498.94 seconds
Started Aug 06 07:14:22 PM PDT 24
Finished Aug 06 07:22:41 PM PDT 24
Peak memory 630132 kb
Host smart-b00844ff-6109-467a-9774-2f9c6f3abf18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535634924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.535634924
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1576667314
Short name T411
Test name
Test status
Simulation time 1393568430 ps
CPU time 19.57 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:14:43 PM PDT 24
Peak memory 199912 kb
Host smart-402cde10-8d56-4241-ad49-7a4a8fe98767
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576667314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1576667314
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.394019934
Short name T80
Test name
Test status
Simulation time 35459960107 ps
CPU time 154.08 seconds
Started Aug 06 07:14:17 PM PDT 24
Finished Aug 06 07:16:51 PM PDT 24
Peak memory 199896 kb
Host smart-a569c529-02a5-4a9b-b00b-0c343ea3df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394019934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.394019934
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.691394095
Short name T51
Test name
Test status
Simulation time 77956059 ps
CPU time 0.81 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:14:24 PM PDT 24
Peak memory 218396 kb
Host smart-ff99a9d4-18cc-4595-b056-ee403d2516b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691394095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.691394095
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1875538914
Short name T273
Test name
Test status
Simulation time 683196669 ps
CPU time 7.11 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:14:31 PM PDT 24
Peak memory 199904 kb
Host smart-2917f8b4-0bf5-4108-b3c4-113d5003e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875538914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1875538914
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1470858375
Short name T251
Test name
Test status
Simulation time 24594213140 ps
CPU time 1286.8 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:35:48 PM PDT 24
Peak memory 727980 kb
Host smart-48298e1d-0d14-40d7-92d4-f16b39ce59f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470858375 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1470858375
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3043737442
Short name T9
Test name
Test status
Simulation time 36729683268 ps
CPU time 1116.93 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:33:01 PM PDT 24
Peak memory 750436 kb
Host smart-452a47aa-7c82-4542-a057-d489ccfb10c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043737442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3043737442
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.894857712
Short name T188
Test name
Test status
Simulation time 1078107435 ps
CPU time 38.98 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:15:02 PM PDT 24
Peak memory 199764 kb
Host smart-b3365504-9c0b-43f3-bd61-ddafa05629c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=894857712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.894857712
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3086788021
Short name T33
Test name
Test status
Simulation time 13604894862 ps
CPU time 75.33 seconds
Started Aug 06 07:14:22 PM PDT 24
Finished Aug 06 07:15:37 PM PDT 24
Peak memory 199880 kb
Host smart-9ccc534e-9c61-40a6-9a97-09e8c3a6a72d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3086788021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3086788021
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.4245260365
Short name T211
Test name
Test status
Simulation time 3056970182 ps
CPU time 120.26 seconds
Started Aug 06 07:14:20 PM PDT 24
Finished Aug 06 07:16:21 PM PDT 24
Peak memory 199892 kb
Host smart-8939fe4a-7b61-4b2d-a6c6-f14f0ec7fcb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4245260365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.4245260365
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3459620746
Short name T494
Test name
Test status
Simulation time 10119866175 ps
CPU time 570.16 seconds
Started Aug 06 07:14:17 PM PDT 24
Finished Aug 06 07:23:47 PM PDT 24
Peak memory 199804 kb
Host smart-44290c4f-6d48-449a-84e7-ee2b53acc63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3459620746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3459620746
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3046404787
Short name T37
Test name
Test status
Simulation time 133842173173 ps
CPU time 2321.63 seconds
Started Aug 06 07:14:16 PM PDT 24
Finished Aug 06 07:52:58 PM PDT 24
Peak memory 215672 kb
Host smart-626e98b5-9b3d-488d-86e9-6fd5715ae7c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3046404787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3046404787
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3334127131
Short name T445
Test name
Test status
Simulation time 694888267486 ps
CPU time 2277.39 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:52:19 PM PDT 24
Peak memory 215992 kb
Host smart-82dcb44d-227b-46b7-8595-b7c76b42f2f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3334127131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3334127131
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.631064227
Short name T392
Test name
Test status
Simulation time 4837050619 ps
CPU time 42.96 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:15:04 PM PDT 24
Peak memory 199800 kb
Host smart-73c73416-2fb8-4811-b9b1-a3163cd8414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631064227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.631064227
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3651066880
Short name T257
Test name
Test status
Simulation time 54549763 ps
CPU time 0.57 seconds
Started Aug 06 07:14:17 PM PDT 24
Finished Aug 06 07:14:18 PM PDT 24
Peak memory 196632 kb
Host smart-b426f2c5-1730-4b42-bc17-bb81a3d68b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651066880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3651066880
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.213266901
Short name T366
Test name
Test status
Simulation time 36450320 ps
CPU time 1.93 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:14:26 PM PDT 24
Peak memory 199704 kb
Host smart-a87fa59c-79a9-4310-b4bf-a9f735430574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213266901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.213266901
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1210624574
Short name T458
Test name
Test status
Simulation time 356676545 ps
CPU time 4.16 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:14:28 PM PDT 24
Peak memory 199644 kb
Host smart-d90285d0-8d61-4255-9a34-c89de487f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210624574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1210624574
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3112186436
Short name T243
Test name
Test status
Simulation time 180384669 ps
CPU time 15.09 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:14:39 PM PDT 24
Peak memory 229968 kb
Host smart-6ed9f104-f916-4589-88f5-2cf5583bed98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112186436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3112186436
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1070789129
Short name T447
Test name
Test status
Simulation time 3033449650 ps
CPU time 39.32 seconds
Started Aug 06 07:14:26 PM PDT 24
Finished Aug 06 07:15:06 PM PDT 24
Peak memory 199808 kb
Host smart-4f53ede4-08c8-4ea1-9dc0-b31dcb2f73b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070789129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1070789129
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3728185293
Short name T422
Test name
Test status
Simulation time 2131680884 ps
CPU time 116.39 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:16:20 PM PDT 24
Peak memory 199508 kb
Host smart-2d1f4696-d030-455e-a712-2f224988dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728185293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3728185293
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.550331335
Short name T434
Test name
Test status
Simulation time 2321117739 ps
CPU time 13.87 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:14:37 PM PDT 24
Peak memory 199720 kb
Host smart-eca286a1-2cbd-4287-b1a6-878f6e640697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550331335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.550331335
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1594033970
Short name T81
Test name
Test status
Simulation time 56430990188 ps
CPU time 960.64 seconds
Started Aug 06 07:14:25 PM PDT 24
Finished Aug 06 07:30:26 PM PDT 24
Peak memory 468016 kb
Host smart-6d58c7d8-9592-4416-9ac5-11ea7a0bd782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594033970 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1594033970
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3860278648
Short name T229
Test name
Test status
Simulation time 4633195844 ps
CPU time 51.34 seconds
Started Aug 06 07:14:17 PM PDT 24
Finished Aug 06 07:15:08 PM PDT 24
Peak memory 199864 kb
Host smart-8b4bde34-52e8-4293-b7fa-062e062b0fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3860278648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3860278648
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2757969427
Short name T269
Test name
Test status
Simulation time 1761013128 ps
CPU time 62.02 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:15:26 PM PDT 24
Peak memory 199772 kb
Host smart-22f77576-717f-4121-847c-c21172834515
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2757969427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2757969427
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.495480425
Short name T439
Test name
Test status
Simulation time 8626573611 ps
CPU time 133.7 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:16:37 PM PDT 24
Peak memory 199944 kb
Host smart-1f3e2537-4d16-4045-8ba2-6c77cf94efb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=495480425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.495480425
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1837987610
Short name T214
Test name
Test status
Simulation time 34340467155 ps
CPU time 623.54 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:24:47 PM PDT 24
Peak memory 199800 kb
Host smart-c9404eef-bd08-473c-986d-3196db6ec9b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1837987610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1837987610
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1319890049
Short name T43
Test name
Test status
Simulation time 414214239531 ps
CPU time 2140.68 seconds
Started Aug 06 07:14:25 PM PDT 24
Finished Aug 06 07:50:07 PM PDT 24
Peak memory 215968 kb
Host smart-c29b4cc8-aac5-4558-b683-fdbededc7671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1319890049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1319890049
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.1381610165
Short name T122
Test name
Test status
Simulation time 203504518565 ps
CPU time 2519.03 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:56:29 PM PDT 24
Peak memory 216092 kb
Host smart-de4814b6-8784-41c3-9f24-d472887009a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1381610165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1381610165
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2866146209
Short name T455
Test name
Test status
Simulation time 5968401498 ps
CPU time 132.05 seconds
Started Aug 06 07:14:25 PM PDT 24
Finished Aug 06 07:16:37 PM PDT 24
Peak memory 199924 kb
Host smart-5fd02d45-738e-4305-95cf-00f3d0a8b33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866146209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2866146209
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2257374940
Short name T404
Test name
Test status
Simulation time 153416703 ps
CPU time 0.6 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:14:51 PM PDT 24
Peak memory 195912 kb
Host smart-15fa4a48-4216-4fd8-b070-0a6fc879d235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257374940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2257374940
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3717457301
Short name T153
Test name
Test status
Simulation time 31154069418 ps
CPU time 82.65 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:16:13 PM PDT 24
Peak memory 208136 kb
Host smart-db5bc7ab-c869-424f-b583-48f561f7a62b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3717457301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3717457301
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2355223626
Short name T511
Test name
Test status
Simulation time 130235614 ps
CPU time 6.41 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:14:57 PM PDT 24
Peak memory 199800 kb
Host smart-d0c4dcf9-5149-4f05-8e9a-9cf6bb185d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355223626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2355223626
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_error.1212419507
Short name T347
Test name
Test status
Simulation time 46642903534 ps
CPU time 41.88 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 07:15:34 PM PDT 24
Peak memory 199876 kb
Host smart-20393596-5338-4646-9a79-2a1973a68d3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212419507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1212419507
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4247792196
Short name T70
Test name
Test status
Simulation time 62917363463 ps
CPU time 215.29 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:18:25 PM PDT 24
Peak memory 199892 kb
Host smart-cb8e0ae3-7ef3-4350-989d-9f81200d64b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247792196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4247792196
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4062757150
Short name T405
Test name
Test status
Simulation time 450958471 ps
CPU time 4.02 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:14:54 PM PDT 24
Peak memory 199804 kb
Host smart-2b1be51e-424b-4296-b7f2-23c9d8772937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062757150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4062757150
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.123438565
Short name T76
Test name
Test status
Simulation time 316810861874 ps
CPU time 317.97 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:20:09 PM PDT 24
Peak memory 215532 kb
Host smart-0bdf9030-a80e-4201-90d3-ea5c62bd39d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123438565 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.123438565
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1730504252
Short name T397
Test name
Test status
Simulation time 389547814 ps
CPU time 19.69 seconds
Started Aug 06 07:14:49 PM PDT 24
Finished Aug 06 07:15:09 PM PDT 24
Peak memory 199836 kb
Host smart-2e9554b5-4523-45dc-8ff1-14d7e12d8d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730504252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1730504252
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3748769562
Short name T441
Test name
Test status
Simulation time 462800748 ps
CPU time 26.54 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:15:17 PM PDT 24
Peak memory 199748 kb
Host smart-985bb30a-1d00-4167-8121-729c30cae360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748769562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3748769562
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4149180969
Short name T175
Test name
Test status
Simulation time 49397445835 ps
CPU time 33.79 seconds
Started Aug 06 07:14:53 PM PDT 24
Finished Aug 06 07:15:26 PM PDT 24
Peak memory 199696 kb
Host smart-965453c8-f0d0-4977-9a23-2d9b51f677fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149180969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4149180969
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.149152853
Short name T387
Test name
Test status
Simulation time 7642987950 ps
CPU time 1557.74 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:40:48 PM PDT 24
Peak memory 740364 kb
Host smart-e6ed683f-4183-43e5-a08b-4353dcce4b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149152853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.149152853
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1039314956
Short name T46
Test name
Test status
Simulation time 5670330935 ps
CPU time 98.73 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:16:47 PM PDT 24
Peak memory 199816 kb
Host smart-a0465bff-fb57-490a-97d8-e0bad3266234
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039314956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1039314956
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3968604109
Short name T346
Test name
Test status
Simulation time 21995898403 ps
CPU time 207.56 seconds
Started Aug 06 07:14:48 PM PDT 24
Finished Aug 06 07:18:16 PM PDT 24
Peak memory 199972 kb
Host smart-c18dab64-0d8d-4d37-8895-bf4c2e80f46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968604109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3968604109
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2182407804
Short name T429
Test name
Test status
Simulation time 999715391 ps
CPU time 12.05 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 07:15:04 PM PDT 24
Peak memory 199904 kb
Host smart-40082eb1-2e30-40f7-95c9-7ab9976aa197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182407804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2182407804
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1060103693
Short name T522
Test name
Test status
Simulation time 103830805291 ps
CPU time 733.58 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:27:24 PM PDT 24
Peak memory 626268 kb
Host smart-c547907a-a6f1-4da9-96bb-f736729d1680
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060103693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1060103693
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2771352187
Short name T40
Test name
Test status
Simulation time 7915895295 ps
CPU time 105.27 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 199904 kb
Host smart-8c544dea-acac-4752-9cc1-e7be10fddf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771352187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2771352187
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2650826411
Short name T236
Test name
Test status
Simulation time 22034200 ps
CPU time 0.58 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:15:09 PM PDT 24
Peak memory 194940 kb
Host smart-5516e989-a50e-43d2-8e31-2ba248efd5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650826411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2650826411
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3249076367
Short name T391
Test name
Test status
Simulation time 1025833682 ps
CPU time 57.21 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:16:04 PM PDT 24
Peak memory 199760 kb
Host smart-fcc9c9dd-d26a-458e-b219-428fa59f7987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249076367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3249076367
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1110697335
Short name T245
Test name
Test status
Simulation time 3186632305 ps
CPU time 44.55 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:53 PM PDT 24
Peak memory 199832 kb
Host smart-22a11596-fbac-4836-8104-1348cb722210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110697335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1110697335
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1702069317
Short name T137
Test name
Test status
Simulation time 19650101300 ps
CPU time 880.7 seconds
Started Aug 06 07:15:11 PM PDT 24
Finished Aug 06 07:29:51 PM PDT 24
Peak memory 705452 kb
Host smart-b7d6f0fc-5ed7-4aa4-ae09-51955b562e1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702069317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1702069317
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.4126253893
Short name T176
Test name
Test status
Simulation time 11402224364 ps
CPU time 71.33 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:16:21 PM PDT 24
Peak memory 199924 kb
Host smart-bd5c50a7-bcd1-4903-8340-09ff2d28cb3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126253893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.4126253893
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1893097519
Short name T502
Test name
Test status
Simulation time 10530399010 ps
CPU time 164.35 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:17:52 PM PDT 24
Peak memory 216164 kb
Host smart-e2293599-7568-435b-8208-d67320adda17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893097519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1893097519
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1548666248
Short name T250
Test name
Test status
Simulation time 602300322 ps
CPU time 10.82 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:15:21 PM PDT 24
Peak memory 199920 kb
Host smart-60012ce8-c80b-4d7a-8010-507b3ccce031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548666248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1548666248
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.725518672
Short name T217
Test name
Test status
Simulation time 29243811 ps
CPU time 0.64 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:15:07 PM PDT 24
Peak memory 195652 kb
Host smart-f6014889-22bd-42bc-85bf-92aa0685f660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725518672 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.725518672
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2032746288
Short name T21
Test name
Test status
Simulation time 4475168803 ps
CPU time 61.14 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:11 PM PDT 24
Peak memory 199920 kb
Host smart-f2b5b5ae-bfbe-441e-bbf4-5b8599282e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032746288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2032746288
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2278532010
Short name T352
Test name
Test status
Simulation time 22363978 ps
CPU time 0.58 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:15:07 PM PDT 24
Peak memory 195932 kb
Host smart-75dfa800-7aab-47c4-a57c-b380895324ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278532010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2278532010
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2405115183
Short name T326
Test name
Test status
Simulation time 274811951 ps
CPU time 14.47 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:15:21 PM PDT 24
Peak memory 199880 kb
Host smart-10e9c422-c13c-419e-9793-b29de5ad3a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405115183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2405115183
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1864072495
Short name T416
Test name
Test status
Simulation time 5921570480 ps
CPU time 26.09 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:34 PM PDT 24
Peak memory 216176 kb
Host smart-a7adc33d-8ccb-46e6-a1c5-6be9e1e131e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864072495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1864072495
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2614343664
Short name T487
Test name
Test status
Simulation time 13736769417 ps
CPU time 503.92 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:23:32 PM PDT 24
Peak memory 641164 kb
Host smart-4ab021b7-f4d6-4988-8056-1f680d67547b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614343664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2614343664
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3770160640
Short name T360
Test name
Test status
Simulation time 24088072693 ps
CPU time 117.33 seconds
Started Aug 06 07:15:05 PM PDT 24
Finished Aug 06 07:17:02 PM PDT 24
Peak memory 199892 kb
Host smart-b9ceaa01-ac58-447a-ad06-d5f4a3cf6963
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770160640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3770160640
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1864340123
Short name T501
Test name
Test status
Simulation time 544362973 ps
CPU time 7.78 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:15:15 PM PDT 24
Peak memory 199700 kb
Host smart-c12bf5bf-359b-43c6-85f5-9edcfc5e638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864340123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1864340123
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.761026798
Short name T5
Test name
Test status
Simulation time 1113457147 ps
CPU time 9.06 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:15:16 PM PDT 24
Peak memory 199668 kb
Host smart-499c1098-e78b-4a8e-8896-e6ae8f35c939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761026798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.761026798
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3861882347
Short name T24
Test name
Test status
Simulation time 23796808073 ps
CPU time 2558.72 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:57:47 PM PDT 24
Peak memory 759996 kb
Host smart-c44bae3c-9197-4880-82b5-b7ba19579152
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861882347 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3861882347
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3343893162
Short name T476
Test name
Test status
Simulation time 47718024743 ps
CPU time 145.03 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:17:34 PM PDT 24
Peak memory 199872 kb
Host smart-a81928a5-b618-49ea-80a7-54b531970b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343893162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3343893162
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3026599770
Short name T241
Test name
Test status
Simulation time 30659320 ps
CPU time 0.6 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:15:07 PM PDT 24
Peak memory 195904 kb
Host smart-b640c62c-d2de-4048-82aa-7c35b3572e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026599770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3026599770
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3043953165
Short name T240
Test name
Test status
Simulation time 2876671064 ps
CPU time 83.71 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:34 PM PDT 24
Peak memory 199900 kb
Host smart-2f69fd45-dc7c-4384-a1b9-e29cf456c6da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043953165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3043953165
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.382114055
Short name T169
Test name
Test status
Simulation time 2613631220 ps
CPU time 50.41 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:15:56 PM PDT 24
Peak memory 199896 kb
Host smart-20e3a75f-7f1c-4096-aeae-d82ff022728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382114055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.382114055
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4125303730
Short name T213
Test name
Test status
Simulation time 18565421443 ps
CPU time 1103.1 seconds
Started Aug 06 07:15:05 PM PDT 24
Finished Aug 06 07:33:28 PM PDT 24
Peak memory 764516 kb
Host smart-5854203e-4e9d-44cc-8234-bd7435b6be5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125303730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4125303730
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3108361880
Short name T219
Test name
Test status
Simulation time 8396892235 ps
CPU time 121.57 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:17:10 PM PDT 24
Peak memory 199756 kb
Host smart-a13d2034-83ef-4cf8-a98b-35ffd944d379
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108361880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3108361880
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2094266680
Short name T378
Test name
Test status
Simulation time 5688049144 ps
CPU time 71.82 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:16:20 PM PDT 24
Peak memory 199892 kb
Host smart-20e9d21c-c202-4efc-b677-1e8e95dac7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094266680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2094266680
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1834428535
Short name T322
Test name
Test status
Simulation time 1501698237 ps
CPU time 8.87 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:15:16 PM PDT 24
Peak memory 199836 kb
Host smart-5cb486bd-f5e8-4d96-a48e-6416f0808468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834428535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1834428535
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3009308448
Short name T108
Test name
Test status
Simulation time 2906810231 ps
CPU time 106.8 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 199924 kb
Host smart-28c8d348-9693-4588-b656-497afcae4174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009308448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3009308448
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1213057543
Short name T45
Test name
Test status
Simulation time 35858814 ps
CPU time 0.58 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:15:08 PM PDT 24
Peak memory 195908 kb
Host smart-2b45f615-3e7e-4a40-98e1-f15a7961e90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213057543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1213057543
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.86745577
Short name T22
Test name
Test status
Simulation time 1381149021 ps
CPU time 15.31 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:15:24 PM PDT 24
Peak memory 199756 kb
Host smart-6451ec25-9cd9-4150-9ce4-1aab613d9283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86745577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.86745577
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2781898379
Short name T166
Test name
Test status
Simulation time 2245554882 ps
CPU time 26.45 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:34 PM PDT 24
Peak memory 199940 kb
Host smart-d9c6dba2-df5c-427e-aee9-f5223b27d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781898379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2781898379
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3840056966
Short name T138
Test name
Test status
Simulation time 27054246099 ps
CPU time 1653.64 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:42:39 PM PDT 24
Peak memory 766480 kb
Host smart-73004381-0be1-4195-b3b2-46094166fd80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840056966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3840056966
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3715584582
Short name T315
Test name
Test status
Simulation time 1267227477 ps
CPU time 71.57 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:22 PM PDT 24
Peak memory 199792 kb
Host smart-a18a4c2d-175a-4ded-9de6-09244a7e64d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715584582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3715584582
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2479047076
Short name T210
Test name
Test status
Simulation time 4355643755 ps
CPU time 72.96 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:16:25 PM PDT 24
Peak memory 199892 kb
Host smart-81349bb1-f8e9-4372-8f9b-2fcda9dd1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479047076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2479047076
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3628119892
Short name T179
Test name
Test status
Simulation time 461108323 ps
CPU time 6.23 seconds
Started Aug 06 07:15:05 PM PDT 24
Finished Aug 06 07:15:12 PM PDT 24
Peak memory 199816 kb
Host smart-d31901e6-e407-49c7-af3a-5ba72dbe6771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628119892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3628119892
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.695250570
Short name T75
Test name
Test status
Simulation time 122513722586 ps
CPU time 857.61 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:29:25 PM PDT 24
Peak memory 684664 kb
Host smart-8d6fdecf-d4af-4a38-861b-a2ae47225d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695250570 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.695250570
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4123711513
Short name T84
Test name
Test status
Simulation time 34955801341 ps
CPU time 111.86 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 199900 kb
Host smart-78f09167-738e-41eb-a6fc-6569fff974e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123711513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4123711513
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4065762874
Short name T356
Test name
Test status
Simulation time 19971461 ps
CPU time 0.56 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:15:10 PM PDT 24
Peak memory 195596 kb
Host smart-7561e8ab-ef61-4f14-b288-3757d51e51da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065762874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4065762874
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2175075825
Short name T495
Test name
Test status
Simulation time 15787716664 ps
CPU time 72.1 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:16:22 PM PDT 24
Peak memory 199604 kb
Host smart-14d330c0-1e7e-45b2-9d4f-35227010b9ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175075825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2175075825
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1385435168
Short name T300
Test name
Test status
Simulation time 751461445 ps
CPU time 32.34 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:15:42 PM PDT 24
Peak memory 199824 kb
Host smart-69737565-b449-4874-a50d-68deeee09856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385435168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1385435168
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1211432148
Short name T490
Test name
Test status
Simulation time 621346424 ps
CPU time 56.83 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:16:05 PM PDT 24
Peak memory 313132 kb
Host smart-155a26c7-9619-4dc9-868b-faaac91ff0e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211432148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1211432148
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1403101183
Short name T152
Test name
Test status
Simulation time 2059363558 ps
CPU time 81.27 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:16:28 PM PDT 24
Peak memory 199812 kb
Host smart-3492c73a-dc8c-4274-bffa-46b3200a28ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403101183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1403101183
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3015409959
Short name T230
Test name
Test status
Simulation time 7317871133 ps
CPU time 83.98 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:16:30 PM PDT 24
Peak memory 199964 kb
Host smart-ac617044-d638-424b-a7f6-9d5087360538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015409959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3015409959
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2098991377
Short name T448
Test name
Test status
Simulation time 235124687 ps
CPU time 2.94 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:11 PM PDT 24
Peak memory 199768 kb
Host smart-b3aa9dde-1f12-4b39-9254-53c254a3e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098991377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2098991377
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4174706137
Short name T358
Test name
Test status
Simulation time 80604422158 ps
CPU time 368.71 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:21:15 PM PDT 24
Peak memory 208016 kb
Host smart-f482b1a3-66c8-4482-a647-730c9b8f3969
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174706137 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4174706137
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2933188353
Short name T324
Test name
Test status
Simulation time 1818700242 ps
CPU time 82.58 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:16:32 PM PDT 24
Peak memory 199804 kb
Host smart-11c112c9-ec47-4b3b-a351-f4d36c64c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933188353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2933188353
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.946185375
Short name T163
Test name
Test status
Simulation time 14003372 ps
CPU time 0.57 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:15:11 PM PDT 24
Peak memory 195632 kb
Host smart-ceb3561e-a2b1-4019-948e-65801b504cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946185375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.946185375
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.272547428
Short name T237
Test name
Test status
Simulation time 885984706 ps
CPU time 43.02 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:15:55 PM PDT 24
Peak memory 199820 kb
Host smart-0029459b-6c12-4322-b955-af14af32e734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=272547428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.272547428
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2831107238
Short name T381
Test name
Test status
Simulation time 3956326625 ps
CPU time 727.04 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:27:16 PM PDT 24
Peak memory 741368 kb
Host smart-6a83a9c9-ab94-4495-8b6a-12499177b35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831107238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2831107238
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2743807006
Short name T410
Test name
Test status
Simulation time 8366860670 ps
CPU time 59.36 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:16:09 PM PDT 24
Peak memory 199564 kb
Host smart-6d2633fd-2891-4393-9a48-62737e7e7236
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743807006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2743807006
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2049412957
Short name T178
Test name
Test status
Simulation time 2381066691 ps
CPU time 132.72 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:17:21 PM PDT 24
Peak memory 199720 kb
Host smart-4d460e2f-15a8-4da9-b561-afd99ee7f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049412957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2049412957
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2967474699
Short name T205
Test name
Test status
Simulation time 104934931 ps
CPU time 2.66 seconds
Started Aug 06 07:15:05 PM PDT 24
Finished Aug 06 07:15:08 PM PDT 24
Peak memory 199768 kb
Host smart-a636f34c-666a-46fe-93d8-7462ced89883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967474699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2967474699
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.950600217
Short name T383
Test name
Test status
Simulation time 373206230996 ps
CPU time 1966.32 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:47:55 PM PDT 24
Peak memory 720940 kb
Host smart-43888602-1d0f-4d1e-ab09-c8f11d0e6fa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950600217 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.950600217
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4032317098
Short name T147
Test name
Test status
Simulation time 147293227 ps
CPU time 3.34 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:15:12 PM PDT 24
Peak memory 199720 kb
Host smart-ee487226-7a43-4425-85cb-8407fdbc9ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032317098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4032317098
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.916591437
Short name T171
Test name
Test status
Simulation time 20144290 ps
CPU time 0.63 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:15:13 PM PDT 24
Peak memory 196504 kb
Host smart-af3ff4bc-1c2a-4179-94f1-c637b9cd6e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916591437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.916591437
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2931290552
Short name T6
Test name
Test status
Simulation time 2788267566 ps
CPU time 41.24 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:15:51 PM PDT 24
Peak memory 199824 kb
Host smart-b69d29f1-4b57-442b-9c00-6e33bbed84bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931290552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2931290552
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3673220791
Short name T466
Test name
Test status
Simulation time 1140270697 ps
CPU time 8.95 seconds
Started Aug 06 07:15:08 PM PDT 24
Finished Aug 06 07:15:17 PM PDT 24
Peak memory 199596 kb
Host smart-4e81f56a-50c4-45fe-bb7e-a5f9ed0cd451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673220791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3673220791
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1830188270
Short name T306
Test name
Test status
Simulation time 7909762617 ps
CPU time 882.09 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:29:54 PM PDT 24
Peak memory 741332 kb
Host smart-85209b12-2729-4102-99ba-f7aad5487d19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830188270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1830188270
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3973267040
Short name T280
Test name
Test status
Simulation time 8869555100 ps
CPU time 38.3 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 199808 kb
Host smart-919e234f-b927-44f5-9910-063d50d46ffc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973267040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3973267040
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1264636348
Short name T38
Test name
Test status
Simulation time 5396716115 ps
CPU time 88.4 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:38 PM PDT 24
Peak memory 199868 kb
Host smart-f1fb483d-03c3-4e9a-affa-29154be3e866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264636348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1264636348
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.147001120
Short name T350
Test name
Test status
Simulation time 469715391 ps
CPU time 3.27 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:15:15 PM PDT 24
Peak memory 199760 kb
Host smart-bbc2d429-f44f-471f-9127-ba2ec17d9d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147001120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.147001120
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3700360785
Short name T479
Test name
Test status
Simulation time 40833373269 ps
CPU time 581.74 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:24:54 PM PDT 24
Peak memory 216240 kb
Host smart-d29c6d95-e932-409a-a64d-c3ed72cdf907
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700360785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3700360785
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4292713687
Short name T460
Test name
Test status
Simulation time 96535516663 ps
CPU time 106.31 seconds
Started Aug 06 07:15:06 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 199940 kb
Host smart-71245625-57c2-467b-838a-3455cb2e6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292713687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4292713687
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4106711668
Short name T310
Test name
Test status
Simulation time 34635391 ps
CPU time 0.59 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:15:27 PM PDT 24
Peak memory 195528 kb
Host smart-dde80734-e790-4408-80cf-1d704d8042dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106711668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4106711668
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2065540098
Short name T41
Test name
Test status
Simulation time 5588402794 ps
CPU time 77.44 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:16:27 PM PDT 24
Peak memory 199912 kb
Host smart-54d700c8-871d-4dc1-b82f-3a6bea711866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065540098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2065540098
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3057523990
Short name T57
Test name
Test status
Simulation time 2015260870 ps
CPU time 9.84 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:15:20 PM PDT 24
Peak memory 199836 kb
Host smart-b779f6f5-232d-4ef5-86ee-0a0b26377562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057523990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3057523990
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3877162694
Short name T462
Test name
Test status
Simulation time 3456508603 ps
CPU time 585.22 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:24:57 PM PDT 24
Peak memory 658368 kb
Host smart-06e32d08-d0a4-4f46-939c-58ba0da2263a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3877162694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3877162694
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1603806916
Short name T353
Test name
Test status
Simulation time 814169431 ps
CPU time 14.24 seconds
Started Aug 06 07:15:11 PM PDT 24
Finished Aug 06 07:15:25 PM PDT 24
Peak memory 199672 kb
Host smart-b1c6b5eb-7b1c-4181-a232-ad5dcb26bbbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603806916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1603806916
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4193039352
Short name T148
Test name
Test status
Simulation time 6145492288 ps
CPU time 102.48 seconds
Started Aug 06 07:15:09 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 199880 kb
Host smart-fac50bac-924e-425a-bd42-e45ba1396c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193039352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4193039352
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.823275087
Short name T336
Test name
Test status
Simulation time 6810383702 ps
CPU time 12.02 seconds
Started Aug 06 07:15:12 PM PDT 24
Finished Aug 06 07:15:24 PM PDT 24
Peak memory 199968 kb
Host smart-e0d032a1-fb7c-4bac-b947-8b4167009f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823275087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.823275087
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.317625176
Short name T331
Test name
Test status
Simulation time 49438539376 ps
CPU time 1104.83 seconds
Started Aug 06 07:15:10 PM PDT 24
Finished Aug 06 07:33:35 PM PDT 24
Peak memory 696652 kb
Host smart-62312f7c-4738-4a52-bc97-400c72ecd758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317625176 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.317625176
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3650947782
Short name T376
Test name
Test status
Simulation time 32331490478 ps
CPU time 84.99 seconds
Started Aug 06 07:15:07 PM PDT 24
Finished Aug 06 07:16:33 PM PDT 24
Peak memory 199820 kb
Host smart-09545a98-fd19-4602-a322-93887a6419b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650947782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3650947782
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3745663138
Short name T329
Test name
Test status
Simulation time 20263702 ps
CPU time 0.59 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:14:22 PM PDT 24
Peak memory 195928 kb
Host smart-507bee3c-dbcc-4bf2-b9a1-5cf055e1ac65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745663138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3745663138
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3915764516
Short name T220
Test name
Test status
Simulation time 1438149025 ps
CPU time 38.9 seconds
Started Aug 06 07:14:18 PM PDT 24
Finished Aug 06 07:14:57 PM PDT 24
Peak memory 199860 kb
Host smart-612243c2-e5fc-43eb-b4ef-b4010ffea023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915764516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3915764516
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.4086580307
Short name T227
Test name
Test status
Simulation time 922364017 ps
CPU time 50.22 seconds
Started Aug 06 07:14:20 PM PDT 24
Finished Aug 06 07:15:11 PM PDT 24
Peak memory 199796 kb
Host smart-818956e3-c650-49e4-8637-b6977bc1b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086580307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.4086580307
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.524290147
Short name T207
Test name
Test status
Simulation time 900274176 ps
CPU time 23.33 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:14:47 PM PDT 24
Peak memory 242968 kb
Host smart-e6c0feb9-187a-4684-a55f-be11b94ec6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524290147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.524290147
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2310223792
Short name T400
Test name
Test status
Simulation time 10170265655 ps
CPU time 175.87 seconds
Started Aug 06 07:14:22 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 199872 kb
Host smart-413ee09d-b7c9-43ea-96fe-2dd9b05ac8ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310223792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2310223792
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2802856331
Short name T203
Test name
Test status
Simulation time 15030020392 ps
CPU time 40.12 seconds
Started Aug 06 07:14:20 PM PDT 24
Finished Aug 06 07:15:01 PM PDT 24
Peak memory 199932 kb
Host smart-8b2bf387-cd66-418f-a78c-7b543a92f1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802856331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2802856331
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3953666847
Short name T50
Test name
Test status
Simulation time 118988705 ps
CPU time 0.79 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:14:24 PM PDT 24
Peak memory 218400 kb
Host smart-d2ebd073-d950-477e-8726-9edfbf52d994
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953666847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3953666847
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1158745799
Short name T198
Test name
Test status
Simulation time 574696923 ps
CPU time 4.99 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:14:28 PM PDT 24
Peak memory 199860 kb
Host smart-9727f472-e6a1-4d9e-8297-b8f29409acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158745799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1158745799
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3480089713
Short name T128
Test name
Test status
Simulation time 7518585373 ps
CPU time 721.78 seconds
Started Aug 06 07:14:22 PM PDT 24
Finished Aug 06 07:26:24 PM PDT 24
Peak memory 470712 kb
Host smart-29466e9f-32de-4eab-9414-75779f908ab8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480089713 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3480089713
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.799957603
Short name T367
Test name
Test status
Simulation time 4641516497 ps
CPU time 55.11 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:15:17 PM PDT 24
Peak memory 199848 kb
Host smart-b35df433-ceba-45d0-a4e9-580e7d41304a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=799957603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.799957603
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3875732886
Short name T443
Test name
Test status
Simulation time 9639664230 ps
CPU time 104.57 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:16:08 PM PDT 24
Peak memory 199908 kb
Host smart-1d58ff9d-a03a-4ddb-bbc4-da641f103161
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3875732886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3875732886
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.719018080
Short name T519
Test name
Test status
Simulation time 8736470393 ps
CPU time 128.48 seconds
Started Aug 06 07:14:20 PM PDT 24
Finished Aug 06 07:16:29 PM PDT 24
Peak memory 199872 kb
Host smart-39b83cee-daa8-45b6-939e-96553b56cb98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=719018080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.719018080
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.828218921
Short name T201
Test name
Test status
Simulation time 66994853093 ps
CPU time 619.25 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:24:40 PM PDT 24
Peak memory 199864 kb
Host smart-dd46d1c0-f6e7-4735-82f4-8b5dd43bac6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=828218921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.828218921
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.66783712
Short name T212
Test name
Test status
Simulation time 387069253585 ps
CPU time 2580.06 seconds
Started Aug 06 07:14:19 PM PDT 24
Finished Aug 06 07:57:20 PM PDT 24
Peak memory 215908 kb
Host smart-2c408f6e-6393-41db-9c2f-642dc9a3e43f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=66783712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.66783712
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.937935251
Short name T452
Test name
Test status
Simulation time 152570749151 ps
CPU time 2178.63 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 215808 kb
Host smart-60530f4a-9a33-4c70-9992-fbf6bfdc9036
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=937935251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.937935251
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2948651950
Short name T491
Test name
Test status
Simulation time 6925286108 ps
CPU time 82.19 seconds
Started Aug 06 07:14:23 PM PDT 24
Finished Aug 06 07:15:45 PM PDT 24
Peak memory 199916 kb
Host smart-71c6367d-1906-472d-8b23-52529e8e1428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948651950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2948651950
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.340564344
Short name T305
Test name
Test status
Simulation time 42003704 ps
CPU time 0.6 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:15:25 PM PDT 24
Peak memory 196608 kb
Host smart-c8568a29-0620-467b-8b8d-61b637544e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340564344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.340564344
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.555682835
Short name T253
Test name
Test status
Simulation time 1315599997 ps
CPU time 70.26 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:16:35 PM PDT 24
Peak memory 199664 kb
Host smart-b40265ca-d046-48bc-8564-ca1ea0ca6e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555682835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.555682835
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.810046586
Short name T190
Test name
Test status
Simulation time 4553245166 ps
CPU time 31.41 seconds
Started Aug 06 07:15:30 PM PDT 24
Finished Aug 06 07:16:02 PM PDT 24
Peak memory 200088 kb
Host smart-d977f481-87ec-43de-a4fd-5f4912c64cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810046586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.810046586
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1925862277
Short name T362
Test name
Test status
Simulation time 7076547577 ps
CPU time 266.87 seconds
Started Aug 06 07:15:23 PM PDT 24
Finished Aug 06 07:19:50 PM PDT 24
Peak memory 464396 kb
Host smart-f62c0118-642b-489f-a604-7e859ed3c801
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925862277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1925862277
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.793019616
Short name T289
Test name
Test status
Simulation time 14915224788 ps
CPU time 21.53 seconds
Started Aug 06 07:15:23 PM PDT 24
Finished Aug 06 07:15:45 PM PDT 24
Peak memory 199740 kb
Host smart-60354aec-113f-46be-acb9-a17ea53bae28
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793019616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.793019616
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2585856572
Short name T330
Test name
Test status
Simulation time 9210283774 ps
CPU time 96.75 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 208136 kb
Host smart-6a97c5ac-3d52-4e38-855a-50a2d24db304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585856572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2585856572
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.853661801
Short name T431
Test name
Test status
Simulation time 874214848 ps
CPU time 13.99 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:15:39 PM PDT 24
Peak memory 199836 kb
Host smart-35da6f95-5da5-4103-96e2-9cff320e736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853661801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.853661801
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3895714528
Short name T15
Test name
Test status
Simulation time 18744075415 ps
CPU time 339.76 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:21:08 PM PDT 24
Peak memory 199896 kb
Host smart-96357092-9982-4b2d-bf69-f9db5fef7f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895714528 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3895714528
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.893245617
Short name T199
Test name
Test status
Simulation time 1137643669 ps
CPU time 30.17 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:15:55 PM PDT 24
Peak memory 199772 kb
Host smart-1a349fce-0120-41a4-ab07-e71ac040654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893245617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.893245617
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3752753442
Short name T279
Test name
Test status
Simulation time 12036113 ps
CPU time 0.58 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:29 PM PDT 24
Peak memory 195508 kb
Host smart-18d5b7e6-1b21-48c0-9787-59f0d6b7ef07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752753442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3752753442
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1244389550
Short name T426
Test name
Test status
Simulation time 1312082844 ps
CPU time 38.08 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:16:09 PM PDT 24
Peak memory 199820 kb
Host smart-f65c0467-d4e6-4bc8-b69b-37e1f3338239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244389550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1244389550
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4046630426
Short name T521
Test name
Test status
Simulation time 8013313931 ps
CPU time 47.35 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:16:17 PM PDT 24
Peak memory 200108 kb
Host smart-f5214d03-fa48-4343-bb5b-0607ffeefcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046630426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4046630426
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2773215295
Short name T308
Test name
Test status
Simulation time 68344348922 ps
CPU time 1188.67 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:35:20 PM PDT 24
Peak memory 712812 kb
Host smart-8a07a295-4eb2-46d7-b917-3fc268b5231b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773215295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2773215295
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1853911463
Short name T135
Test name
Test status
Simulation time 2708273231 ps
CPU time 38.28 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:16:07 PM PDT 24
Peak memory 199856 kb
Host smart-508b3202-7ee0-44cf-b702-0f3c3ff2ccca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853911463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1853911463
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.100993868
Short name T337
Test name
Test status
Simulation time 5862893691 ps
CPU time 54.15 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:16:22 PM PDT 24
Peak memory 199868 kb
Host smart-a6f5f303-11be-4a02-951b-d94d0934cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100993868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.100993868
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4034730484
Short name T412
Test name
Test status
Simulation time 2014348981 ps
CPU time 14.46 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:43 PM PDT 24
Peak memory 199808 kb
Host smart-4d884333-5124-4be3-850c-85c238a152dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034730484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4034730484
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2573502141
Short name T129
Test name
Test status
Simulation time 41941490145 ps
CPU time 2077.52 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:50:06 PM PDT 24
Peak memory 779204 kb
Host smart-ddc70637-8185-40eb-ad0c-d47b15b3da3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573502141 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2573502141
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4185210865
Short name T525
Test name
Test status
Simulation time 8333860819 ps
CPU time 53.38 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:16:25 PM PDT 24
Peak memory 199972 kb
Host smart-11cdbc39-bbbe-486b-89ed-cfaf40613df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185210865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4185210865
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.4154604905
Short name T27
Test name
Test status
Simulation time 36370865 ps
CPU time 0.58 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:15:28 PM PDT 24
Peak memory 196580 kb
Host smart-67c34a0e-716b-4f7d-9c82-9e07d27cdc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154604905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.4154604905
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.226495612
Short name T164
Test name
Test status
Simulation time 393302307 ps
CPU time 21.68 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:15:53 PM PDT 24
Peak memory 199704 kb
Host smart-043388d6-33d6-4f1c-95cf-6f11c0989899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226495612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.226495612
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1635536349
Short name T127
Test name
Test status
Simulation time 2290393381 ps
CPU time 59.44 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:16:26 PM PDT 24
Peak memory 199868 kb
Host smart-c5be90e5-61b4-4b98-9792-5ec5cf978d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635536349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1635536349
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1707261262
Short name T3
Test name
Test status
Simulation time 3422268500 ps
CPU time 525.97 seconds
Started Aug 06 07:15:33 PM PDT 24
Finished Aug 06 07:24:19 PM PDT 24
Peak memory 492716 kb
Host smart-c693c744-cb90-4873-9d0c-fe35d9f53ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707261262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1707261262
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3760948068
Short name T513
Test name
Test status
Simulation time 3568166578 ps
CPU time 196.11 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:18:42 PM PDT 24
Peak memory 199880 kb
Host smart-9a10380a-9ba4-4a16-8e6c-dc810745f23e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760948068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3760948068
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1087748397
Short name T372
Test name
Test status
Simulation time 5701961247 ps
CPU time 103.99 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:17:12 PM PDT 24
Peak memory 199940 kb
Host smart-b6ed203b-7f95-4795-9e8e-d2b51ab923cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087748397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1087748397
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2263907470
Short name T369
Test name
Test status
Simulation time 1206760013 ps
CPU time 15.04 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:44 PM PDT 24
Peak memory 199852 kb
Host smart-c71a27b4-1e45-4ef1-b62f-487219e5ec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263907470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2263907470
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.581017968
Short name T440
Test name
Test status
Simulation time 75254705761 ps
CPU time 223.8 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:19:11 PM PDT 24
Peak memory 274476 kb
Host smart-64cc1d1a-fde1-4383-8abd-7378a76a604e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581017968 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.581017968
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1162733895
Short name T341
Test name
Test status
Simulation time 9285059148 ps
CPU time 69.85 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:16:39 PM PDT 24
Peak memory 199900 kb
Host smart-5d5efe9e-81cc-44a4-b041-f651bc327bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162733895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1162733895
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3373205688
Short name T418
Test name
Test status
Simulation time 41674365 ps
CPU time 0.59 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:15:32 PM PDT 24
Peak memory 195936 kb
Host smart-d3d19011-97d0-4fa9-a0bc-749febed3e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373205688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3373205688
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1724698652
Short name T35
Test name
Test status
Simulation time 25373147146 ps
CPU time 75 seconds
Started Aug 06 07:15:24 PM PDT 24
Finished Aug 06 07:16:40 PM PDT 24
Peak memory 216292 kb
Host smart-9de1e20c-22b6-40ff-af0a-f1eaf4e0094a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724698652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1724698652
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3920027964
Short name T124
Test name
Test status
Simulation time 1078443973 ps
CPU time 54.69 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:16:21 PM PDT 24
Peak memory 199880 kb
Host smart-270165e0-b6b8-4fd9-8a29-fc9262c30320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920027964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3920027964
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1808286542
Short name T136
Test name
Test status
Simulation time 6182818218 ps
CPU time 586.63 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:25:14 PM PDT 24
Peak memory 729252 kb
Host smart-a7cf2a2d-8a88-4eed-a9b5-63366d19b9f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808286542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1808286542
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2037192016
Short name T321
Test name
Test status
Simulation time 36212409549 ps
CPU time 108.48 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:17:17 PM PDT 24
Peak memory 199876 kb
Host smart-f976f39f-7a66-48dc-931a-8bf2f62eb322
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037192016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2037192016
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2608521213
Short name T157
Test name
Test status
Simulation time 11452353469 ps
CPU time 197.5 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:18:43 PM PDT 24
Peak memory 199840 kb
Host smart-780e34dd-c492-4d29-bd37-b2b070e371ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608521213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2608521213
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2887295367
Short name T274
Test name
Test status
Simulation time 5114863139 ps
CPU time 9.15 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:37 PM PDT 24
Peak memory 199952 kb
Host smart-a1bd7c23-97fd-463a-ae10-86a32bb64832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887295367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2887295367
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3736403611
Short name T59
Test name
Test status
Simulation time 64404881994 ps
CPU time 2577.8 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:58:27 PM PDT 24
Peak memory 768684 kb
Host smart-62c177ae-50db-4059-872d-2e48b29e65a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736403611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3736403611
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2393673091
Short name T86
Test name
Test status
Simulation time 16659139586 ps
CPU time 149.42 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:18:01 PM PDT 24
Peak memory 200088 kb
Host smart-b82ede12-829a-4d63-8536-607d2b79b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393673091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2393673091
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.487723836
Short name T56
Test name
Test status
Simulation time 54689624 ps
CPU time 0.58 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:15:32 PM PDT 24
Peak memory 196596 kb
Host smart-5d7e30e1-a895-4ad6-9da7-a10bb04d21ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487723836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.487723836
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2491073378
Short name T149
Test name
Test status
Simulation time 5683387683 ps
CPU time 85.26 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 199760 kb
Host smart-96124392-9a9f-42ce-9de9-0f48fceeb176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491073378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2491073378
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1095683829
Short name T313
Test name
Test status
Simulation time 8099837768 ps
CPU time 31.22 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:15:58 PM PDT 24
Peak memory 199880 kb
Host smart-26145416-c387-41b3-996a-daa19e13512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095683829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1095683829
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2760333092
Short name T351
Test name
Test status
Simulation time 5467164053 ps
CPU time 1019.78 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:32:25 PM PDT 24
Peak memory 768696 kb
Host smart-66d9b4b0-0ff6-48eb-9789-713e9de42bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760333092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2760333092
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3717512136
Short name T182
Test name
Test status
Simulation time 9977457628 ps
CPU time 173.78 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:18:19 PM PDT 24
Peak memory 199996 kb
Host smart-eb7dd555-3b3e-4d6a-ad3a-c3572e1cc752
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717512136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3717512136
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2786062653
Short name T216
Test name
Test status
Simulation time 45204551147 ps
CPU time 154.69 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:18:06 PM PDT 24
Peak memory 216136 kb
Host smart-47495bde-204c-44ae-bf2a-d73afc27472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786062653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2786062653
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.900494681
Short name T425
Test name
Test status
Simulation time 888191563 ps
CPU time 15.77 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:15:45 PM PDT 24
Peak memory 199848 kb
Host smart-33e93fe1-af35-48a6-babb-fdf8bcf73b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900494681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.900494681
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1015144818
Short name T77
Test name
Test status
Simulation time 26557448891 ps
CPU time 276.46 seconds
Started Aug 06 07:15:31 PM PDT 24
Finished Aug 06 07:20:07 PM PDT 24
Peak memory 207988 kb
Host smart-f11c0e2b-96a1-4e50-ad72-91469cd21179
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015144818 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1015144818
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3992897226
Short name T497
Test name
Test status
Simulation time 7849155133 ps
CPU time 104.19 seconds
Started Aug 06 07:15:30 PM PDT 24
Finished Aug 06 07:17:14 PM PDT 24
Peak memory 199804 kb
Host smart-e1c63a4e-afad-4a24-b1f2-495575a79bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992897226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3992897226
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.466762369
Short name T286
Test name
Test status
Simulation time 29026444 ps
CPU time 0.55 seconds
Started Aug 06 07:15:34 PM PDT 24
Finished Aug 06 07:15:35 PM PDT 24
Peak memory 194708 kb
Host smart-8641eb4d-a340-4fd7-98de-e70e0e3fecce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466762369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.466762369
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1767351544
Short name T388
Test name
Test status
Simulation time 1020541569 ps
CPU time 42.95 seconds
Started Aug 06 07:15:30 PM PDT 24
Finished Aug 06 07:16:13 PM PDT 24
Peak memory 199856 kb
Host smart-9e015c43-bac9-4fba-9c32-4238cbc6afeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767351544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1767351544
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3833196143
Short name T258
Test name
Test status
Simulation time 3558937716 ps
CPU time 17.1 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:15:49 PM PDT 24
Peak memory 199888 kb
Host smart-b99f0175-762a-4b1e-94f2-614ee20a53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833196143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3833196143
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1390966913
Short name T355
Test name
Test status
Simulation time 42530775968 ps
CPU time 1490.72 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:40:23 PM PDT 24
Peak memory 736100 kb
Host smart-aff861a8-1ac9-4ebf-a3ea-8393207f098a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390966913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1390966913
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3294670165
Short name T493
Test name
Test status
Simulation time 3188034494 ps
CPU time 87.85 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 199468 kb
Host smart-d075d43a-162b-4969-8bb4-fca161fd79c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294670165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3294670165
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.236889113
Short name T196
Test name
Test status
Simulation time 2973084774 ps
CPU time 170.7 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:18:22 PM PDT 24
Peak memory 199956 kb
Host smart-e8ed4766-ec09-48dd-98e2-9f8e337ca7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236889113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.236889113
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2412649573
Short name T191
Test name
Test status
Simulation time 240385140 ps
CPU time 4.02 seconds
Started Aug 06 07:15:30 PM PDT 24
Finished Aug 06 07:15:35 PM PDT 24
Peak memory 199688 kb
Host smart-19d491c7-f550-4d6c-83b1-24c4b4f29ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412649573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2412649573
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.248762718
Short name T345
Test name
Test status
Simulation time 28343837554 ps
CPU time 121.13 seconds
Started Aug 06 07:15:33 PM PDT 24
Finished Aug 06 07:17:34 PM PDT 24
Peak memory 199880 kb
Host smart-907c6647-9672-40fb-8d27-49d040238d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248762718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.248762718
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1545557853
Short name T470
Test name
Test status
Simulation time 50301953 ps
CPU time 0.58 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:15:36 PM PDT 24
Peak memory 195596 kb
Host smart-77274efe-2fe7-4640-b4dd-7276b1acb569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545557853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1545557853
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.165824156
Short name T342
Test name
Test status
Simulation time 996471360 ps
CPU time 33.63 seconds
Started Aug 06 07:15:32 PM PDT 24
Finished Aug 06 07:16:05 PM PDT 24
Peak memory 199448 kb
Host smart-d0acb6c1-bea8-4c2b-b23e-9b3c4f7c363e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=165824156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.165824156
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2270535650
Short name T373
Test name
Test status
Simulation time 6275465170 ps
CPU time 27.88 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:16:03 PM PDT 24
Peak memory 199984 kb
Host smart-7cfb69d1-51a9-4459-96c6-29deec5458c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270535650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2270535650
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_error.2567616323
Short name T332
Test name
Test status
Simulation time 9605278352 ps
CPU time 28.71 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:16:04 PM PDT 24
Peak memory 199824 kb
Host smart-361a74cf-6d3d-448b-b6ed-07813c61676e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567616323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2567616323
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2335232374
Short name T226
Test name
Test status
Simulation time 2662706517 ps
CPU time 142.25 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:17:57 PM PDT 24
Peak memory 199836 kb
Host smart-27fd0513-9d10-400a-b52a-54f8aad612b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335232374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2335232374
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3603694049
Short name T53
Test name
Test status
Simulation time 330120246 ps
CPU time 13.99 seconds
Started Aug 06 07:15:37 PM PDT 24
Finished Aug 06 07:15:51 PM PDT 24
Peak memory 199860 kb
Host smart-45cac35d-dd03-4fb2-872c-f86dfaa8325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603694049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3603694049
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2316318929
Short name T72
Test name
Test status
Simulation time 492175775108 ps
CPU time 678.26 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:26:46 PM PDT 24
Peak memory 199848 kb
Host smart-3f46644f-6453-460c-b5bd-fa6b3cd94cb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316318929 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2316318929
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2621871073
Short name T488
Test name
Test status
Simulation time 4286177991 ps
CPU time 75.74 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:16:51 PM PDT 24
Peak memory 199936 kb
Host smart-119534f8-1654-463d-911c-30aa63250954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621871073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2621871073
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.454151494
Short name T396
Test name
Test status
Simulation time 40858778 ps
CPU time 0.6 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:15:26 PM PDT 24
Peak memory 196568 kb
Host smart-04dcbc87-77bd-4ed6-b70b-8141f995ba8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454151494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.454151494
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.257811418
Short name T454
Test name
Test status
Simulation time 1592728045 ps
CPU time 25.89 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:15:53 PM PDT 24
Peak memory 199784 kb
Host smart-c18d6046-2acd-497e-9519-b6722ad07724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257811418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.257811418
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3007106907
Short name T311
Test name
Test status
Simulation time 4250705318 ps
CPU time 80.14 seconds
Started Aug 06 07:15:33 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 199912 kb
Host smart-0a2e0205-d7cc-40e4-ab5d-f97de7b4e39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007106907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3007106907
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2635509845
Short name T438
Test name
Test status
Simulation time 5740110239 ps
CPU time 945.63 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:31:21 PM PDT 24
Peak memory 709464 kb
Host smart-0417701f-ec20-40b1-a56b-41413aba70c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635509845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2635509845
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2452838009
Short name T506
Test name
Test status
Simulation time 77416034568 ps
CPU time 62.76 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:16:30 PM PDT 24
Peak memory 199060 kb
Host smart-cf5ed5a0-5ef5-433f-906d-9d73ec48cf97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452838009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2452838009
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1457847459
Short name T32
Test name
Test status
Simulation time 33230901267 ps
CPU time 101.5 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:17:10 PM PDT 24
Peak memory 199816 kb
Host smart-cd6c6708-98d0-475c-991c-abbbccaa087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457847459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1457847459
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.275987219
Short name T348
Test name
Test status
Simulation time 465646594 ps
CPU time 1.96 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:15:37 PM PDT 24
Peak memory 199736 kb
Host smart-1aa6ba40-5ff5-4e8b-bdfb-6a3450d818c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275987219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.275987219
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.645550118
Short name T73
Test name
Test status
Simulation time 75133244886 ps
CPU time 235.16 seconds
Started Aug 06 07:15:35 PM PDT 24
Finished Aug 06 07:19:30 PM PDT 24
Peak memory 207672 kb
Host smart-dcfa174a-0933-4d2b-acfc-c93edea43fbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645550118 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.645550118
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2986189179
Short name T444
Test name
Test status
Simulation time 32161628383 ps
CPU time 97.81 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 199848 kb
Host smart-74bc8e58-9575-44ee-917c-c46fedb95d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986189179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2986189179
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3612770198
Short name T276
Test name
Test status
Simulation time 42580245 ps
CPU time 0.58 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:29 PM PDT 24
Peak memory 195920 kb
Host smart-64453923-b407-4dbd-acfc-75d1f8ede150
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612770198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3612770198
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1446814777
Short name T292
Test name
Test status
Simulation time 1267260212 ps
CPU time 69.41 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 199844 kb
Host smart-668e22b9-55c7-42c1-b687-28577ffbf2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446814777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1446814777
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1943313225
Short name T36
Test name
Test status
Simulation time 279669432 ps
CPU time 15.26 seconds
Started Aug 06 07:15:25 PM PDT 24
Finished Aug 06 07:15:41 PM PDT 24
Peak memory 199796 kb
Host smart-d4a1529b-e553-48dd-8fa6-f586098dd760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943313225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1943313225
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1620539525
Short name T215
Test name
Test status
Simulation time 2664063087 ps
CPU time 15.72 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:44 PM PDT 24
Peak memory 230708 kb
Host smart-201e224a-9b07-4a74-9f1e-89de28ec0df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620539525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1620539525
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3044603089
Short name T260
Test name
Test status
Simulation time 13405836714 ps
CPU time 108.23 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:17:14 PM PDT 24
Peak memory 199840 kb
Host smart-b34ea235-721a-4bdc-ac2c-96264e64c422
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044603089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3044603089
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3801566408
Short name T159
Test name
Test status
Simulation time 12277742770 ps
CPU time 150.33 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:17:57 PM PDT 24
Peak memory 200000 kb
Host smart-b4f5f1ca-0a97-464c-93c1-b904f29c7650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801566408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3801566408
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1860625052
Short name T242
Test name
Test status
Simulation time 127293633 ps
CPU time 5.68 seconds
Started Aug 06 07:15:28 PM PDT 24
Finished Aug 06 07:15:34 PM PDT 24
Peak memory 199812 kb
Host smart-a5107228-37df-4076-934b-0ef7d065804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860625052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1860625052
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3967764560
Short name T277
Test name
Test status
Simulation time 314009819904 ps
CPU time 2354.17 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:54:41 PM PDT 24
Peak memory 746432 kb
Host smart-90c84257-371f-4fe6-b3b8-1a12da406310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967764560 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3967764560
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2620735243
Short name T514
Test name
Test status
Simulation time 295911198 ps
CPU time 5.65 seconds
Started Aug 06 07:15:27 PM PDT 24
Finished Aug 06 07:15:33 PM PDT 24
Peak memory 199840 kb
Host smart-dbcc088a-3987-417d-b641-4e6d1db29a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620735243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2620735243
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.107692385
Short name T474
Test name
Test status
Simulation time 74132884 ps
CPU time 0.57 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:15:44 PM PDT 24
Peak memory 194704 kb
Host smart-00b07950-8c57-444c-bf10-2dea73ee509b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107692385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.107692385
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.228647177
Short name T402
Test name
Test status
Simulation time 733249250 ps
CPU time 39.8 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:16:23 PM PDT 24
Peak memory 199812 kb
Host smart-d09eed31-7254-42a3-8b84-ac12e4282fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228647177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.228647177
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1402121312
Short name T359
Test name
Test status
Simulation time 4109626965 ps
CPU time 322.4 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:21:06 PM PDT 24
Peak memory 512536 kb
Host smart-a470b210-31be-4f58-8c7c-c3aaec37960f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402121312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1402121312
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2480840685
Short name T283
Test name
Test status
Simulation time 2078001528 ps
CPU time 9.8 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:15:56 PM PDT 24
Peak memory 199736 kb
Host smart-69d237be-df6a-47f5-9c9a-8e0a3d138a22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480840685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2480840685
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.626732686
Short name T162
Test name
Test status
Simulation time 29186728039 ps
CPU time 85.54 seconds
Started Aug 06 07:15:29 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 199960 kb
Host smart-efae2961-05d3-4ab7-9ac6-ee7b8f678360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626732686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.626732686
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3311762852
Short name T370
Test name
Test status
Simulation time 5233274406 ps
CPU time 16.2 seconds
Started Aug 06 07:15:26 PM PDT 24
Finished Aug 06 07:15:42 PM PDT 24
Peak memory 199980 kb
Host smart-19c5e1f6-e2d4-4b82-b7e6-525834ad6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311762852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3311762852
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1436142202
Short name T74
Test name
Test status
Simulation time 26394973332 ps
CPU time 50.79 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:16:34 PM PDT 24
Peak memory 208016 kb
Host smart-12395421-ac77-4ebf-9ce2-f2d9d36c6d1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436142202 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1436142202
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1149843797
Short name T301
Test name
Test status
Simulation time 15818966594 ps
CPU time 70.75 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 199904 kb
Host smart-b16405dc-4b0e-4bc2-ba88-435ce52d8a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149843797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1149843797
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3684288806
Short name T195
Test name
Test status
Simulation time 13928641 ps
CPU time 0.57 seconds
Started Aug 06 07:14:32 PM PDT 24
Finished Aug 06 07:14:33 PM PDT 24
Peak memory 194592 kb
Host smart-59e012e0-6ea6-457b-8def-b7be152d710b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684288806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3684288806
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1806328120
Short name T496
Test name
Test status
Simulation time 5255581726 ps
CPU time 81.3 seconds
Started Aug 06 07:14:24 PM PDT 24
Finished Aug 06 07:15:45 PM PDT 24
Peak memory 215908 kb
Host smart-02782efc-afd5-453d-9314-8d0e214bd6d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806328120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1806328120
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1167155340
Short name T131
Test name
Test status
Simulation time 21928542851 ps
CPU time 69.75 seconds
Started Aug 06 07:14:22 PM PDT 24
Finished Aug 06 07:15:31 PM PDT 24
Peak memory 199864 kb
Host smart-bd0698c9-a3e9-4b7a-a00d-0b7daf9939b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167155340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1167155340
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3866647497
Short name T468
Test name
Test status
Simulation time 5679790731 ps
CPU time 561.95 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:23:43 PM PDT 24
Peak memory 707808 kb
Host smart-d5c9c6ca-17fc-4572-932e-8052b15200b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866647497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3866647497
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2284131583
Short name T471
Test name
Test status
Simulation time 8804526983 ps
CPU time 157.43 seconds
Started Aug 06 07:14:33 PM PDT 24
Finished Aug 06 07:17:10 PM PDT 24
Peak memory 199820 kb
Host smart-4ffd8017-a235-4608-9330-b766954025b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284131583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2284131583
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3966308739
Short name T335
Test name
Test status
Simulation time 4554055538 ps
CPU time 124.33 seconds
Started Aug 06 07:14:27 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 200088 kb
Host smart-d5130224-fa2e-4a9b-b23b-c4b0a408c5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966308739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3966308739
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.180286755
Short name T47
Test name
Test status
Simulation time 112607022 ps
CPU time 0.86 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:14:32 PM PDT 24
Peak memory 218540 kb
Host smart-4c450d5d-5a04-4c4a-9a9b-6a704f2f38eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180286755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.180286755
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1870818278
Short name T174
Test name
Test status
Simulation time 5786385129 ps
CPU time 13.28 seconds
Started Aug 06 07:14:21 PM PDT 24
Finished Aug 06 07:14:34 PM PDT 24
Peak memory 199940 kb
Host smart-b8a4a924-9e7e-41e5-9f8d-a5a6bff90aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870818278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1870818278
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3944188538
Short name T272
Test name
Test status
Simulation time 102904531494 ps
CPU time 956.56 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:30:28 PM PDT 24
Peak memory 709880 kb
Host smart-ae1d1fc5-5887-4e43-8779-3d0af0949e2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944188538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3944188538
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1522648891
Short name T19
Test name
Test status
Simulation time 230355896450 ps
CPU time 5332.44 seconds
Started Aug 06 07:14:32 PM PDT 24
Finished Aug 06 08:43:25 PM PDT 24
Peak memory 843432 kb
Host smart-d5163423-1f28-41bd-8440-debd606f83bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522648891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1522648891
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1961298314
Short name T375
Test name
Test status
Simulation time 15556339862 ps
CPU time 51.86 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:15:23 PM PDT 24
Peak memory 199868 kb
Host smart-62df9da4-b511-447d-a2e0-16d6fd15a45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1961298314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1961298314
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2617449003
Short name T340
Test name
Test status
Simulation time 4549439537 ps
CPU time 84.43 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:15:58 PM PDT 24
Peak memory 199728 kb
Host smart-912dbc27-2bc2-411b-985e-0110dc18b7a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2617449003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2617449003
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.576477212
Short name T156
Test name
Test status
Simulation time 2303490359 ps
CPU time 76.22 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 199852 kb
Host smart-ac23e157-2a4f-4300-ad3f-24de52666793
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=576477212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.576477212
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.226304371
Short name T140
Test name
Test status
Simulation time 37004462582 ps
CPU time 647.59 seconds
Started Aug 06 07:14:32 PM PDT 24
Finished Aug 06 07:25:20 PM PDT 24
Peak memory 199860 kb
Host smart-63a21a46-141f-4bf9-9727-22b11b212154
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=226304371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.226304371
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3314547692
Short name T401
Test name
Test status
Simulation time 750474569094 ps
CPU time 2051.31 seconds
Started Aug 06 07:14:37 PM PDT 24
Finished Aug 06 07:48:49 PM PDT 24
Peak memory 215496 kb
Host smart-ece21075-953c-414a-85be-1343818c5291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3314547692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3314547692
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2558609021
Short name T464
Test name
Test status
Simulation time 188204475817 ps
CPU time 2430.68 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:55:05 PM PDT 24
Peak memory 215324 kb
Host smart-3e1821a2-5516-47f2-878e-95feb8832ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2558609021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2558609021
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2706005531
Short name T204
Test name
Test status
Simulation time 11535968379 ps
CPU time 37.77 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:15:12 PM PDT 24
Peak memory 199876 kb
Host smart-bc5f50dc-7c66-4c3b-8b2a-3da3aa436e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706005531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2706005531
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.313820360
Short name T520
Test name
Test status
Simulation time 45876202 ps
CPU time 0.56 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:15:44 PM PDT 24
Peak memory 194844 kb
Host smart-9157a905-bd2d-41d8-be30-8e699bfa0855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313820360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.313820360
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.107016876
Short name T386
Test name
Test status
Simulation time 3441262199 ps
CPU time 43.6 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:16:27 PM PDT 24
Peak memory 199836 kb
Host smart-24b20b01-d11c-43e8-a876-1a316afc2ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107016876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.107016876
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.807458147
Short name T338
Test name
Test status
Simulation time 5635733730 ps
CPU time 37 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:16:22 PM PDT 24
Peak memory 199868 kb
Host smart-2956d569-8546-41be-9040-b367fdcd07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807458147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.807458147
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1810147814
Short name T477
Test name
Test status
Simulation time 9419826392 ps
CPU time 876.7 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 684688 kb
Host smart-35cb3ed3-fc2e-4e29-8d9f-953a75a8a753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810147814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1810147814
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1954806121
Short name T524
Test name
Test status
Simulation time 1711491984 ps
CPU time 21.93 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:16:06 PM PDT 24
Peak memory 199724 kb
Host smart-b3e0365b-5916-40b8-94c8-0edd313d7989
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954806121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1954806121
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1657816057
Short name T141
Test name
Test status
Simulation time 9717027723 ps
CPU time 112.09 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:17:35 PM PDT 24
Peak memory 199828 kb
Host smart-04a240d4-36d2-4e85-9b22-ff05b861a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657816057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1657816057
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1576141218
Short name T200
Test name
Test status
Simulation time 82102511 ps
CPU time 2.1 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 199836 kb
Host smart-69757b3b-2cb4-4f59-b38a-768f9ef7a6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576141218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1576141218
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1030218110
Short name T361
Test name
Test status
Simulation time 74645144327 ps
CPU time 1858.15 seconds
Started Aug 06 07:15:42 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 654228 kb
Host smart-e54e7758-d233-4ec6-a884-29b6ffe76bfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030218110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1030218110
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.4048447745
Short name T88
Test name
Test status
Simulation time 11079415705 ps
CPU time 71.25 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 199912 kb
Host smart-9a718000-fe56-4c58-b7fd-a8b5cb00aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048447745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.4048447745
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1755493886
Short name T379
Test name
Test status
Simulation time 36155239 ps
CPU time 0.59 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 194868 kb
Host smart-b4aebdaa-393b-49f5-a8c9-adbaa0aecfce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755493886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1755493886
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1930859167
Short name T28
Test name
Test status
Simulation time 5580518751 ps
CPU time 79.08 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:17:04 PM PDT 24
Peak memory 199932 kb
Host smart-2a41e783-9b22-40e0-b7c1-b971568ace26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930859167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1930859167
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2507523993
Short name T398
Test name
Test status
Simulation time 4673127030 ps
CPU time 47.79 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:16:32 PM PDT 24
Peak memory 199792 kb
Host smart-548ebfbe-854a-45da-9f54-e0f7f96d34a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507523993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2507523993
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2389703041
Short name T354
Test name
Test status
Simulation time 5680816546 ps
CPU time 1320.76 seconds
Started Aug 06 07:15:48 PM PDT 24
Finished Aug 06 07:37:49 PM PDT 24
Peak memory 748800 kb
Host smart-0d5a8271-d3df-47ce-b3a7-76a1cdebc4d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389703041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2389703041
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.633948808
Short name T284
Test name
Test status
Simulation time 8939102990 ps
CPU time 152.3 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:18:17 PM PDT 24
Peak memory 199896 kb
Host smart-ebc3f745-0eb9-4305-9dd5-5797ede5505f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633948808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.633948808
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2400027644
Short name T486
Test name
Test status
Simulation time 7878228162 ps
CPU time 148.83 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:18:15 PM PDT 24
Peak memory 199884 kb
Host smart-42264a40-3c5a-4ccf-82c8-c71588a8a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400027644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2400027644
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.787392702
Short name T238
Test name
Test status
Simulation time 356644003 ps
CPU time 7.64 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:15:52 PM PDT 24
Peak memory 199840 kb
Host smart-2b00cdf9-af43-4e6b-b5fa-d5ff484c60c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787392702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.787392702
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2561367992
Short name T463
Test name
Test status
Simulation time 6543442659 ps
CPU time 1073.48 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:33:39 PM PDT 24
Peak memory 759992 kb
Host smart-f2646fdd-0cc9-4307-a71b-21d3716ccf22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561367992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2561367992
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1283454161
Short name T249
Test name
Test status
Simulation time 6607383395 ps
CPU time 19.94 seconds
Started Aug 06 07:15:48 PM PDT 24
Finished Aug 06 07:16:08 PM PDT 24
Peak memory 199936 kb
Host smart-de67bd06-dee1-47de-bfc0-9b0916274470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283454161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1283454161
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2222507388
Short name T407
Test name
Test status
Simulation time 197282647 ps
CPU time 0.6 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 195908 kb
Host smart-e89e2116-1c10-42d8-a49c-675a2de7a716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222507388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2222507388
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1049959941
Short name T17
Test name
Test status
Simulation time 3611201098 ps
CPU time 51.08 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:16:38 PM PDT 24
Peak memory 199836 kb
Host smart-78cca15c-7580-4d15-8b8f-541605876f9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049959941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1049959941
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1853759869
Short name T414
Test name
Test status
Simulation time 2852588840 ps
CPU time 18.85 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:16:05 PM PDT 24
Peak memory 199860 kb
Host smart-f2482970-bfc6-4d5c-9b15-f45c030a9ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853759869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1853759869
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.572469974
Short name T390
Test name
Test status
Simulation time 7546312130 ps
CPU time 664.26 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:26:50 PM PDT 24
Peak memory 665708 kb
Host smart-2e943db2-9026-4bd5-8040-e8cb20e37afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572469974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.572469974
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3475046561
Short name T228
Test name
Test status
Simulation time 11363096176 ps
CPU time 161.6 seconds
Started Aug 06 07:15:49 PM PDT 24
Finished Aug 06 07:18:31 PM PDT 24
Peak memory 199876 kb
Host smart-308a1bd3-5805-4dad-a52d-af05696bdeb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475046561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3475046561
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2023001491
Short name T150
Test name
Test status
Simulation time 7016577784 ps
CPU time 87.99 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:17:13 PM PDT 24
Peak memory 199908 kb
Host smart-ba16fe4a-9d00-4c79-8afa-027e30e368bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023001491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2023001491
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3114588318
Short name T489
Test name
Test status
Simulation time 720400086 ps
CPU time 1.56 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 199824 kb
Host smart-10583128-d10b-4911-b6ce-5cb5f7d089e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114588318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3114588318
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.365391264
Short name T526
Test name
Test status
Simulation time 5517803312 ps
CPU time 158.12 seconds
Started Aug 06 07:15:49 PM PDT 24
Finished Aug 06 07:18:27 PM PDT 24
Peak memory 216244 kb
Host smart-135991fa-0b56-46dc-97f0-e9b7b1de2bdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365391264 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.365391264
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1944460831
Short name T87
Test name
Test status
Simulation time 3787587680 ps
CPU time 66.69 seconds
Started Aug 06 07:15:44 PM PDT 24
Finished Aug 06 07:16:51 PM PDT 24
Peak memory 199972 kb
Host smart-d30a7458-45d7-4a5c-a511-07aa1b4063e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944460831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1944460831
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1669030346
Short name T510
Test name
Test status
Simulation time 14221871 ps
CPU time 0.64 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 195924 kb
Host smart-b1cc4edb-2ab2-4cac-969b-9861be8a89ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669030346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1669030346
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.945301622
Short name T16
Test name
Test status
Simulation time 787351191 ps
CPU time 44.39 seconds
Started Aug 06 07:15:49 PM PDT 24
Finished Aug 06 07:16:34 PM PDT 24
Peak memory 199864 kb
Host smart-365d71b8-de09-4d6d-986d-b50539e12278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945301622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.945301622
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3903125305
Short name T185
Test name
Test status
Simulation time 1966337689 ps
CPU time 14.54 seconds
Started Aug 06 07:15:50 PM PDT 24
Finished Aug 06 07:16:05 PM PDT 24
Peak memory 199848 kb
Host smart-0acd531f-1cd2-430b-b847-3f50cd9a8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903125305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3903125305
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.901087611
Short name T357
Test name
Test status
Simulation time 5096519346 ps
CPU time 959.97 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:31:47 PM PDT 24
Peak memory 761956 kb
Host smart-2469736f-128c-4693-982c-2c100e888ab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901087611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.901087611
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3928431440
Short name T287
Test name
Test status
Simulation time 2082974487 ps
CPU time 110.23 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:17:38 PM PDT 24
Peak memory 199836 kb
Host smart-2d767921-da66-41f6-9cbc-64d5c30ff0b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928431440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3928431440
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3882124076
Short name T234
Test name
Test status
Simulation time 4966359599 ps
CPU time 53.54 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:16:41 PM PDT 24
Peak memory 199996 kb
Host smart-c5316287-0d6f-4acc-8dea-a364c490ab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882124076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3882124076
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1615164755
Short name T327
Test name
Test status
Simulation time 1650127115 ps
CPU time 14.48 seconds
Started Aug 06 07:15:48 PM PDT 24
Finished Aug 06 07:16:02 PM PDT 24
Peak memory 199892 kb
Host smart-1ee1dd7a-7e87-4975-b782-ffae15dba89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615164755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1615164755
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.392131418
Short name T406
Test name
Test status
Simulation time 84190259568 ps
CPU time 4939.97 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 08:38:07 PM PDT 24
Peak memory 850148 kb
Host smart-ecfd2f8d-c9cd-42de-95c2-a32f875dd73a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392131418 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.392131418
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3607986990
Short name T111
Test name
Test status
Simulation time 11484041312 ps
CPU time 50.81 seconds
Started Aug 06 07:15:50 PM PDT 24
Finished Aug 06 07:16:41 PM PDT 24
Peak memory 199888 kb
Host smart-fb0673d4-e10a-469b-b6ca-9c886c881569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607986990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3607986990
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.714930346
Short name T433
Test name
Test status
Simulation time 14104631 ps
CPU time 0.59 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:15 PM PDT 24
Peak memory 195856 kb
Host smart-38591812-f4cf-4cca-b461-fb8894f956e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714930346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.714930346
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4013014595
Short name T266
Test name
Test status
Simulation time 2113045430 ps
CPU time 30.33 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:16:17 PM PDT 24
Peak memory 199852 kb
Host smart-2415cfd4-bfec-409a-b046-68f90859fc67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013014595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4013014595
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.914795688
Short name T132
Test name
Test status
Simulation time 2611747067 ps
CPU time 33.96 seconds
Started Aug 06 07:15:49 PM PDT 24
Finished Aug 06 07:16:23 PM PDT 24
Peak memory 199940 kb
Host smart-d4b141c0-e04d-4c99-bf31-c3a8e2c1a34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914795688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.914795688
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.626443653
Short name T516
Test name
Test status
Simulation time 5760780891 ps
CPU time 522.45 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:24:30 PM PDT 24
Peak memory 631944 kb
Host smart-02ad4627-555a-4ce4-a62d-6c03c0242a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626443653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.626443653
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3372411053
Short name T427
Test name
Test status
Simulation time 18118144251 ps
CPU time 155.61 seconds
Started Aug 06 07:15:47 PM PDT 24
Finished Aug 06 07:18:22 PM PDT 24
Peak memory 199956 kb
Host smart-77e24587-080c-4249-b27d-15ef4e7df9de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372411053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3372411053
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1134975279
Short name T344
Test name
Test status
Simulation time 21465424228 ps
CPU time 41.56 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:16:28 PM PDT 24
Peak memory 199948 kb
Host smart-8ece9f54-c282-4c13-86c8-478981b02eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134975279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1134975279
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.733906447
Short name T408
Test name
Test status
Simulation time 2105419901 ps
CPU time 6.94 seconds
Started Aug 06 07:15:46 PM PDT 24
Finished Aug 06 07:15:53 PM PDT 24
Peak memory 199724 kb
Host smart-27b3adb5-5689-4381-9d44-936be5537626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733906447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.733906447
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1429354070
Short name T83
Test name
Test status
Simulation time 5553845262 ps
CPU time 279 seconds
Started Aug 06 07:15:43 PM PDT 24
Finished Aug 06 07:20:22 PM PDT 24
Peak memory 199732 kb
Host smart-d9c0c926-92e9-4116-9063-6afea117c93f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429354070 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1429354070
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3191737476
Short name T85
Test name
Test status
Simulation time 16628207814 ps
CPU time 69.83 seconds
Started Aug 06 07:15:45 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 199912 kb
Host smart-265da83d-ec1a-4929-9d25-c6c09e164490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191737476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3191737476
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.579335067
Short name T160
Test name
Test status
Simulation time 12313699 ps
CPU time 0.6 seconds
Started Aug 06 07:16:17 PM PDT 24
Finished Aug 06 07:16:17 PM PDT 24
Peak memory 195616 kb
Host smart-966e8cc2-1ac7-4fd8-ba83-d30c8bb1f7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579335067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.579335067
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.624791156
Short name T23
Test name
Test status
Simulation time 867397519 ps
CPU time 51.11 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 199796 kb
Host smart-ec55619d-5d29-44e2-8e15-2b8131e5a7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=624791156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.624791156
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1578323647
Short name T291
Test name
Test status
Simulation time 10880623208 ps
CPU time 31.62 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:47 PM PDT 24
Peak memory 199964 kb
Host smart-5b03b2be-d4e3-4af3-9d70-f18d20097e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578323647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1578323647
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3488435407
Short name T26
Test name
Test status
Simulation time 3618756057 ps
CPU time 614.34 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:26:28 PM PDT 24
Peak memory 661364 kb
Host smart-c3a153a9-8098-484a-95a2-d572faaaf246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488435407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3488435407
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1282157688
Short name T232
Test name
Test status
Simulation time 13269126338 ps
CPU time 247.59 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:20:20 PM PDT 24
Peak memory 199952 kb
Host smart-e99c6190-3413-4c67-904d-4bd0f83f21ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282157688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1282157688
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2781050319
Short name T384
Test name
Test status
Simulation time 10773938963 ps
CPU time 190 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:19:24 PM PDT 24
Peak memory 199868 kb
Host smart-de80fddc-311e-43a3-8239-a0c647d8356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781050319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2781050319
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3026582046
Short name T461
Test name
Test status
Simulation time 7454120097 ps
CPU time 6.64 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:21 PM PDT 24
Peak memory 199932 kb
Host smart-38e08041-b047-4847-9604-d394438c6d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026582046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3026582046
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1255237608
Short name T508
Test name
Test status
Simulation time 51764755961 ps
CPU time 1000.31 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:32:53 PM PDT 24
Peak memory 641132 kb
Host smart-f98dad08-f729-4e21-b5b9-e9b69fde5a1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255237608 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1255237608
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3469864268
Short name T267
Test name
Test status
Simulation time 148449675 ps
CPU time 8.63 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:23 PM PDT 24
Peak memory 199736 kb
Host smart-ea04b5f8-193d-4583-b23f-4c66920c2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469864268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3469864268
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3170106833
Short name T515
Test name
Test status
Simulation time 27397790 ps
CPU time 0.56 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:15 PM PDT 24
Peak memory 195456 kb
Host smart-7d420135-f843-4650-8dc2-f0a2693ddcb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170106833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3170106833
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2455455059
Short name T504
Test name
Test status
Simulation time 3613055983 ps
CPU time 72.11 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 199944 kb
Host smart-885eb82a-3ad1-4f45-80a5-ba4441700f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2455455059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2455455059
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.926929765
Short name T298
Test name
Test status
Simulation time 28304842255 ps
CPU time 78.92 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 200088 kb
Host smart-0e0159d8-931d-46f3-a973-5d802a6e6f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926929765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.926929765
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.555341132
Short name T415
Test name
Test status
Simulation time 14470902 ps
CPU time 0.69 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:15 PM PDT 24
Peak memory 198108 kb
Host smart-1418a3b5-d8d0-4863-aea6-a5ff85504c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555341132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.555341132
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.937347038
Short name T325
Test name
Test status
Simulation time 17941037729 ps
CPU time 214.21 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:19:48 PM PDT 24
Peak memory 199916 kb
Host smart-a9401ef8-4895-4319-aadf-850438fa5747
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937347038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.937347038
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2758396002
Short name T285
Test name
Test status
Simulation time 4899153662 ps
CPU time 83.12 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:17:37 PM PDT 24
Peak memory 199928 kb
Host smart-9955cdf7-8744-438d-8e32-71ecf38953a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758396002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2758396002
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1445479569
Short name T275
Test name
Test status
Simulation time 309460617 ps
CPU time 3.6 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:16:16 PM PDT 24
Peak memory 199844 kb
Host smart-a76f2fe0-1d52-469a-a18f-e0577bd6b5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445479569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1445479569
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3513026241
Short name T380
Test name
Test status
Simulation time 86295464108 ps
CPU time 1336.62 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:38:29 PM PDT 24
Peak memory 735088 kb
Host smart-b021efdf-432c-4f38-ad68-09cbc3a4ac59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513026241 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3513026241
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1536087660
Short name T299
Test name
Test status
Simulation time 531592798 ps
CPU time 15.08 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:16:28 PM PDT 24
Peak memory 199832 kb
Host smart-bc46afaa-e381-4b04-b263-e0b8a7aed45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536087660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1536087660
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3625148235
Short name T423
Test name
Test status
Simulation time 61459656 ps
CPU time 0.54 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:16:14 PM PDT 24
Peak memory 194752 kb
Host smart-ce7b97fc-b312-46d1-bf03-2dddd814637b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625148235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3625148235
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1206774561
Short name T167
Test name
Test status
Simulation time 6046357365 ps
CPU time 98.28 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:53 PM PDT 24
Peak memory 199892 kb
Host smart-3336baf9-bda4-48d1-9e1e-645bcf558cde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206774561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1206774561
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3338905923
Short name T475
Test name
Test status
Simulation time 1052992525 ps
CPU time 55.24 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 199844 kb
Host smart-dbdeb040-e6c4-463d-97ae-844f4586434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338905923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3338905923
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.629896322
Short name T268
Test name
Test status
Simulation time 5993819574 ps
CPU time 1067.61 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:34:00 PM PDT 24
Peak memory 684720 kb
Host smart-7b6ffcbd-964c-49b9-a63e-65b17889eb96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629896322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.629896322
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1902338296
Short name T419
Test name
Test status
Simulation time 10098641055 ps
CPU time 284.06 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:20:57 PM PDT 24
Peak memory 199864 kb
Host smart-5e6b4993-361c-4e49-b167-037f079b9286
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902338296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1902338296
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2343929054
Short name T328
Test name
Test status
Simulation time 12792008696 ps
CPU time 41.07 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 199936 kb
Host smart-2c71a48d-2270-442c-9a74-9e11cab85a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343929054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2343929054
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2278820502
Short name T235
Test name
Test status
Simulation time 1387985847 ps
CPU time 3.94 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:16:16 PM PDT 24
Peak memory 199900 kb
Host smart-b1a687ce-a887-4ec4-ace4-62e4b6520299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278820502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2278820502
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1790281185
Short name T193
Test name
Test status
Simulation time 7048985428 ps
CPU time 113.13 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:18:07 PM PDT 24
Peak memory 199824 kb
Host smart-d6320de9-43a5-469e-a74a-7b7e41938246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790281185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1790281185
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.56563299
Short name T484
Test name
Test status
Simulation time 14170710835 ps
CPU time 94.8 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:17:49 PM PDT 24
Peak memory 199836 kb
Host smart-d3eaf4ae-11c5-4a36-b0ba-bf7eecf24072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56563299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.56563299
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1015906741
Short name T262
Test name
Test status
Simulation time 21087396 ps
CPU time 0.58 seconds
Started Aug 06 07:16:16 PM PDT 24
Finished Aug 06 07:16:16 PM PDT 24
Peak memory 194780 kb
Host smart-6f75ca1c-9a76-43e9-9846-2dd8e91877ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015906741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1015906741
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2111730233
Short name T183
Test name
Test status
Simulation time 234174223 ps
CPU time 13.01 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:16:26 PM PDT 24
Peak memory 199852 kb
Host smart-fbc5d0d5-c316-410c-9924-b55a180ad7b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111730233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2111730233
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1693496376
Short name T421
Test name
Test status
Simulation time 761898938 ps
CPU time 13.07 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:28 PM PDT 24
Peak memory 199756 kb
Host smart-1571d9f2-d9c1-46e9-83c9-3d2b1c18ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693496376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1693496376
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3334605311
Short name T146
Test name
Test status
Simulation time 5818757817 ps
CPU time 987.41 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:32:42 PM PDT 24
Peak memory 691544 kb
Host smart-cde716b8-00e9-4798-8536-8b630c597034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334605311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3334605311
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2843512468
Short name T492
Test name
Test status
Simulation time 19553512759 ps
CPU time 133.51 seconds
Started Aug 06 07:16:17 PM PDT 24
Finished Aug 06 07:18:31 PM PDT 24
Peak memory 199852 kb
Host smart-49cbcb99-6736-42c6-b3a3-ea769846af36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843512468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2843512468
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1110594265
Short name T523
Test name
Test status
Simulation time 22824386451 ps
CPU time 151.76 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:18:47 PM PDT 24
Peak memory 215292 kb
Host smart-50afeaf7-1c64-4e7a-837d-260e55292d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110594265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1110594265
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3493571630
Short name T304
Test name
Test status
Simulation time 296028115 ps
CPU time 13.94 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:28 PM PDT 24
Peak memory 199784 kb
Host smart-349bbd93-a56c-449d-a30f-f0d0abd14af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493571630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3493571630
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1363327270
Short name T223
Test name
Test status
Simulation time 738626728058 ps
CPU time 2420.85 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:56:35 PM PDT 24
Peak memory 771416 kb
Host smart-027f0c1a-7b41-4ce3-8d67-f1ee95300142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363327270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1363327270
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1790257413
Short name T472
Test name
Test status
Simulation time 3986755883 ps
CPU time 74.25 seconds
Started Aug 06 07:16:16 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 199784 kb
Host smart-5bbeff14-59e2-4bc4-99a4-1cedda319925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790257413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1790257413
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2682819039
Short name T44
Test name
Test status
Simulation time 29465144 ps
CPU time 0.57 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:16 PM PDT 24
Peak memory 194876 kb
Host smart-eb2cdb3b-b7e5-48dd-b9e5-217458b5d6da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682819039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2682819039
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1882809190
Short name T55
Test name
Test status
Simulation time 1174439381 ps
CPU time 34.47 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:48 PM PDT 24
Peak memory 199688 kb
Host smart-12fea8db-dcdb-4771-90e1-6bea1c311435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882809190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1882809190
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3239133484
Short name T161
Test name
Test status
Simulation time 2371347801 ps
CPU time 22.27 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 199956 kb
Host smart-ee3376e9-2ff6-4f11-b00a-1d672e4dca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239133484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3239133484
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3116857377
Short name T318
Test name
Test status
Simulation time 4573794816 ps
CPU time 443.67 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:23:38 PM PDT 24
Peak memory 501156 kb
Host smart-308780fd-dc32-4d1e-a89f-8730335cdd24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116857377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3116857377
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.752762341
Short name T30
Test name
Test status
Simulation time 2068723069 ps
CPU time 21.93 seconds
Started Aug 06 07:16:11 PM PDT 24
Finished Aug 06 07:16:33 PM PDT 24
Peak memory 199712 kb
Host smart-be56c054-9eae-4fa9-a7a4-63f49f5245d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752762341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.752762341
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2445385931
Short name T480
Test name
Test status
Simulation time 17568251599 ps
CPU time 98.38 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:52 PM PDT 24
Peak memory 199820 kb
Host smart-2c1ef8a7-9ed0-415f-a273-74d375b64c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445385931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2445385931
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.562099417
Short name T320
Test name
Test status
Simulation time 107038046 ps
CPU time 1.37 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:16:14 PM PDT 24
Peak memory 199780 kb
Host smart-a8d39c2a-27bb-456b-b0bd-0137471696f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562099417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.562099417
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4232230558
Short name T307
Test name
Test status
Simulation time 12237359870 ps
CPU time 1116.45 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:34:51 PM PDT 24
Peak memory 711896 kb
Host smart-c6ac09ff-735b-4723-a215-9e544a2d4415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232230558 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4232230558
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1625505661
Short name T485
Test name
Test status
Simulation time 7944783461 ps
CPU time 102.47 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:57 PM PDT 24
Peak memory 199868 kb
Host smart-8b27dc6b-fe70-49e9-a225-8e984ec24421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625505661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1625505661
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2578114275
Short name T209
Test name
Test status
Simulation time 31101963 ps
CPU time 0.58 seconds
Started Aug 06 07:14:35 PM PDT 24
Finished Aug 06 07:14:35 PM PDT 24
Peak memory 195928 kb
Host smart-43023139-6b3f-47c6-9589-9e4816412733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578114275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2578114275
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3284833415
Short name T12
Test name
Test status
Simulation time 349620889 ps
CPU time 20.24 seconds
Started Aug 06 07:14:36 PM PDT 24
Finished Aug 06 07:14:57 PM PDT 24
Peak memory 199808 kb
Host smart-d6d21f3c-47df-495c-8898-4ad6f3d49cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284833415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3284833415
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3743875817
Short name T453
Test name
Test status
Simulation time 5365666560 ps
CPU time 48.7 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:15:19 PM PDT 24
Peak memory 199796 kb
Host smart-1af034c1-aa1f-4ba9-a3f0-888ff4c5a035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743875817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3743875817
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1686866841
Short name T248
Test name
Test status
Simulation time 3511615824 ps
CPU time 624.64 seconds
Started Aug 06 07:14:33 PM PDT 24
Finished Aug 06 07:24:58 PM PDT 24
Peak memory 676756 kb
Host smart-e34cf1d5-d795-44bb-97dc-3fab910736fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686866841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1686866841
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2865771453
Short name T181
Test name
Test status
Simulation time 26917684705 ps
CPU time 206.54 seconds
Started Aug 06 07:14:36 PM PDT 24
Finished Aug 06 07:18:03 PM PDT 24
Peak memory 199812 kb
Host smart-ee9495bb-4de7-469c-8927-5405e5adca70
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865771453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2865771453
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.344688322
Short name T374
Test name
Test status
Simulation time 5053623228 ps
CPU time 67.99 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:15:42 PM PDT 24
Peak memory 199916 kb
Host smart-141faeca-d42b-4f4e-9e46-5b6685d45b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344688322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.344688322
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1170599834
Short name T48
Test name
Test status
Simulation time 57670130 ps
CPU time 0.9 seconds
Started Aug 06 07:14:38 PM PDT 24
Finished Aug 06 07:14:40 PM PDT 24
Peak memory 218424 kb
Host smart-6ec64497-1e76-4be7-b8d1-8e5477dba332
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170599834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1170599834
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.985811058
Short name T187
Test name
Test status
Simulation time 123783957 ps
CPU time 5.17 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:14:36 PM PDT 24
Peak memory 199892 kb
Host smart-efae1e62-1a73-46dc-9113-c9b15af29845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985811058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.985811058
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.827284546
Short name T297
Test name
Test status
Simulation time 10990718460 ps
CPU time 89.43 seconds
Started Aug 06 07:14:37 PM PDT 24
Finished Aug 06 07:16:07 PM PDT 24
Peak memory 199460 kb
Host smart-5f76a7ac-d0af-467c-95e3-0b90abfedb3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827284546 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.827284546
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.908326472
Short name T382
Test name
Test status
Simulation time 4792702032 ps
CPU time 72.64 seconds
Started Aug 06 07:14:38 PM PDT 24
Finished Aug 06 07:15:51 PM PDT 24
Peak memory 199868 kb
Host smart-ba502256-5f5c-44e6-b062-271cdee13d56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=908326472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.908326472
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.384529160
Short name T264
Test name
Test status
Simulation time 6408371235 ps
CPU time 52.14 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:15:22 PM PDT 24
Peak memory 199892 kb
Host smart-f2dbb63b-d00d-474b-baf5-513e7cc887ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=384529160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.384529160
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3619764342
Short name T177
Test name
Test status
Simulation time 14410858601 ps
CPU time 143.83 seconds
Started Aug 06 07:14:38 PM PDT 24
Finished Aug 06 07:17:02 PM PDT 24
Peak memory 199960 kb
Host smart-87ec54ab-620b-4a56-a3ed-d286b614d612
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3619764342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3619764342
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3256338147
Short name T437
Test name
Test status
Simulation time 53950369344 ps
CPU time 615.32 seconds
Started Aug 06 07:14:37 PM PDT 24
Finished Aug 06 07:24:53 PM PDT 24
Peak memory 199768 kb
Host smart-df38d4c6-5d33-44c8-8254-e0b0f7a71fe3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3256338147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3256338147
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1426161387
Short name T428
Test name
Test status
Simulation time 435353179703 ps
CPU time 2610.3 seconds
Started Aug 06 07:14:33 PM PDT 24
Finished Aug 06 07:58:03 PM PDT 24
Peak memory 215248 kb
Host smart-3d4457fa-9b0d-41f0-86d8-5e4e27ca9926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1426161387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1426161387
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3778181952
Short name T123
Test name
Test status
Simulation time 417837152423 ps
CPU time 2566.01 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:57:16 PM PDT 24
Peak memory 215284 kb
Host smart-09e278de-2261-40c2-8d23-d6ff04ffa74a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3778181952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3778181952
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2070422017
Short name T110
Test name
Test status
Simulation time 15160764504 ps
CPU time 107.01 seconds
Started Aug 06 07:14:35 PM PDT 24
Finished Aug 06 07:16:23 PM PDT 24
Peak memory 199872 kb
Host smart-bc824a27-b18d-4c93-a653-da2f3e2bd257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070422017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2070422017
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4003194154
Short name T394
Test name
Test status
Simulation time 11222793 ps
CPU time 0.58 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:16 PM PDT 24
Peak memory 194960 kb
Host smart-a015f547-68c7-434f-82e7-595bc4140eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003194154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4003194154
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1756859016
Short name T293
Test name
Test status
Simulation time 4587074750 ps
CPU time 69.61 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:17:24 PM PDT 24
Peak memory 208112 kb
Host smart-ae030440-d305-4f54-a73b-d259a13fc052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756859016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1756859016
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3964361368
Short name T481
Test name
Test status
Simulation time 1680699453 ps
CPU time 14.66 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:16:27 PM PDT 24
Peak memory 199716 kb
Host smart-92e9ff88-3629-4f76-ab11-ba45fb8442e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964361368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3964361368
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2786765220
Short name T52
Test name
Test status
Simulation time 14910647440 ps
CPU time 541.9 seconds
Started Aug 06 07:16:13 PM PDT 24
Finished Aug 06 07:25:16 PM PDT 24
Peak memory 647896 kb
Host smart-14ed60aa-572a-481f-8835-5f1a1de4d859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786765220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2786765220
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2033183845
Short name T34
Test name
Test status
Simulation time 733931368 ps
CPU time 20.13 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:35 PM PDT 24
Peak memory 199828 kb
Host smart-0a418adc-b79d-4229-a946-822ef7087f56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033183845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2033183845
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3040725221
Short name T189
Test name
Test status
Simulation time 4731768290 ps
CPU time 32.62 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:48 PM PDT 24
Peak memory 199884 kb
Host smart-a19a0373-34af-4f59-b5ca-df1ab0df4764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040725221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3040725221
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2540107074
Short name T224
Test name
Test status
Simulation time 15507223 ps
CPU time 0.67 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:16 PM PDT 24
Peak memory 196208 kb
Host smart-6fa8a5b0-a190-434c-8ed9-c355d37f5e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540107074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2540107074
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3873236443
Short name T130
Test name
Test status
Simulation time 4089332100 ps
CPU time 207.31 seconds
Started Aug 06 07:16:16 PM PDT 24
Finished Aug 06 07:19:43 PM PDT 24
Peak memory 199924 kb
Host smart-12720a80-a481-4172-ab7f-e2adb24dddc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873236443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3873236443
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4248482077
Short name T206
Test name
Test status
Simulation time 1982374649 ps
CPU time 36.46 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 199836 kb
Host smart-af06d901-2ea3-4de3-8f4b-037fa610bb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248482077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4248482077
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.296725075
Short name T456
Test name
Test status
Simulation time 44397093 ps
CPU time 0.59 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 195612 kb
Host smart-3fd0869d-3767-4355-b9cd-6f5eafe2b82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296725075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.296725075
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2726721274
Short name T143
Test name
Test status
Simulation time 924912311 ps
CPU time 26.68 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:16:41 PM PDT 24
Peak memory 199820 kb
Host smart-807645a4-8fd6-4fb6-a376-15c17fe4a189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726721274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2726721274
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.707610005
Short name T173
Test name
Test status
Simulation time 101450673 ps
CPU time 2.62 seconds
Started Aug 06 07:16:16 PM PDT 24
Finished Aug 06 07:16:18 PM PDT 24
Peak memory 199724 kb
Host smart-9078e1b7-1811-40e3-a1bb-90fa1b3848a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707610005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.707610005
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3079404413
Short name T29
Test name
Test status
Simulation time 28072692770 ps
CPU time 956.49 seconds
Started Aug 06 07:16:14 PM PDT 24
Finished Aug 06 07:32:11 PM PDT 24
Peak memory 668492 kb
Host smart-769ebfea-cda7-4b71-b556-9c35d6f000f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079404413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3079404413
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2979353804
Short name T294
Test name
Test status
Simulation time 3637356662 ps
CPU time 45.24 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 199788 kb
Host smart-b86ee652-0451-492f-aace-1c05adf1a987
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979353804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2979353804
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3411029446
Short name T459
Test name
Test status
Simulation time 3653144427 ps
CPU time 96.01 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:17:48 PM PDT 24
Peak memory 199856 kb
Host smart-c6f3a014-1e62-46d2-8450-b9c80ab8166b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411029446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3411029446
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1728658834
Short name T158
Test name
Test status
Simulation time 269922909 ps
CPU time 11.82 seconds
Started Aug 06 07:16:12 PM PDT 24
Finished Aug 06 07:16:24 PM PDT 24
Peak memory 199804 kb
Host smart-832b68b2-6585-45bd-89df-0bd1940c82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728658834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1728658834
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2157054918
Short name T109
Test name
Test status
Simulation time 86037858593 ps
CPU time 583.79 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:25:59 PM PDT 24
Peak memory 680560 kb
Host smart-14510351-3174-4fc4-a529-0c02f1ff853e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157054918 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2157054918
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.637626770
Short name T82
Test name
Test status
Simulation time 7407443492 ps
CPU time 106.93 seconds
Started Aug 06 07:16:15 PM PDT 24
Finished Aug 06 07:18:02 PM PDT 24
Peak memory 199904 kb
Host smart-491d7bfa-f290-4d3a-b378-e56eae95c0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637626770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.637626770
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.262318655
Short name T312
Test name
Test status
Simulation time 18566560 ps
CPU time 0.59 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:16:32 PM PDT 24
Peak memory 195704 kb
Host smart-0dd4b68a-59ac-429b-80ef-bf1f7920f2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262318655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.262318655
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3480335110
Short name T42
Test name
Test status
Simulation time 1065019021 ps
CPU time 28.36 seconds
Started Aug 06 07:16:28 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 199884 kb
Host smart-e1426041-b974-4791-9682-5eba72821e64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480335110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3480335110
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1030574556
Short name T303
Test name
Test status
Simulation time 3089505283 ps
CPU time 15.39 seconds
Started Aug 06 07:16:28 PM PDT 24
Finished Aug 06 07:16:44 PM PDT 24
Peak memory 199992 kb
Host smart-30de86b6-b59a-409f-8d28-6b59ff451eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030574556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1030574556
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1592199066
Short name T246
Test name
Test status
Simulation time 1188563570 ps
CPU time 30.64 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:16:59 PM PDT 24
Peak memory 243480 kb
Host smart-ae75636f-05fe-4a6a-9f0e-125c7b544142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592199066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1592199066
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1037945541
Short name T255
Test name
Test status
Simulation time 9533018211 ps
CPU time 165.5 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:19:16 PM PDT 24
Peak memory 199900 kb
Host smart-2435a7be-8121-497c-88a9-8e87e3592ea1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037945541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1037945541
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1427399918
Short name T265
Test name
Test status
Simulation time 13558628423 ps
CPU time 187.57 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:19:38 PM PDT 24
Peak memory 216312 kb
Host smart-20eec7e4-b762-477b-be97-88e1a02242d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427399918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1427399918
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1325518700
Short name T302
Test name
Test status
Simulation time 638976941 ps
CPU time 3.26 seconds
Started Aug 06 07:16:33 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 199836 kb
Host smart-c2b5f1f6-3366-4986-abc4-2de5d314f0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325518700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1325518700
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.767570728
Short name T349
Test name
Test status
Simulation time 95954220280 ps
CPU time 3466.44 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 08:14:16 PM PDT 24
Peak memory 853004 kb
Host smart-3dbeeb8f-8085-4af6-beff-c447441d4189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767570728 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.767570728
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2983822197
Short name T449
Test name
Test status
Simulation time 11008264561 ps
CPU time 137.19 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:18:48 PM PDT 24
Peak memory 199940 kb
Host smart-a264afe8-02b1-4321-b5cb-77583324ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983822197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2983822197
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3000339769
Short name T197
Test name
Test status
Simulation time 49030978 ps
CPU time 0.6 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 195876 kb
Host smart-6bdd6512-6e73-44c3-8a1c-62986daaa7b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000339769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3000339769
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2456743386
Short name T4
Test name
Test status
Simulation time 613859929 ps
CPU time 8.98 seconds
Started Aug 06 07:16:33 PM PDT 24
Finished Aug 06 07:16:42 PM PDT 24
Peak memory 199824 kb
Host smart-b2456873-3614-4479-b3f3-aac136f084e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456743386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2456743386
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3799524249
Short name T125
Test name
Test status
Simulation time 1355951713 ps
CPU time 20.66 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:16:50 PM PDT 24
Peak memory 199692 kb
Host smart-a91e49e8-0188-42a8-8a2e-2a8c183ecb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799524249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3799524249
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2685472942
Short name T184
Test name
Test status
Simulation time 14731622412 ps
CPU time 397.96 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:23:08 PM PDT 24
Peak memory 670692 kb
Host smart-a61b9d4f-b4c4-4968-a60e-c29e723f3931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685472942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2685472942
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3193249287
Short name T499
Test name
Test status
Simulation time 15713553868 ps
CPU time 211.06 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:20:02 PM PDT 24
Peak memory 199960 kb
Host smart-9658441a-c666-4828-9c7d-08f2fcde1fb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193249287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3193249287
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1379416977
Short name T170
Test name
Test status
Simulation time 2878484516 ps
CPU time 43.61 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:17:14 PM PDT 24
Peak memory 199912 kb
Host smart-7c8ef5e5-59d1-49f0-8b5b-1f6d57281d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379416977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1379416977
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2727996440
Short name T500
Test name
Test status
Simulation time 146930331 ps
CPU time 2.01 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:16:33 PM PDT 24
Peak memory 199848 kb
Host smart-84d6fc98-9735-49b5-af21-ba8bba6999ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727996440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2727996440
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4242097317
Short name T151
Test name
Test status
Simulation time 59372181454 ps
CPU time 1494.35 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:41:28 PM PDT 24
Peak memory 678756 kb
Host smart-beee8a43-a405-4ed4-a8ee-7bcf9a316588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242097317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4242097317
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1005061542
Short name T168
Test name
Test status
Simulation time 50800463831 ps
CPU time 55.07 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:17:26 PM PDT 24
Peak memory 199868 kb
Host smart-4f3dc17f-dae9-4bac-9893-7ed78d06a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005061542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1005061542
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.767478684
Short name T518
Test name
Test status
Simulation time 17954863 ps
CPU time 0.58 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:16:33 PM PDT 24
Peak memory 195904 kb
Host smart-9cced447-f310-4214-bee3-9469831691b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767478684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.767478684
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.849566809
Short name T134
Test name
Test status
Simulation time 581675890 ps
CPU time 16.45 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:16:45 PM PDT 24
Peak memory 199752 kb
Host smart-17e80ac2-73bf-4ad9-b02e-569719901e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849566809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.849566809
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.472119542
Short name T385
Test name
Test status
Simulation time 917108268 ps
CPU time 51.07 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:17:21 PM PDT 24
Peak memory 199844 kb
Host smart-2792c98a-7e1f-420e-a32a-a035be3f4996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472119542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.472119542
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3496411322
Short name T281
Test name
Test status
Simulation time 24912173619 ps
CPU time 1186.8 seconds
Started Aug 06 07:16:27 PM PDT 24
Finished Aug 06 07:36:14 PM PDT 24
Peak memory 767148 kb
Host smart-81f37ddb-3ac6-414e-bc1f-8219722d457d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496411322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3496411322
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.522123048
Short name T208
Test name
Test status
Simulation time 50457768071 ps
CPU time 133.94 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:18:43 PM PDT 24
Peak memory 199848 kb
Host smart-e6b16f72-2993-4366-9b70-6699ec510b77
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522123048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.522123048
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3417148124
Short name T154
Test name
Test status
Simulation time 29050408609 ps
CPU time 85.63 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:18:00 PM PDT 24
Peak memory 200012 kb
Host smart-80ed97da-429e-415a-a0b9-3494f2b6199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417148124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3417148124
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.14051196
Short name T142
Test name
Test status
Simulation time 84776083 ps
CPU time 4.17 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:34 PM PDT 24
Peak memory 199824 kb
Host smart-75dfb184-a39f-45ce-b748-a76877e02221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14051196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.14051196
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3060466911
Short name T507
Test name
Test status
Simulation time 83752863677 ps
CPU time 3908.94 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 08:21:39 PM PDT 24
Peak memory 839904 kb
Host smart-944fdec7-6e31-4595-b066-5b5a31b6f8d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060466911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3060466911
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1145563395
Short name T413
Test name
Test status
Simulation time 310287498 ps
CPU time 11.69 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:42 PM PDT 24
Peak memory 199776 kb
Host smart-77c4c024-36d6-434e-8cd6-3d1edd5230db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145563395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1145563395
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1479901590
Short name T172
Test name
Test status
Simulation time 51553560 ps
CPU time 0.6 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 195928 kb
Host smart-04174a0b-17a7-4c9e-94dc-0dd57019cbf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479901590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1479901590
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.658671128
Short name T79
Test name
Test status
Simulation time 1403135035 ps
CPU time 83.54 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:17:55 PM PDT 24
Peak memory 199720 kb
Host smart-a6fe32dd-1bf3-49df-9db0-0e63ea2420a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=658671128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.658671128
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.70322292
Short name T368
Test name
Test status
Simulation time 1238683809 ps
CPU time 21.29 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 199780 kb
Host smart-725b0c9c-d887-42c1-a010-4632ecd73f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70322292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.70322292
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3520062656
Short name T247
Test name
Test status
Simulation time 46724546144 ps
CPU time 629.71 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:27:01 PM PDT 24
Peak memory 701812 kb
Host smart-d02fad86-c05d-43fb-8b0a-0b4ca68c3537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520062656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3520062656
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.541463885
Short name T194
Test name
Test status
Simulation time 940826160 ps
CPU time 28.44 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:17:03 PM PDT 24
Peak memory 199732 kb
Host smart-3e416157-bbb8-4019-8295-6c439c19378e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541463885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.541463885
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1872686994
Short name T221
Test name
Test status
Simulation time 2242729109 ps
CPU time 127.2 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:18:39 PM PDT 24
Peak memory 199848 kb
Host smart-28ce719d-33ed-4932-ad99-3b363c3f03aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872686994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1872686994
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2750074255
Short name T259
Test name
Test status
Simulation time 49794687 ps
CPU time 1.41 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 199724 kb
Host smart-b6b59885-8a3b-4243-8384-cd2861a5741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750074255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2750074255
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.866379889
Short name T505
Test name
Test status
Simulation time 90960181871 ps
CPU time 2156.71 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:52:26 PM PDT 24
Peak memory 729688 kb
Host smart-4ee849ef-2ea5-4aea-a49b-fe54269973e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866379889 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.866379889
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4288830010
Short name T420
Test name
Test status
Simulation time 2293804881 ps
CPU time 40.44 seconds
Started Aug 06 07:16:29 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 199844 kb
Host smart-86d566d7-d249-49f4-9498-2dd3ad45287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288830010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4288830010
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2891834283
Short name T467
Test name
Test status
Simulation time 38985730 ps
CPU time 0.58 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:16:33 PM PDT 24
Peak memory 195968 kb
Host smart-10ba4839-4180-497c-bdd3-485df45c54ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891834283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2891834283
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2285102333
Short name T333
Test name
Test status
Simulation time 208753220 ps
CPU time 11.74 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:16:46 PM PDT 24
Peak memory 199748 kb
Host smart-738a9eda-968d-4822-b074-8e030480eddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285102333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2285102333
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2388589114
Short name T192
Test name
Test status
Simulation time 25795944066 ps
CPU time 323.42 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:21:56 PM PDT 24
Peak memory 664644 kb
Host smart-a4d6f88f-7e43-46f5-a76f-424ea7fcd2b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388589114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2388589114
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.4259287001
Short name T31
Test name
Test status
Simulation time 22536362532 ps
CPU time 75.89 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:17:48 PM PDT 24
Peak memory 199876 kb
Host smart-ea02090d-c8a2-4e87-8095-e47781f1dea7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259287001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4259287001
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.753866623
Short name T66
Test name
Test status
Simulation time 9938535568 ps
CPU time 113.2 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:18:25 PM PDT 24
Peak memory 200112 kb
Host smart-bc5ba287-c0f9-404d-a9b6-325e024b751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753866623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.753866623
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1844120174
Short name T457
Test name
Test status
Simulation time 19125827 ps
CPU time 0.69 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:16:31 PM PDT 24
Peak memory 196396 kb
Host smart-148fbd1a-521f-441f-b19c-caa7736b6068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844120174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1844120174
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1809593256
Short name T25
Test name
Test status
Simulation time 26268664142 ps
CPU time 675.52 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:27:48 PM PDT 24
Peak memory 660876 kb
Host smart-84a8ea9e-347b-4e8e-8221-269c452a8c7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809593256 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1809593256
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1638011903
Short name T261
Test name
Test status
Simulation time 6448191942 ps
CPU time 90.57 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:18:02 PM PDT 24
Peak memory 199836 kb
Host smart-06852c1c-8a86-4d12-92c5-955e0c3067d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638011903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1638011903
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3079968086
Short name T503
Test name
Test status
Simulation time 41183020 ps
CPU time 0.54 seconds
Started Aug 06 07:16:37 PM PDT 24
Finished Aug 06 07:16:37 PM PDT 24
Peak memory 194900 kb
Host smart-a60cc3e6-af54-4eee-9dc3-a7e43ad4fe0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079968086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3079968086
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2246496488
Short name T395
Test name
Test status
Simulation time 6257120258 ps
CPU time 66.22 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:17:38 PM PDT 24
Peak memory 216244 kb
Host smart-fe6482fb-bd59-4e8e-93d7-c04f00b4df81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246496488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2246496488
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4018667728
Short name T334
Test name
Test status
Simulation time 233447207 ps
CPU time 12.25 seconds
Started Aug 06 07:16:33 PM PDT 24
Finished Aug 06 07:16:45 PM PDT 24
Peak memory 199872 kb
Host smart-e2d5d7bc-9407-4739-a886-8aced1fd985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018667728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4018667728
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2052750258
Short name T339
Test name
Test status
Simulation time 21017146789 ps
CPU time 1053.24 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:34:08 PM PDT 24
Peak memory 749088 kb
Host smart-1f43b34d-4f9a-48c9-8d42-542cd475fb93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052750258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2052750258
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2738534096
Short name T389
Test name
Test status
Simulation time 46908746612 ps
CPU time 97.15 seconds
Started Aug 06 07:16:35 PM PDT 24
Finished Aug 06 07:18:12 PM PDT 24
Peak memory 199824 kb
Host smart-521449d6-2149-4345-aa9b-a42531fe088d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738534096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2738534096
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2022209898
Short name T256
Test name
Test status
Simulation time 827977506 ps
CPU time 3.39 seconds
Started Aug 06 07:16:33 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 199780 kb
Host smart-435c57c0-ed98-414a-8776-542dfcd64e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022209898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2022209898
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.481524008
Short name T482
Test name
Test status
Simulation time 2248449109 ps
CPU time 13.97 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:16:46 PM PDT 24
Peak memory 199956 kb
Host smart-d1450f76-2038-4d2c-b391-908da4c6dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481524008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.481524008
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.101712319
Short name T316
Test name
Test status
Simulation time 222566408721 ps
CPU time 366.87 seconds
Started Aug 06 07:16:35 PM PDT 24
Finished Aug 06 07:22:42 PM PDT 24
Peak memory 208100 kb
Host smart-31c5a9fd-1ddc-4e72-bd02-8fe672284fa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101712319 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.101712319
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3389224024
Short name T282
Test name
Test status
Simulation time 75489086761 ps
CPU time 126.87 seconds
Started Aug 06 07:16:36 PM PDT 24
Finished Aug 06 07:18:43 PM PDT 24
Peak memory 199960 kb
Host smart-1df2828b-e1b2-4fad-8dab-87d3c6188064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389224024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3389224024
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2583985914
Short name T442
Test name
Test status
Simulation time 68931681 ps
CPU time 0.63 seconds
Started Aug 06 07:16:36 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 194896 kb
Host smart-ab06e3a6-7225-4912-9a51-299de19567c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583985914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2583985914
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3250998103
Short name T473
Test name
Test status
Simulation time 1204181552 ps
CPU time 64.21 seconds
Started Aug 06 07:16:30 PM PDT 24
Finished Aug 06 07:17:34 PM PDT 24
Peak memory 199840 kb
Host smart-37b38d44-91ca-4f12-8c72-0c15c853fa1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3250998103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3250998103
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.863486411
Short name T14
Test name
Test status
Simulation time 2525805502 ps
CPU time 32.92 seconds
Started Aug 06 07:16:31 PM PDT 24
Finished Aug 06 07:17:04 PM PDT 24
Peak memory 199864 kb
Host smart-76eb26be-ad8e-4759-a8de-4a3a5fa891e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863486411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.863486411
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3826695234
Short name T68
Test name
Test status
Simulation time 5626695892 ps
CPU time 1045.68 seconds
Started Aug 06 07:16:33 PM PDT 24
Finished Aug 06 07:33:59 PM PDT 24
Peak memory 740904 kb
Host smart-ba67d36e-f5e3-4e68-bf13-00eab7a02dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826695234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3826695234
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3345703197
Short name T403
Test name
Test status
Simulation time 4875951452 ps
CPU time 73.56 seconds
Started Aug 06 07:16:36 PM PDT 24
Finished Aug 06 07:17:50 PM PDT 24
Peak memory 199872 kb
Host smart-dc0fc418-7631-4ca3-8195-2787cda2332c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345703197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3345703197
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1809452463
Short name T393
Test name
Test status
Simulation time 13295730389 ps
CPU time 163.08 seconds
Started Aug 06 07:16:36 PM PDT 24
Finished Aug 06 07:19:19 PM PDT 24
Peak memory 199900 kb
Host smart-603498f2-40cc-4431-8527-35eef7dbab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809452463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1809452463
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1609129169
Short name T39
Test name
Test status
Simulation time 1478180728 ps
CPU time 13.09 seconds
Started Aug 06 07:16:35 PM PDT 24
Finished Aug 06 07:16:48 PM PDT 24
Peak memory 199824 kb
Host smart-271c845a-2295-4317-90e6-7969d5b5c6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609129169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1609129169
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1721327820
Short name T71
Test name
Test status
Simulation time 649127968081 ps
CPU time 2725.59 seconds
Started Aug 06 07:16:36 PM PDT 24
Finished Aug 06 08:02:02 PM PDT 24
Peak memory 747900 kb
Host smart-1fcf5c57-5483-4c8a-88ce-79e91849686d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721327820 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1721327820
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.187537762
Short name T478
Test name
Test status
Simulation time 3901974308 ps
CPU time 51.88 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:17:26 PM PDT 24
Peak memory 199924 kb
Host smart-73493d52-c8a8-406c-8d78-56b7cfe1af9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187537762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.187537762
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3517358136
Short name T244
Test name
Test status
Simulation time 10881193 ps
CPU time 0.6 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:51 PM PDT 24
Peak memory 195772 kb
Host smart-0b669d13-75d1-4715-afa3-d144184ec8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517358136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3517358136
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1172726744
Short name T295
Test name
Test status
Simulation time 3790687175 ps
CPU time 53.27 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 199912 kb
Host smart-d0a63ed9-69a5-49b3-a125-3d7a611021b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172726744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1172726744
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1771931059
Short name T2
Test name
Test status
Simulation time 1925428041 ps
CPU time 48.59 seconds
Started Aug 06 07:16:33 PM PDT 24
Finished Aug 06 07:17:21 PM PDT 24
Peak memory 199816 kb
Host smart-876f479f-bbc4-4316-9496-808ea796605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771931059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1771931059
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2074195914
Short name T399
Test name
Test status
Simulation time 6081573399 ps
CPU time 241.34 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:20:34 PM PDT 24
Peak memory 480648 kb
Host smart-c8822b8d-fe25-46c6-98fe-d0d492c03b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2074195914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2074195914
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1832404405
Short name T290
Test name
Test status
Simulation time 16195513363 ps
CPU time 215.95 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:20:26 PM PDT 24
Peak memory 199940 kb
Host smart-810d535d-fbbc-40e0-a84a-c32d4be626fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832404405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1832404405
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1809981708
Short name T58
Test name
Test status
Simulation time 65646899620 ps
CPU time 206.18 seconds
Started Aug 06 07:16:32 PM PDT 24
Finished Aug 06 07:19:59 PM PDT 24
Peak memory 199864 kb
Host smart-8de03709-f889-405b-ba05-7e78e4e67069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809981708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1809981708
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3425690904
Short name T317
Test name
Test status
Simulation time 202008773 ps
CPU time 2.25 seconds
Started Aug 06 07:16:34 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 199860 kb
Host smart-c5f9c193-51f4-4510-8ba4-2bcaed6c97a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425690904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3425690904
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4013850447
Short name T498
Test name
Test status
Simulation time 31109527299 ps
CPU time 259.2 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:21:09 PM PDT 24
Peak memory 216252 kb
Host smart-ebc50569-5ebd-4183-bd37-dafde9fb82e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013850447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4013850447
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3697758326
Short name T254
Test name
Test status
Simulation time 21261490505 ps
CPU time 64.54 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:17:55 PM PDT 24
Peak memory 199844 kb
Host smart-963cf0e6-4e55-496a-a833-0b0ac5f489fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697758326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3697758326
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3228137392
Short name T270
Test name
Test status
Simulation time 161095598 ps
CPU time 0.58 seconds
Started Aug 06 07:14:39 PM PDT 24
Finished Aug 06 07:14:40 PM PDT 24
Peak memory 195568 kb
Host smart-69fc9224-84a7-412f-aeee-42b8a2e6dfd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228137392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3228137392
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.330977955
Short name T165
Test name
Test status
Simulation time 42490877 ps
CPU time 2.51 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:14:36 PM PDT 24
Peak memory 199756 kb
Host smart-59573d75-9077-4819-8738-894a5fb1a70b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330977955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.330977955
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3261432328
Short name T222
Test name
Test status
Simulation time 4299847487 ps
CPU time 21.23 seconds
Started Aug 06 07:14:37 PM PDT 24
Finished Aug 06 07:14:58 PM PDT 24
Peak memory 199868 kb
Host smart-4088a26a-1eeb-4385-9f9b-983e44efdb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261432328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3261432328
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4196643806
Short name T417
Test name
Test status
Simulation time 3240824831 ps
CPU time 139.78 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:16:50 PM PDT 24
Peak memory 597368 kb
Host smart-8cc90d3e-7c2c-483d-bf12-39057382ede8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196643806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4196643806
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.714849154
Short name T139
Test name
Test status
Simulation time 4334353671 ps
CPU time 49.32 seconds
Started Aug 06 07:14:39 PM PDT 24
Finished Aug 06 07:15:28 PM PDT 24
Peak memory 199848 kb
Host smart-f5ee555d-0066-49ee-9c38-4b475e1f4eee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714849154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.714849154
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3145004293
Short name T364
Test name
Test status
Simulation time 7319647573 ps
CPU time 99.1 seconds
Started Aug 06 07:14:32 PM PDT 24
Finished Aug 06 07:16:12 PM PDT 24
Peak memory 199892 kb
Host smart-f78441f3-d48b-46df-abf7-59e6dc23ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145004293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3145004293
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1078468606
Short name T512
Test name
Test status
Simulation time 4660190262 ps
CPU time 13.24 seconds
Started Aug 06 07:14:32 PM PDT 24
Finished Aug 06 07:14:46 PM PDT 24
Peak memory 199696 kb
Host smart-5a58e9fd-660c-4c1a-93d6-d26b4af93ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078468606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1078468606
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1197119313
Short name T67
Test name
Test status
Simulation time 56977504 ps
CPU time 0.61 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:14:34 PM PDT 24
Peak memory 195580 kb
Host smart-45b52b61-c07a-4801-bfec-80dbae7daa19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197119313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1197119313
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.521856497
Short name T225
Test name
Test status
Simulation time 5638023658 ps
CPU time 42.67 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:15:13 PM PDT 24
Peak memory 199788 kb
Host smart-f8a6c256-da85-4295-993c-152f87fb0d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521856497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.521856497
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2522233237
Short name T469
Test name
Test status
Simulation time 25311858 ps
CPU time 0.56 seconds
Started Aug 06 07:14:38 PM PDT 24
Finished Aug 06 07:14:38 PM PDT 24
Peak memory 195840 kb
Host smart-7d411fce-0885-4df8-b773-17549d57e878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522233237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2522233237
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2494538903
Short name T145
Test name
Test status
Simulation time 6320047316 ps
CPU time 91.59 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:16:03 PM PDT 24
Peak memory 199864 kb
Host smart-a980c527-47ad-47e3-970a-a26e339e80fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494538903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2494538903
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3716718660
Short name T314
Test name
Test status
Simulation time 314118426 ps
CPU time 17.06 seconds
Started Aug 06 07:14:38 PM PDT 24
Finished Aug 06 07:14:56 PM PDT 24
Peak memory 199776 kb
Host smart-1df79c99-21fc-41b4-9cdc-ee8101e8cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716718660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3716718660
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3302323068
Short name T155
Test name
Test status
Simulation time 2319213105 ps
CPU time 289.22 seconds
Started Aug 06 07:14:31 PM PDT 24
Finished Aug 06 07:19:20 PM PDT 24
Peak memory 583156 kb
Host smart-8b6a4c78-828f-42f5-ba77-e4d44a7747b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302323068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3302323068
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.46608476
Short name T231
Test name
Test status
Simulation time 6875139071 ps
CPU time 46.4 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:15:16 PM PDT 24
Peak memory 199772 kb
Host smart-e267b7fa-8db1-48db-bc76-aa445d072184
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46608476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.46608476
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.549075761
Short name T69
Test name
Test status
Simulation time 6405344292 ps
CPU time 117.56 seconds
Started Aug 06 07:14:30 PM PDT 24
Finished Aug 06 07:16:28 PM PDT 24
Peak memory 199904 kb
Host smart-ba251a6b-9934-4e42-9360-6b2c1d38c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549075761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.549075761
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.893944809
Short name T252
Test name
Test status
Simulation time 348325795 ps
CPU time 15.44 seconds
Started Aug 06 07:14:32 PM PDT 24
Finished Aug 06 07:14:47 PM PDT 24
Peak memory 199812 kb
Host smart-b8baf7ba-134e-4f2c-b3b9-7bc25396c62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893944809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.893944809
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2870045088
Short name T432
Test name
Test status
Simulation time 48961372417 ps
CPU time 124.05 seconds
Started Aug 06 07:14:39 PM PDT 24
Finished Aug 06 07:16:43 PM PDT 24
Peak memory 199800 kb
Host smart-745dd257-0904-4a48-ab06-40c3da04385f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870045088 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2870045088
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1272285382
Short name T7
Test name
Test status
Simulation time 22481978133 ps
CPU time 390.24 seconds
Started Aug 06 07:14:34 PM PDT 24
Finished Aug 06 07:21:04 PM PDT 24
Peak memory 241844 kb
Host smart-949d6111-10a4-4578-9f47-4502019bef68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272285382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1272285382
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.334583301
Short name T323
Test name
Test status
Simulation time 967403264 ps
CPU time 37.02 seconds
Started Aug 06 07:14:29 PM PDT 24
Finished Aug 06 07:15:06 PM PDT 24
Peak memory 199860 kb
Host smart-2b08b5be-3a1a-40c6-8db2-c0f6aa44094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334583301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.334583301
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3764238471
Short name T483
Test name
Test status
Simulation time 18667492 ps
CPU time 0.57 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:14:52 PM PDT 24
Peak memory 195516 kb
Host smart-ab6ecefb-b474-4689-947c-878534a2b006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764238471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3764238471
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2005831752
Short name T509
Test name
Test status
Simulation time 969750722 ps
CPU time 55.98 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:15:47 PM PDT 24
Peak memory 199840 kb
Host smart-a177f386-d4f7-45ff-8fc1-948fc7a1c181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005831752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2005831752
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2321493532
Short name T271
Test name
Test status
Simulation time 2902609587 ps
CPU time 9.85 seconds
Started Aug 06 07:14:49 PM PDT 24
Finished Aug 06 07:14:59 PM PDT 24
Peak memory 199912 kb
Host smart-88b4b5cc-073f-469c-b409-beb386c838b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321493532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2321493532
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2332185274
Short name T424
Test name
Test status
Simulation time 4649519491 ps
CPU time 999.82 seconds
Started Aug 06 07:14:49 PM PDT 24
Finished Aug 06 07:31:29 PM PDT 24
Peak memory 739684 kb
Host smart-a6adb295-9f14-44e4-90fb-da9146d72ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332185274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2332185274
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2069469228
Short name T430
Test name
Test status
Simulation time 1686637085 ps
CPU time 46.6 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 07:15:39 PM PDT 24
Peak memory 199828 kb
Host smart-69c3b404-d539-4ed0-aefe-945933fa312e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069469228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2069469228
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1806947568
Short name T133
Test name
Test status
Simulation time 18931278838 ps
CPU time 106.08 seconds
Started Aug 06 07:14:48 PM PDT 24
Finished Aug 06 07:16:35 PM PDT 24
Peak memory 199912 kb
Host smart-7c812e92-6f7d-47a1-bd7a-ea314cda69be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806947568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1806947568
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4063516873
Short name T202
Test name
Test status
Simulation time 1103802221 ps
CPU time 9.71 seconds
Started Aug 06 07:14:40 PM PDT 24
Finished Aug 06 07:14:50 PM PDT 24
Peak memory 199840 kb
Host smart-12c37f6d-1093-4603-ab0c-0a724a4cebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063516873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4063516873
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3190714986
Short name T186
Test name
Test status
Simulation time 87759313449 ps
CPU time 516.65 seconds
Started Aug 06 07:14:55 PM PDT 24
Finished Aug 06 07:23:32 PM PDT 24
Peak memory 661396 kb
Host smart-e3542045-edd5-44eb-80d8-cd3c849da78f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190714986 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3190714986
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2332920790
Short name T450
Test name
Test status
Simulation time 9727744688 ps
CPU time 100.02 seconds
Started Aug 06 07:14:47 PM PDT 24
Finished Aug 06 07:16:27 PM PDT 24
Peak memory 199908 kb
Host smart-e98eb455-a5e2-442c-b42c-2852cf6710ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332920790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2332920790
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3308156611
Short name T233
Test name
Test status
Simulation time 49903289 ps
CPU time 0.59 seconds
Started Aug 06 07:14:55 PM PDT 24
Finished Aug 06 07:14:55 PM PDT 24
Peak memory 195916 kb
Host smart-de3ad56b-d51a-467f-8fd5-b865f9f3154a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308156611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3308156611
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4237973270
Short name T278
Test name
Test status
Simulation time 422390238 ps
CPU time 5.35 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:14:56 PM PDT 24
Peak memory 199796 kb
Host smart-ef00a66d-b035-41a4-8dfa-8368b7ebdb53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237973270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4237973270
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1980124733
Short name T377
Test name
Test status
Simulation time 651953777 ps
CPU time 9.42 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:14:59 PM PDT 24
Peak memory 199648 kb
Host smart-49f2597e-1814-415b-a447-66f3c6bc9cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980124733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1980124733
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3506894937
Short name T409
Test name
Test status
Simulation time 302731557 ps
CPU time 5.32 seconds
Started Aug 06 07:14:54 PM PDT 24
Finished Aug 06 07:14:59 PM PDT 24
Peak memory 216244 kb
Host smart-1789d25c-39f7-450b-a2df-17525efa5178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506894937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3506894937
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1814579977
Short name T288
Test name
Test status
Simulation time 13712086074 ps
CPU time 106.56 seconds
Started Aug 06 07:14:49 PM PDT 24
Finished Aug 06 07:16:36 PM PDT 24
Peak memory 199956 kb
Host smart-802f4260-3949-4f02-b43f-f9db471d97be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814579977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1814579977
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1271423531
Short name T180
Test name
Test status
Simulation time 42009286 ps
CPU time 0.96 seconds
Started Aug 06 07:14:53 PM PDT 24
Finished Aug 06 07:14:54 PM PDT 24
Peak memory 199132 kb
Host smart-94643ce2-4944-40eb-b1eb-149aeda47e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271423531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1271423531
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1012726613
Short name T371
Test name
Test status
Simulation time 1333656240 ps
CPU time 15.02 seconds
Started Aug 06 07:14:49 PM PDT 24
Finished Aug 06 07:15:04 PM PDT 24
Peak memory 199740 kb
Host smart-27d46738-a663-4d2c-b774-3fa024c6ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012726613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1012726613
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2615536759
Short name T465
Test name
Test status
Simulation time 547944083687 ps
CPU time 1947.67 seconds
Started Aug 06 07:14:51 PM PDT 24
Finished Aug 06 07:47:19 PM PDT 24
Peak memory 730400 kb
Host smart-1cb0b8cd-6654-4f4c-9962-fb74a0f2505a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615536759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2615536759
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1009931249
Short name T20
Test name
Test status
Simulation time 94683103717 ps
CPU time 3305.62 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 08:09:58 PM PDT 24
Peak memory 783692 kb
Host smart-65b5cc56-1e5e-4a3f-9cd5-3811e02aac5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009931249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1009931249
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.368218345
Short name T446
Test name
Test status
Simulation time 3767447751 ps
CPU time 49.31 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:15:39 PM PDT 24
Peak memory 199868 kb
Host smart-ee7a8b74-f7ea-4dba-b345-543a4f4f9598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368218345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.368218345
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2610450557
Short name T435
Test name
Test status
Simulation time 11460850 ps
CPU time 0.57 seconds
Started Aug 06 07:14:53 PM PDT 24
Finished Aug 06 07:14:53 PM PDT 24
Peak memory 194752 kb
Host smart-e1be3730-a882-4525-97f1-be6636229629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610450557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2610450557
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3522978098
Short name T239
Test name
Test status
Simulation time 5350451743 ps
CPU time 75.84 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 07:16:08 PM PDT 24
Peak memory 199860 kb
Host smart-2fcf9831-5309-477c-b21e-41ceae5cafa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522978098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3522978098
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1250427460
Short name T319
Test name
Test status
Simulation time 4418954333 ps
CPU time 59.26 seconds
Started Aug 06 07:14:49 PM PDT 24
Finished Aug 06 07:15:49 PM PDT 24
Peak memory 199788 kb
Host smart-cb98d9c1-d9b9-43da-97d4-fc53468a9c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250427460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1250427460
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2123048530
Short name T365
Test name
Test status
Simulation time 19621580779 ps
CPU time 999.99 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:31:31 PM PDT 24
Peak memory 680552 kb
Host smart-ba0b65f9-e594-432b-9fcc-64cecad668d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123048530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2123048530
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3307063960
Short name T218
Test name
Test status
Simulation time 5277574032 ps
CPU time 87.93 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:16:18 PM PDT 24
Peak memory 199884 kb
Host smart-5d9c8d5a-e2c8-43e5-b62c-b1e7638c24cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307063960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3307063960
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1838901317
Short name T451
Test name
Test status
Simulation time 9104098099 ps
CPU time 166.13 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 07:17:38 PM PDT 24
Peak memory 208184 kb
Host smart-cce23be4-989c-43b4-8d43-ac63232459fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838901317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1838901317
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2263141568
Short name T363
Test name
Test status
Simulation time 175564600 ps
CPU time 7.63 seconds
Started Aug 06 07:14:53 PM PDT 24
Finished Aug 06 07:15:00 PM PDT 24
Peak memory 199612 kb
Host smart-e10ec6e1-5a42-4df9-97fe-370888198eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263141568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2263141568
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3186215226
Short name T263
Test name
Test status
Simulation time 94501361485 ps
CPU time 1340.34 seconds
Started Aug 06 07:14:55 PM PDT 24
Finished Aug 06 07:37:16 PM PDT 24
Peak memory 760132 kb
Host smart-01d15083-fbbe-45b2-b879-d4bf545c3256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186215226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3186215226
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.461253691
Short name T13
Test name
Test status
Simulation time 72149320241 ps
CPU time 2235.33 seconds
Started Aug 06 07:14:50 PM PDT 24
Finished Aug 06 07:52:05 PM PDT 24
Peak memory 741884 kb
Host smart-32c93807-b854-401f-907e-807adefc4bcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461253691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.461253691
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.402660760
Short name T296
Test name
Test status
Simulation time 1888021174 ps
CPU time 3.04 seconds
Started Aug 06 07:14:52 PM PDT 24
Finished Aug 06 07:14:55 PM PDT 24
Peak memory 199832 kb
Host smart-c0c67e7a-d43e-4238-830e-85a0549c520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402660760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.402660760
Directory /workspace/9.hmac_wipe_secret/latest
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