Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	21018571	1			T1	15023		T2	44071		T3	8380
all_values[1]	21018571	1			T1	15023		T2	44071		T3	8380
all_values[2]	21018571	1			T1	15023		T2	44071		T3	8380

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

273557

1

T4

972

T7

1017

T26

654

auto[1]

62782156

1

T1

45069

T2

132213

T3

25140

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53611904

1

T1

35235

T2

119678

T3

24960

auto[1]

9443809

1

T1

9834

T2

12535

T3

180

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84027	1			T7	1		T26	652		T52	1497
all_values[0]	auto[0]	auto[1]	322	1			T7	6		T26	2		T52	5
all_values[0]	auto[1]	auto[0]	20911902	1			T1	15017		T2	44049		T3	8200
all_values[0]	auto[1]	auto[1]	22320	1			T1	6		T2	22		T3	180
all_values[1]	auto[0]	auto[0]	88032	1			T4	486		T7	985		T52	46
all_values[1]	auto[0]	auto[1]	219	1			T7	3		T52	2		T61	6
all_values[1]	auto[1]	auto[0]	20929960	1			T1	15023		T2	44071		T3	8380
all_values[1]	auto[1]	auto[1]	360	1			T7	3		T52	1		T61	5
all_values[2]	auto[0]	auto[0]	49421	1			T4	112		T7	20		T27	725
all_values[2]	auto[0]	auto[1]	51536	1			T4	374		T7	2		T52	3
all_values[2]	auto[1]	auto[0]	11548562	1			T1	5195		T2	31558		T3	8380
all_values[2]	auto[1]	auto[1]	9369052	1			T1	9828		T2	12513		T15	10123