Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164234

1

T1

12

T4

22

T6

4

auto[1]

164948

1

T1

14

T2

44

T3

186

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	121986	1			T1	10		T2	11		T4	17
len_1026_2046	7279	1			T5	1		T7	29		T21	1
len_514_1022	5137	1			T4	4		T5	5		T7	19
len_2_510	4920	1			T7	14		T57	61		T27	3
len_2056	186	1			T7	4		T52	5		T121	2
len_2048	428	1			T7	4		T21	1		T18	1
len_2040	200	1			T7	2		T52	1		T61	3
len_1032	1065	1			T7	5		T121	2		T8	2
len_1024	1874	1			T3	93		T15	109		T4	1
len_1016	227	1			T7	6		T52	3		T61	6
len_520	290	1			T7	11		T57	1		T52	4
len_512	441	1			T4	1		T5	1		T7	2
len_504	236	1			T7	7		T57	1		T52	14
len_8	1370	1			T2	11		T7	10		T17	3
len_0	18954	1			T1	3		T4	8		T5	4

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

117

1

T4

1

T18

2

T19

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	61229	1			T1	6		T4	5		T6	2
auto[0]	len_1026_2046	2895	1			T7	5		T21	1		T18	2
auto[0]	len_514_1022	2690	1			T4	1		T5	2		T7	2
auto[0]	len_2_510	3100	1			T7	3		T57	61		T27	2
auto[0]	len_2056	105	1			T7	3		T52	3		T8	9
auto[0]	len_2048	220	1			T7	2		T21	1		T18	1
auto[0]	len_2040	111	1			T7	1		T61	3		T8	9
auto[0]	len_1032	976	1			T7	1		T8	1		T35	2
auto[0]	len_1024	304	1			T4	1		T7	4		T52	6
auto[0]	len_1016	129	1			T61	2		T68	1		T121	2
auto[0]	len_520	178	1			T7	5		T57	1		T52	2
auto[0]	len_512	266	1			T4	1		T5	1		T57	2
auto[0]	len_504	140	1			T7	5		T57	1		T52	9
auto[0]	len_8	51	1			T57	2		T68	1		T82	1
auto[0]	len_0	9725	1			T4	3		T5	4		T7	13
auto[1]	len_2050_plus	60757	1			T1	4		T2	11		T4	12
auto[1]	len_1026_2046	4384	1			T5	1		T7	24		T52	98
auto[1]	len_514_1022	2447	1			T4	3		T5	3		T7	17
auto[1]	len_2_510	1820	1			T7	11		T27	1		T52	64
auto[1]	len_2056	81	1			T7	1		T52	2		T121	2
auto[1]	len_2048	208	1			T7	2		T52	3		T23	1
auto[1]	len_2040	89	1			T7	1		T52	1		T8	4
auto[1]	len_1032	89	1			T7	4		T121	2		T8	1
auto[1]	len_1024	1570	1			T3	93		T15	109		T7	5
auto[1]	len_1016	98	1			T7	6		T52	3		T61	4
auto[1]	len_520	112	1			T7	6		T52	2		T61	2
auto[1]	len_512	175	1			T7	2		T52	8		T72	1
auto[1]	len_504	96	1			T7	2		T52	5		T121	1
auto[1]	len_8	1319	1			T2	11		T7	10		T17	3
auto[1]	len_0	9229	1			T1	3		T4	5		T7	23

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

63

1

T4

1

T18

2

T19

2

auto[1]

len_upper

54

1

T20

1

T82

3

T134

2