Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5265868 1 T1 5641 T2 10327 T3 4198
auto[1] 3534724 1 T1 1876 T2 11538 T4 8564


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3465997 1 T1 2032 T2 7173 T4 10158
auto[1] 5334595 1 T1 5485 T2 14692 T3 4198


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3650999 1 T1 4463 T4 7947 T6 1117
auto[1] 5149593 1 T1 3054 T2 21865 T3 4198


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5260339 1 T1 2194 T2 13655 T3 4198
auto[1] 3540253 1 T1 5323 T2 8210 T4 5093


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7945491 1 T1 7308 T2 18181 T3 3928
fifo_depth[1] 134263 1 T1 29 T2 646 T3 135
fifo_depth[2] 101896 1 T1 34 T2 620 T3 89
fifo_depth[3] 81295 1 T1 29 T2 573 T3 38
fifo_depth[4] 75471 1 T1 31 T2 561 T3 7
fifo_depth[5] 60002 1 T1 32 T2 456 T3 1
fifo_depth[6] 48850 1 T1 24 T2 336 T15 39
fifo_depth[7] 32662 1 T1 15 T2 257 T15 9


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 855101 1 T1 209 T2 3684 T3 270
auto[1] 7945491 1 T1 7308 T2 18181 T3 3928


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8785207 1 T1 7517 T2 21865 T3 4198
auto[1] 15385 1 T23 151 T24 20 T121 673


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 39140 1 T4 495 T5 20 T7 11
auto[0] auto[0] auto[0] auto[0] auto[1] 41110 1 T5 75 T7 158 T21 1
auto[0] auto[0] auto[0] auto[1] auto[0] 44379 1 T1 95 T4 136 T5 20
auto[0] auto[0] auto[0] auto[1] auto[1] 46559 1 T4 275 T7 131 T49 15
auto[0] auto[0] auto[1] auto[0] auto[0] 121844 1 T6 18 T5 25 T7 12
auto[0] auto[0] auto[1] auto[0] auto[1] 33913 1 T1 48 T5 12 T7 135
auto[0] auto[0] auto[1] auto[1] auto[0] 34930 1 T4 380 T7 5 T26 15
auto[0] auto[0] auto[1] auto[1] auto[1] 47430 1 T4 5 T6 28 T5 21
auto[0] auto[1] auto[0] auto[0] auto[0] 58022 1 T2 668 T4 631 T5 11
auto[0] auto[1] auto[0] auto[0] auto[1] 50838 1 T2 90 T7 364 T26 19
auto[0] auto[1] auto[0] auto[1] auto[0] 51644 1 T2 261 T7 14 T18 2
auto[0] auto[1] auto[0] auto[1] auto[1] 58288 1 T2 298 T4 55 T6 13
auto[0] auto[1] auto[1] auto[0] auto[0] 56459 1 T2 600 T3 270 T15 813
auto[0] auto[1] auto[1] auto[0] auto[1] 63471 1 T1 66 T4 84 T5 1
auto[0] auto[1] auto[1] auto[1] auto[0] 54691 1 T2 612 T5 13 T7 689
auto[0] auto[1] auto[1] auto[1] auto[1] 52383 1 T2 1155 T4 231 T7 1245
auto[1] auto[0] auto[0] auto[0] auto[0] 209872 1 T4 2299 T5 667 T7 102
auto[1] auto[0] auto[0] auto[0] auto[1] 215404 1 T4 22 T5 1949 T7 587
auto[1] auto[0] auto[0] auto[1] auto[0] 208801 1 T1 352 T4 1811 T5 652
auto[1] auto[0] auto[0] auto[1] auto[1] 214195 1 T4 872 T5 242 T7 1808
auto[1] auto[0] auto[1] auto[0] auto[0] 1800239 1 T1 515 T4 308 T6 447
auto[1] auto[0] auto[1] auto[0] auto[1] 200215 1 T1 2025 T4 11 T5 474
auto[1] auto[0] auto[1] auto[1] auto[0] 204934 1 T4 1305 T7 901 T26 308
auto[1] auto[0] auto[1] auto[1] auto[1] 188034 1 T1 1428 T4 28 T6 624
auto[1] auto[1] auto[0] auto[0] auto[0] 556325 1 T2 4063 T4 2341 T5 299
auto[1] auto[1] auto[0] auto[0] auto[1] 532239 1 T1 1584 T2 286 T4 477
auto[1] auto[1] auto[0] auto[1] auto[0] 578532 1 T2 483 T4 589 T5 1943
auto[1] auto[1] auto[0] auto[1] auto[1] 560649 1 T1 1 T2 1024 T4 155
auto[1] auto[1] auto[1] auto[0] auto[0] 686988 1 T1 1232 T2 2154 T3 3928
auto[1] auto[1] auto[1] auto[0] auto[1] 599789 1 T1 171 T2 2466 T4 1042
auto[1] auto[1] auto[1] auto[1] auto[0] 553539 1 T2 4814 T4 886 T6 437
auto[1] auto[1] auto[1] auto[1] auto[1] 635736 1 T2 2891 T4 1836 T5 472


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 248324 1 T4 2794 T5 687 T7 113
auto[0] auto[0] auto[0] auto[0] auto[1] 254467 1 T4 22 T5 2024 T7 745
auto[0] auto[0] auto[0] auto[1] auto[0] 252821 1 T1 447 T4 1947 T5 672
auto[0] auto[0] auto[0] auto[1] auto[1] 258734 1 T4 1147 T5 242 T7 1939
auto[0] auto[0] auto[1] auto[0] auto[0] 1921350 1 T1 515 T4 308 T6 465
auto[0] auto[0] auto[1] auto[0] auto[1] 233358 1 T1 2073 T4 11 T5 486
auto[0] auto[0] auto[1] auto[1] auto[0] 239359 1 T4 1685 T7 906 T26 323
auto[0] auto[0] auto[1] auto[1] auto[1] 233790 1 T1 1428 T4 33 T6 652
auto[0] auto[1] auto[0] auto[0] auto[0] 613592 1 T2 4731 T4 2972 T5 310
auto[0] auto[1] auto[0] auto[0] auto[1] 582896 1 T1 1584 T2 376 T4 477
auto[0] auto[1] auto[0] auto[1] auto[0] 629576 1 T2 744 T4 589 T5 1943
auto[0] auto[1] auto[0] auto[1] auto[1] 618458 1 T1 1 T2 1322 T4 210
auto[0] auto[1] auto[1] auto[0] auto[0] 742756 1 T1 1232 T2 2754 T3 4198
auto[0] auto[1] auto[1] auto[0] auto[1] 661107 1 T1 237 T2 2466 T4 1126
auto[0] auto[1] auto[1] auto[1] auto[0] 607457 1 T2 5426 T4 886 T6 437
auto[0] auto[1] auto[1] auto[1] auto[1] 687162 1 T2 4046 T4 2067 T5 472
auto[1] auto[0] auto[0] auto[0] auto[0] 688 1 T37 85 T136 20 T137 24
auto[1] auto[0] auto[0] auto[0] auto[1] 2047 1 T23 9 T35 77 T37 11
auto[1] auto[0] auto[0] auto[1] auto[0] 359 1 T23 9 T121 47 T37 5
auto[1] auto[0] auto[0] auto[1] auto[1] 2020 1 T35 62 T37 7 T136 40
auto[1] auto[0] auto[1] auto[0] auto[0] 733 1 T23 50 T24 5 T76 29
auto[1] auto[0] auto[1] auto[0] auto[1] 770 1 T37 11 T136 109 T50 100
auto[1] auto[0] auto[1] auto[1] auto[0] 505 1 T23 4 T121 10 T35 102
auto[1] auto[0] auto[1] auto[1] auto[1] 1674 1 T24 7 T121 458 T35 35
auto[1] auto[1] auto[0] auto[0] auto[0] 755 1 T23 61 T121 22 T35 9
auto[1] auto[1] auto[0] auto[0] auto[1] 181 1 T23 5 T35 41 T37 66
auto[1] auto[1] auto[0] auto[1] auto[0] 600 1 T24 8 T138 176 T139 13
auto[1] auto[1] auto[0] auto[1] auto[1] 479 1 T121 101 T35 38 T136 28
auto[1] auto[1] auto[1] auto[0] auto[0] 691 1 T121 4 T50 80 T140 10
auto[1] auto[1] auto[1] auto[0] auto[1] 2153 1 T23 9 T121 1 T35 428
auto[1] auto[1] auto[1] auto[1] auto[0] 773 1 T23 4 T50 218 T141 14
auto[1] auto[1] auto[1] auto[1] auto[1] 957 1 T121 30 T35 1 T37 4


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 209872 1 T4 2299 T5 667 T7 102
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 215404 1 T4 22 T5 1949 T7 587
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 208801 1 T1 352 T4 1811 T5 652
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 214195 1 T4 872 T5 242 T7 1808
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1800239 1 T1 515 T4 308 T6 447
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 200215 1 T1 2025 T4 11 T5 474
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 204934 1 T4 1305 T7 901 T26 308
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 188034 1 T1 1428 T4 28 T6 624
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 556325 1 T2 4063 T4 2341 T5 299
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 532239 1 T1 1584 T2 286 T4 477
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 578532 1 T2 483 T4 589 T5 1943
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 560649 1 T1 1 T2 1024 T4 155
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 686988 1 T1 1232 T2 2154 T3 3928
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 599789 1 T1 171 T2 2466 T4 1042
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 553539 1 T2 4814 T4 886 T6 437
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 635736 1 T2 2891 T4 1836 T5 472
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4318 1 T4 93 T5 15 T7 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4483 1 T5 57 T7 24 T26 2
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4121 1 T1 11 T4 24 T5 12
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4795 1 T4 61 T7 19 T49 11
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 38877 1 T6 15 T5 18 T7 3
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4778 1 T1 8 T5 8 T7 24
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3776 1 T4 52 T7 2 T26 10
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4102 1 T4 1 T6 21 T5 14
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 7013 1 T2 110 T4 126 T5 6
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7487 1 T2 12 T7 56 T26 10
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 7890 1 T2 54 T7 2 T27 19
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 7796 1 T2 46 T4 8 T6 11
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 10378 1 T2 116 T3 135 T15 172
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 8732 1 T1 10 T4 10 T7 66
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7360 1 T2 89 T5 12 T7 121
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 8357 1 T2 219 T4 39 T7 93
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3470 1 T4 90 T5 5 T26 3
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3581 1 T5 16 T7 19 T21 1
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3555 1 T1 16 T4 27 T5 5
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 4075 1 T4 44 T7 27 T49 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 22472 1 T6 3 T5 6 T7 2
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3716 1 T1 5 T5 3 T7 27
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3026 1 T4 60 T26 4 T27 60
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3570 1 T4 2 T6 6 T5 4
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6085 1 T2 97 T4 102 T5 3
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 6536 1 T2 11 T7 53 T26 9
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 6649 1 T2 61 T7 2 T27 19
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 6433 1 T2 42 T4 6 T6 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 8317 1 T2 113 T3 89 T15 172
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 7540 1 T1 13 T4 12 T5 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5871 1 T2 94 T5 1 T7 113
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 7000 1 T2 202 T4 42 T7 103
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2743 1 T4 95 T7 3 T21 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2691 1 T5 2 T7 28 T27 14
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2978 1 T1 13 T4 28 T5 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 3321 1 T4 47 T7 21 T119 28
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 14542 1 T7 2 T57 313 T119 64
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 3079 1 T1 8 T5 1 T7 30
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2279 1 T4 59 T26 1 T27 67
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2745 1 T4 1 T6 1 T5 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5278 1 T2 94 T4 106 T5 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 5473 1 T2 17 T7 50 T54 45
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 5691 1 T2 39 T7 2 T27 15
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5662 1 T2 35 T4 10 T5 3
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 7189 1 T2 107 T3 38 T15 168
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 6680 1 T1 8 T4 6 T7 68
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4911 1 T2 94 T7 120 T26 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 6033 1 T2 187 T4 48 T7 102
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2809 1 T4 69 T7 2 T52 10
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2708 1 T7 21 T27 18 T52 15
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 3067 1 T1 18 T4 17 T7 42
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 3461 1 T4 38 T7 16 T119 19
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 9791 1 T5 1 T7 2 T57 57
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2870 1 T1 7 T7 22 T18 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2412 1 T4 51 T7 1 T27 70
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2861 1 T5 2 T119 23 T52 4
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 5205 1 T2 80 T4 104 T5 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 5499 1 T2 11 T7 50 T54 43
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 5379 1 T2 45 T7 3 T27 14
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 5400 1 T2 54 T4 8 T7 3
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 6585 1 T2 103 T3 7 T15 145
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 6399 1 T1 6 T4 10 T7 63
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5183 1 T2 94 T7 119 T54 25
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5842 1 T2 174 T4 38 T7 159
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2096 1 T4 72 T7 1 T21 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2024 1 T7 28 T27 12 T61 4
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2500 1 T1 16 T4 22 T7 59
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2598 1 T4 39 T7 14 T119 18
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 6583 1 T7 2 T57 16 T119 41
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2351 1 T1 5 T7 15 T52 6
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1803 1 T4 56 T7 2 T27 54
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2223 1 T4 1 T7 2 T119 15
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4238 1 T2 86 T4 84 T7 83
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4401 1 T2 8 T7 39 T54 41
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4610 1 T2 34 T7 1 T27 17
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4487 1 T2 27 T4 6 T7 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 5657 1 T2 80 T3 1 T15 106
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 5572 1 T1 11 T4 15 T7 51
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3985 1 T2 77 T7 103 T54 24
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4874 1 T2 144 T4 28 T7 75
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1646 1 T4 35 T7 2 T52 5
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 2077 1 T7 11 T27 9 T52 16
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 2060 1 T1 10 T4 14 T7 24
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 2329 1 T4 30 T7 22 T119 13
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 4638 1 T7 1 T57 3 T119 39
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1808 1 T1 6 T7 11 T52 5
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1590 1 T4 43 T27 36 T23 4
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1838 1 T119 6 T52 5 T23 74
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3374 1 T2 80 T4 73 T7 48
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3698 1 T2 9 T7 45 T54 25
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3449 1 T2 13 T7 2 T27 7
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3864 1 T2 33 T4 3 T54 44
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 4503 1 T2 42 T15 39 T4 15
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 4473 1 T1 8 T4 12 T7 37
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3448 1 T2 68 T7 54 T21 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 4055 1 T2 91 T4 23 T7 128
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1091 1 T4 20 T7 1 T133 10
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1349 1 T7 12 T27 5 T52 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1695 1 T1 5 T4 4 T7 11
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1276 1 T4 12 T7 6 T119 3
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 2839 1 T119 32 T52 3 T24 5
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1267 1 T1 6 T7 4 T52 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1068 1 T4 33 T27 15 T52 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1201 1 T7 1 T18 1 T119 11
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2310 1 T2 66 T4 22 T7 37
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2391 1 T2 9 T7 32 T54 16
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2357 1 T2 10 T27 3 T119 12
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2819 1 T2 34 T4 8 T7 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 3127 1 T2 20 T15 9 T4 7
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 3036 1 T1 4 T4 11 T7 15
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2187 1 T2 50 T7 30 T54 14
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2649 1 T2 68 T4 8 T7 45

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