Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	21018571	1			T1	15023		T2	44071		T3	8380
all_pins[1]	21018571	1			T1	15023		T2	44071		T3	8380
all_pins[2]	21018571	1			T1	15023		T2	44071		T3	8380

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	53662994	1			T1	35233		T2	119677		T3	24960
values[0x1]	9392719	1			T1	9836		T2	12536		T3	180
transitions[0x0=>0x1]	9392492	1			T1	9836		T2	12536		T3	180
transitions[0x1=>0x0]	9392510	1			T1	9836		T2	12536		T3	180

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	20995299	1			T1	15015		T2	44048		T3	8200
all_pins[0]	values[0x1]	23272	1			T1	8		T2	23		T3	180
all_pins[0]	transitions[0x0=>0x1]	23170	1			T1	8		T2	23		T3	180
all_pins[0]	transitions[0x1=>0x0]	9368968	1			T1	9828		T2	12513		T15	10123
all_pins[1]	values[0x0]	21018176	1			T1	15023		T2	44071		T3	8380
all_pins[1]	values[0x1]	395	1			T7	3		T52	1		T61	5
all_pins[1]	transitions[0x0=>0x1]	332	1			T7	3		T61	5		T23	4
all_pins[1]	transitions[0x1=>0x0]	23209	1			T1	8		T2	23		T3	180
all_pins[2]	values[0x0]	11649519	1			T1	5195		T2	31558		T3	8380
all_pins[2]	values[0x1]	9369052	1			T1	9828		T2	12513		T15	10123
all_pins[2]	transitions[0x0=>0x1]	9368990	1			T1	9828		T2	12513		T15	10123
all_pins[2]	transitions[0x1=>0x0]	333	1			T7	3		T52	1		T61	3