Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1057 1 T7 10 T52 4 T61 20
all_values[1] 1057 1 T7 10 T52 4 T61 20
all_values[2] 1057 1 T7 10 T52 4 T61 20


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1532 1 T7 17 T52 6 T61 28
auto[1] 1639 1 T7 13 T52 6 T61 32


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1141 1 T7 7 T52 1 T61 17
auto[1] 2030 1 T7 23 T52 11 T61 43


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1817 1 T7 13 T52 7 T61 32
auto[1] 1354 1 T7 17 T52 5 T61 28


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 213 1 T7 1 T52 1 T61 4
all_values[0] auto[0] auto[0] auto[1] 88 1 T7 3 T61 2 T121 1
all_values[0] auto[0] auto[1] auto[0] 213 1 T61 4 T121 1 T8 1
all_values[0] auto[0] auto[1] auto[1] 119 1 T52 2 T61 1 T121 1
all_values[0] auto[1] auto[0] auto[1] 210 1 T7 3 T52 1 T61 3
all_values[0] auto[1] auto[1] auto[1] 214 1 T7 3 T61 6 T121 1
all_values[1] auto[0] auto[0] auto[0] 169 1 T7 2 T61 1 T121 1
all_values[1] auto[0] auto[0] auto[1] 134 1 T7 2 T61 2 T121 2
all_values[1] auto[0] auto[1] auto[0] 174 1 T61 2 T121 5 T8 4
all_values[1] auto[0] auto[1] auto[1] 130 1 T52 1 T61 4 T121 3
all_values[1] auto[1] auto[0] auto[1] 230 1 T7 2 T52 2 T61 7
all_values[1] auto[1] auto[1] auto[1] 220 1 T7 4 T52 1 T61 4
all_values[2] auto[0] auto[0] auto[0] 169 1 T61 1 T121 2 T8 7
all_values[2] auto[0] auto[0] auto[1] 86 1 T7 1 T52 2 T61 4
all_values[2] auto[0] auto[1] auto[0] 203 1 T7 4 T61 5 T121 5
all_values[2] auto[0] auto[1] auto[1] 119 1 T52 1 T61 2 T121 2
all_values[2] auto[1] auto[0] auto[1] 233 1 T7 3 T61 4 T121 2
all_values[2] auto[1] auto[1] auto[1] 247 1 T7 2 T52 1 T61 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%