Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	5060	1			T1	4		T2	8		T4	8
sha2_none	5187	1			T1	5		T2	6		T4	10
sha2_512	8490	1			T1	3		T2	9		T15	225
sha2_384	8298	1			T1	3		T2	9		T3	180
sha2_256	7278	1			T1	1		T2	5		T4	15

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21199

1

T1

12

T2

12

T3

180

auto[1]

13578

1

T1

4

T2

26

T4

21

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13426

1

T1

6

T2

16

T4

25

auto[1]

21351

1

T1

10

T2

22

T3

180

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

18397

1

T1

7

T2

38

T3

180

disabled

16380

1

T1

9

T4

20

T6

2

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5591	1			T1	3		T2	6		T4	10
key_none	8349	1			T1	1		T2	3		T4	10
key_1024	4949	1			T1	5		T2	5		T3	60
key_512	4442	1			T1	2		T2	5		T3	120
key_384	4026	1			T1	2		T2	8		T4	6
key_256	3719	1			T1	1		T2	4		T4	3
key_128	3623	1			T1	2		T2	7		T4	6

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21252

1

T1

6

T2

27

T3

180

auto[1]

13525

1

T1

10

T2

11

T4

20

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

34566

1

T1

16

T2

38

T3

180

disabled

211

1

T7

1

T55

3

T52

6

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

2028

1

T2

3

T4

5

T5

1

enabled

auto[0]

auto[0]

auto[1]

1833

1

T1

3

T2

2

T4

2

enabled

auto[0]

auto[1]

auto[0]

1834

1

T2

9

T4

3

T5

4

enabled

auto[0]

auto[1]

auto[1]

1884

1

T1

1

T2

2

T4

1

enabled

auto[1]

auto[0]

auto[0]

4687

1

T1

2

T2

4

T3

180

enabled

auto[1]

auto[0]

auto[1]

2025

1

T1

1

T2

3

T4

4

enabled

auto[1]

auto[1]

auto[0]

2102

1

T2

11

T4

2

T6

1

enabled

auto[1]

auto[1]

auto[1]

2004

1

T2

4

T4

5

T5

1

disabled

auto[0]

auto[0]

auto[0]

1472

1

T4

5

T5

5

T7

7

disabled

auto[0]

auto[0]

auto[1]

1449

1

T4

2

T5

4

T7

10

disabled

auto[0]

auto[1]

auto[0]

1444

1

T1

2

T4

3

T5

4

disabled

auto[0]

auto[1]

auto[1]

1482

1

T4

4

T5

2

T7

7

disabled

auto[1]

auto[0]

auto[0]

6267

1

T1

2

T4

2

T6

1

disabled

auto[1]

auto[0]

auto[1]

1438

1

T1

4

T4

1

T5

1

disabled

auto[1]

auto[1]

auto[0]

1418

1

T4

2

T7

9

T26

1

disabled

auto[1]

auto[1]

auto[1]

1410

1

T1

1

T4

1

T6

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

18323

1

T1

7

T2

38

T3

180

enabled

disabled

74

1

T52

3

T61

5

T133

2

disabled

disabled

137

1

T7

1

T55

3

T52

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

16243

1

T1

9

T4

20

T6

2

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1341	1			T1	1		T2	2		T4	2
key_invalid	sha2_none	1041	1			T1	1		T4	1		T5	3
key_invalid	sha2_512	1058	1			T2	2		T6	1		T5	1
key_invalid	sha2_384	995	1			T1	1		T2	2		T5	1
key_invalid	sha2_256	1028	1			T4	7		T5	2		T7	6
key_none	sha2_invalid	556	1			T2	1		T4	2		T6	1
key_none	sha2_none	709	1			T2	1		T4	3		T5	2
key_none	sha2_512	2657	1			T4	4		T5	1		T7	7
key_none	sha2_384	2666	1			T2	1		T5	1		T7	3
key_none	sha2_256	1704	1			T1	1		T4	1		T5	2
key_1024	sha2_invalid	635	1			T1	1		T4	1		T7	5
key_1024	sha2_none	666	1			T1	1		T2	1		T4	3
key_1024	sha2_512	1833	1			T1	3		T2	1		T15	225
key_1024	sha2_384	1059	1			T2	3		T3	60		T4	1
key_512	sha2_invalid	621	1			T4	1		T7	13		T21	2
key_512	sha2_none	734	1			T1	2		T4	1		T5	2
key_512	sha2_512	757	1			T2	1		T4	1		T5	1
key_512	sha2_384	1309	1			T2	1		T3	120		T7	4
key_512	sha2_256	969	1			T2	3		T4	4		T5	1
key_384	sha2_invalid	597	1			T1	2		T2	1		T4	1
key_384	sha2_none	671	1			T2	3		T7	4		T17	1
key_384	sha2_512	715	1			T4	1		T5	1		T7	7
key_384	sha2_384	786	1			T2	1		T4	2		T7	5
key_384	sha2_256	1193	1			T2	2		T4	2		T5	3
key_256	sha2_invalid	642	1			T2	1		T4	1		T7	8
key_256	sha2_none	682	1			T2	1		T4	1		T5	2
key_256	sha2_512	715	1			T2	1		T4	1		T7	6
key_256	sha2_384	699	1			T1	1		T2	1		T5	4
key_256	sha2_256	926	1			T5	2		T7	4		T17	1
key_128	sha2_invalid	649	1			T2	3		T7	4		T17	1
key_128	sha2_none	669	1			T1	1		T4	1		T5	1
key_128	sha2_512	746	1			T2	4		T4	4		T7	6
key_128	sha2_384	766	1			T1	1		T5	2		T7	5
key_128	sha2_256	735	1			T4	1		T6	3		T7	4

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

706

1

T7

5

T18

5

T54

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1341	1			T1	1		T2	2		T4	2
key_invalid	sha2_none	1041	1			T1	1		T4	1		T5	3
key_invalid	sha2_512	1058	1			T2	2		T6	1		T5	1
key_invalid	sha2_384	995	1			T1	1		T2	2		T5	1
key_invalid	sha2_256	1028	1			T4	7		T5	2		T7	6
key_none	sha2_invalid	556	1			T2	1		T4	2		T6	1
key_none	sha2_none	709	1			T2	1		T4	3		T5	2
key_none	sha2_512	2657	1			T4	4		T5	1		T7	7
key_none	sha2_384	2666	1			T2	1		T5	1		T7	3
key_none	sha2_256	1704	1			T1	1		T4	1		T5	2
key_1024	sha2_invalid	635	1			T1	1		T4	1		T7	5
key_1024	sha2_none	666	1			T1	1		T2	1		T4	3
key_1024	sha2_512	1833	1			T1	3		T2	1		T15	225
key_1024	sha2_384	1059	1			T2	3		T3	60		T4	1
key_1024	sha2_256	706	1			T7	5		T18	5		T54	2
key_512	sha2_invalid	621	1			T4	1		T7	13		T21	2
key_512	sha2_none	734	1			T1	2		T4	1		T5	2
key_512	sha2_512	757	1			T2	1		T4	1		T5	1
key_512	sha2_384	1309	1			T2	1		T3	120		T7	4
key_512	sha2_256	969	1			T2	3		T4	4		T5	1
key_384	sha2_invalid	597	1			T1	2		T2	1		T4	1
key_384	sha2_none	671	1			T2	3		T7	4		T17	1
key_384	sha2_512	715	1			T4	1		T5	1		T7	7
key_384	sha2_384	786	1			T2	1		T4	2		T7	5
key_384	sha2_256	1193	1			T2	2		T4	2		T5	3
key_256	sha2_invalid	642	1			T2	1		T4	1		T7	8
key_256	sha2_none	682	1			T2	1		T4	1		T5	2
key_256	sha2_512	715	1			T2	1		T4	1		T7	6
key_256	sha2_384	699	1			T1	1		T2	1		T5	4
key_256	sha2_256	926	1			T5	2		T7	4		T17	1
key_128	sha2_invalid	649	1			T2	3		T7	4		T17	1
key_128	sha2_none	669	1			T1	1		T4	1		T5	1
key_128	sha2_512	746	1			T2	4		T4	4		T7	6
key_128	sha2_384	766	1			T1	1		T5	2		T7	5
key_128	sha2_256	735	1			T4	1		T6	3		T7	4