Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 659
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T74 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2398817566 Aug 07 05:45:54 PM PDT 24 Aug 07 05:45:56 PM PDT 24 483680468 ps
T531 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3743503799 Aug 07 05:46:03 PM PDT 24 Aug 07 05:46:03 PM PDT 24 19044572 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3159222131 Aug 07 05:45:32 PM PDT 24 Aug 07 05:45:35 PM PDT 24 628987851 ps
T532 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4155294183 Aug 07 05:46:01 PM PDT 24 Aug 07 05:46:02 PM PDT 24 58440001 ps
T75 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.952746951 Aug 07 05:45:40 PM PDT 24 Aug 07 05:45:44 PM PDT 24 216191651 ps
T533 /workspace/coverage/cover_reg_top/5.hmac_intr_test.70105798 Aug 07 05:45:31 PM PDT 24 Aug 07 05:45:31 PM PDT 24 14799566 ps
T103 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2125993357 Aug 07 05:45:48 PM PDT 24 Aug 07 05:45:49 PM PDT 24 28660463 ps
T534 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1664110771 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:43 PM PDT 24 39350734 ps
T104 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3319866817 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:00 PM PDT 24 63908604 ps
T535 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1383335691 Aug 07 05:45:52 PM PDT 24 Aug 07 05:45:55 PM PDT 24 47630368 ps
T536 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3097226717 Aug 07 05:46:00 PM PDT 24 Aug 07 05:46:01 PM PDT 24 125518854 ps
T105 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3820493141 Aug 07 05:45:30 PM PDT 24 Aug 07 05:45:35 PM PDT 24 235915625 ps
T113 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2327249064 Aug 07 05:45:47 PM PDT 24 Aug 07 05:45:48 PM PDT 24 49247339 ps
T537 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1829066040 Aug 07 05:45:45 PM PDT 24 Aug 07 05:45:47 PM PDT 24 235678291 ps
T122 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3692360145 Aug 07 05:45:18 PM PDT 24 Aug 07 05:45:21 PM PDT 24 172766608 ps
T106 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2705000148 Aug 07 05:45:19 PM PDT 24 Aug 07 05:45:24 PM PDT 24 360191545 ps
T538 /workspace/coverage/cover_reg_top/14.hmac_intr_test.770111028 Aug 07 05:45:45 PM PDT 24 Aug 07 05:45:46 PM PDT 24 48144790 ps
T539 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2082167446 Aug 07 05:45:18 PM PDT 24 Aug 07 05:45:24 PM PDT 24 575683571 ps
T123 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4026411972 Aug 07 05:45:58 PM PDT 24 Aug 07 05:46:03 PM PDT 24 425962665 ps
T540 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2208182584 Aug 07 05:45:50 PM PDT 24 Aug 07 05:45:51 PM PDT 24 365333337 ps
T541 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.173980379 Aug 07 05:45:31 PM PDT 24 Aug 07 05:45:33 PM PDT 24 49096546 ps
T542 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2681248846 Aug 07 05:45:36 PM PDT 24 Aug 07 05:45:37 PM PDT 24 17291143 ps
T543 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3450382863 Aug 07 05:45:40 PM PDT 24 Aug 07 05:45:42 PM PDT 24 209411898 ps
T109 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.638018650 Aug 07 05:45:34 PM PDT 24 Aug 07 05:45:49 PM PDT 24 5210961227 ps
T126 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3125313399 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:47 PM PDT 24 1559651245 ps
T544 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1275731265 Aug 07 05:45:52 PM PDT 24 Aug 07 05:45:54 PM PDT 24 136027394 ps
T545 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2292849421 Aug 07 05:45:45 PM PDT 24 Aug 07 05:51:18 PM PDT 24 156878438724 ps
T546 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3225759295 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:00 PM PDT 24 57024694 ps
T547 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1811840984 Aug 07 05:45:57 PM PDT 24 Aug 07 05:45:57 PM PDT 24 42379007 ps
T548 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2453315682 Aug 07 05:45:23 PM PDT 24 Aug 07 05:45:24 PM PDT 24 19688983 ps
T114 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.117870621 Aug 07 05:45:52 PM PDT 24 Aug 07 05:45:54 PM PDT 24 48806570 ps
T115 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4160843351 Aug 07 05:45:18 PM PDT 24 Aug 07 05:45:19 PM PDT 24 29053058 ps
T549 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3984833703 Aug 07 05:45:54 PM PDT 24 Aug 07 05:45:57 PM PDT 24 412874959 ps
T130 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3104983690 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:46 PM PDT 24 439737374 ps
T550 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1140953491 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:00 PM PDT 24 41524081 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.318475463 Aug 07 05:45:19 PM PDT 24 Aug 07 05:45:20 PM PDT 24 41152260 ps
T551 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.645705032 Aug 07 05:45:25 PM PDT 24 Aug 07 05:45:27 PM PDT 24 36931693 ps
T552 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3508104996 Aug 07 05:45:29 PM PDT 24 Aug 07 05:45:29 PM PDT 24 26092915 ps
T553 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2361828168 Aug 07 05:46:03 PM PDT 24 Aug 07 05:46:04 PM PDT 24 19911903 ps
T124 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1511637852 Aug 07 05:45:47 PM PDT 24 Aug 07 05:45:51 PM PDT 24 136675630 ps
T554 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1675618058 Aug 07 05:46:02 PM PDT 24 Aug 07 05:46:03 PM PDT 24 22593919 ps
T555 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1206692865 Aug 07 05:45:35 PM PDT 24 Aug 07 05:45:38 PM PDT 24 172242612 ps
T108 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.297817975 Aug 07 05:45:34 PM PDT 24 Aug 07 05:45:35 PM PDT 24 15258421 ps
T110 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.73106548 Aug 07 05:45:38 PM PDT 24 Aug 07 05:45:39 PM PDT 24 25763549 ps
T556 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1335998206 Aug 07 05:45:32 PM PDT 24 Aug 07 05:45:33 PM PDT 24 99956806 ps
T557 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4220612531 Aug 07 05:45:37 PM PDT 24 Aug 07 05:45:38 PM PDT 24 30042704 ps
T116 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3107260560 Aug 07 05:45:24 PM PDT 24 Aug 07 05:45:26 PM PDT 24 349079147 ps
T558 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1302954149 Aug 07 05:45:50 PM PDT 24 Aug 07 05:45:53 PM PDT 24 187924223 ps
T559 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1567942641 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:00 PM PDT 24 36058153 ps
T560 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3968723765 Aug 07 05:45:38 PM PDT 24 Aug 07 05:45:39 PM PDT 24 256725205 ps
T111 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1698608878 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:43 PM PDT 24 41381045 ps
T561 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.365920459 Aug 07 05:45:44 PM PDT 24 Aug 07 05:45:48 PM PDT 24 215353954 ps
T562 /workspace/coverage/cover_reg_top/31.hmac_intr_test.545431997 Aug 07 05:45:58 PM PDT 24 Aug 07 05:45:59 PM PDT 24 43072231 ps
T563 /workspace/coverage/cover_reg_top/20.hmac_intr_test.86518243 Aug 07 05:45:56 PM PDT 24 Aug 07 05:45:56 PM PDT 24 48225721 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2847020224 Aug 07 05:45:29 PM PDT 24 Aug 07 05:45:30 PM PDT 24 23125089 ps
T117 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.488107138 Aug 07 05:45:30 PM PDT 24 Aug 07 05:45:30 PM PDT 24 53317440 ps
T125 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1630396129 Aug 07 05:45:27 PM PDT 24 Aug 07 05:45:30 PM PDT 24 765531838 ps
T118 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2382261383 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:45 PM PDT 24 83692039 ps
T565 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3657117920 Aug 07 05:45:32 PM PDT 24 Aug 07 05:45:33 PM PDT 24 13220620 ps
T566 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1552141461 Aug 07 05:46:04 PM PDT 24 Aug 07 05:46:05 PM PDT 24 115109352 ps
T567 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3420446718 Aug 07 05:45:22 PM PDT 24 Aug 07 05:45:23 PM PDT 24 50745553 ps
T568 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2951508286 Aug 07 05:45:53 PM PDT 24 Aug 07 05:45:54 PM PDT 24 36047376 ps
T569 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1823268924 Aug 07 05:45:55 PM PDT 24 Aug 07 05:45:58 PM PDT 24 105430142 ps
T570 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3325054588 Aug 07 05:45:57 PM PDT 24 Aug 07 05:45:58 PM PDT 24 11969190 ps
T571 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1420046538 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:46 PM PDT 24 3508657131 ps
T112 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3419815665 Aug 07 05:45:29 PM PDT 24 Aug 07 05:45:30 PM PDT 24 53157833 ps
T572 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.965089390 Aug 07 05:45:44 PM PDT 24 Aug 07 05:45:46 PM PDT 24 102380266 ps
T573 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1384961523 Aug 07 05:46:02 PM PDT 24 Aug 07 05:46:02 PM PDT 24 12408254 ps
T132 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2130354056 Aug 07 05:45:24 PM PDT 24 Aug 07 05:45:28 PM PDT 24 1621606517 ps
T574 /workspace/coverage/cover_reg_top/27.hmac_intr_test.143790025 Aug 07 05:46:02 PM PDT 24 Aug 07 05:46:03 PM PDT 24 31904813 ps
T127 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.833726646 Aug 07 05:45:34 PM PDT 24 Aug 07 05:45:37 PM PDT 24 774692750 ps
T575 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1857471888 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:01 PM PDT 24 99070185 ps
T576 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3871334583 Aug 07 05:45:25 PM PDT 24 Aug 07 05:45:30 PM PDT 24 110257547 ps
T131 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.543928546 Aug 07 05:45:55 PM PDT 24 Aug 07 05:45:58 PM PDT 24 156582044 ps
T577 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4102190836 Aug 07 05:45:30 PM PDT 24 Aug 07 05:45:31 PM PDT 24 216418080 ps
T578 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1561988709 Aug 07 05:45:38 PM PDT 24 Aug 07 05:45:41 PM PDT 24 530872720 ps
T579 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1822762212 Aug 07 05:45:44 PM PDT 24 Aug 07 05:45:46 PM PDT 24 68475938 ps
T580 /workspace/coverage/cover_reg_top/29.hmac_intr_test.71271918 Aug 07 05:45:58 PM PDT 24 Aug 07 05:45:59 PM PDT 24 18628401 ps
T581 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2044754262 Aug 07 05:46:05 PM PDT 24 Aug 07 05:46:06 PM PDT 24 25152001 ps
T582 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.423406046 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:45 PM PDT 24 383489635 ps
T583 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.173254926 Aug 07 05:45:49 PM PDT 24 Aug 07 05:45:51 PM PDT 24 90806169 ps
T584 /workspace/coverage/cover_reg_top/12.hmac_intr_test.693968055 Aug 07 05:45:47 PM PDT 24 Aug 07 05:45:47 PM PDT 24 33314716 ps
T585 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1072073238 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:43 PM PDT 24 46097721 ps
T586 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2098948434 Aug 07 05:45:49 PM PDT 24 Aug 07 05:45:53 PM PDT 24 749652750 ps
T587 /workspace/coverage/cover_reg_top/35.hmac_intr_test.227174277 Aug 07 05:45:58 PM PDT 24 Aug 07 05:45:59 PM PDT 24 27856538 ps
T588 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2951299226 Aug 07 05:45:59 PM PDT 24 Aug 07 05:45:59 PM PDT 24 17048070 ps
T589 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.472455382 Aug 07 05:45:19 PM PDT 24 Aug 07 05:45:22 PM PDT 24 2030229115 ps
T590 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3317594385 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:45 PM PDT 24 153065853 ps
T591 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3305586526 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:43 PM PDT 24 13357353 ps
T592 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3202287401 Aug 07 05:45:44 PM PDT 24 Aug 07 05:45:47 PM PDT 24 835102433 ps
T593 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3807033912 Aug 07 05:45:29 PM PDT 24 Aug 07 05:45:30 PM PDT 24 88641133 ps
T594 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3773902562 Aug 07 05:45:30 PM PDT 24 Aug 07 05:45:35 PM PDT 24 214239332 ps
T595 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1410038645 Aug 07 05:45:46 PM PDT 24 Aug 07 05:45:47 PM PDT 24 40933383 ps
T128 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3637167067 Aug 07 05:45:49 PM PDT 24 Aug 07 05:45:54 PM PDT 24 2003126121 ps
T596 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1238561111 Aug 07 05:45:22 PM PDT 24 Aug 07 05:45:27 PM PDT 24 431875497 ps
T597 /workspace/coverage/cover_reg_top/16.hmac_intr_test.678916062 Aug 07 05:45:47 PM PDT 24 Aug 07 05:45:48 PM PDT 24 95334684 ps
T598 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3188061785 Aug 07 05:45:26 PM PDT 24 Aug 07 05:45:27 PM PDT 24 68339185 ps
T599 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1502133641 Aug 07 05:45:25 PM PDT 24 Aug 07 05:45:26 PM PDT 24 107203682 ps
T600 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2544827979 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:00 PM PDT 24 30122743 ps
T601 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3349844577 Aug 07 05:45:41 PM PDT 24 Aug 07 05:45:42 PM PDT 24 41727879 ps
T602 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.157998316 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:47 PM PDT 24 1101124217 ps
T603 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.492713314 Aug 07 05:45:46 PM PDT 24 Aug 07 05:45:48 PM PDT 24 113046427 ps
T604 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2578085017 Aug 07 05:45:19 PM PDT 24 Aug 07 05:45:21 PM PDT 24 33495331 ps
T605 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3266088239 Aug 07 05:45:56 PM PDT 24 Aug 07 05:45:58 PM PDT 24 128163398 ps
T606 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2737002955 Aug 07 05:46:09 PM PDT 24 Aug 07 05:46:09 PM PDT 24 118936490 ps
T607 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3708830600 Aug 07 05:45:48 PM PDT 24 Aug 07 05:45:49 PM PDT 24 29663801 ps
T608 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3387849915 Aug 07 05:45:44 PM PDT 24 Aug 07 05:45:48 PM PDT 24 51627416 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.800863980 Aug 07 05:45:20 PM PDT 24 Aug 07 05:45:24 PM PDT 24 315216170 ps
T610 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.818652045 Aug 07 05:45:38 PM PDT 24 Aug 07 05:45:41 PM PDT 24 352349523 ps
T611 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3449392785 Aug 07 05:45:58 PM PDT 24 Aug 07 05:45:59 PM PDT 24 15168552 ps
T612 /workspace/coverage/cover_reg_top/26.hmac_intr_test.803368321 Aug 07 05:45:58 PM PDT 24 Aug 07 05:45:59 PM PDT 24 47248909 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1731291794 Aug 07 05:45:17 PM PDT 24 Aug 07 05:45:23 PM PDT 24 481504043 ps
T614 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4199372994 Aug 07 05:45:23 PM PDT 24 Aug 07 05:45:23 PM PDT 24 28168766 ps
T615 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3925656697 Aug 07 05:45:34 PM PDT 24 Aug 07 05:45:36 PM PDT 24 383129724 ps
T616 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.398030951 Aug 07 05:45:56 PM PDT 24 Aug 07 05:45:58 PM PDT 24 865457530 ps
T129 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2163591946 Aug 07 05:45:33 PM PDT 24 Aug 07 05:45:37 PM PDT 24 464515879 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2545132742 Aug 07 05:45:26 PM PDT 24 Aug 07 05:45:27 PM PDT 24 255135406 ps
T618 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2931669990 Aug 07 05:45:56 PM PDT 24 Aug 07 05:45:58 PM PDT 24 63261102 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3907325558 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:43 PM PDT 24 19939466 ps
T620 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2062744595 Aug 07 05:45:56 PM PDT 24 Aug 07 05:45:57 PM PDT 24 55588754 ps
T621 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2731273360 Aug 07 05:46:04 PM PDT 24 Aug 07 05:46:04 PM PDT 24 17882396 ps
T622 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.613614274 Aug 07 05:45:37 PM PDT 24 Aug 07 05:45:39 PM PDT 24 101996129 ps
T623 /workspace/coverage/cover_reg_top/49.hmac_intr_test.967680019 Aug 07 05:46:04 PM PDT 24 Aug 07 05:46:05 PM PDT 24 61088084 ps
T624 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1211429307 Aug 07 05:46:05 PM PDT 24 Aug 07 05:46:06 PM PDT 24 132584260 ps
T625 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4079931772 Aug 07 05:45:39 PM PDT 24 Aug 07 05:45:41 PM PDT 24 79284338 ps
T626 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.258356973 Aug 07 05:45:37 PM PDT 24 Aug 07 05:45:38 PM PDT 24 340999344 ps
T627 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2919888835 Aug 07 05:45:41 PM PDT 24 Aug 07 05:45:42 PM PDT 24 239341747 ps
T628 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1914573662 Aug 07 05:45:40 PM PDT 24 Aug 07 05:45:41 PM PDT 24 21643427 ps
T629 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2625568527 Aug 07 05:46:02 PM PDT 24 Aug 07 05:46:03 PM PDT 24 24197475 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1861671184 Aug 07 05:45:48 PM PDT 24 Aug 07 05:45:48 PM PDT 24 38018759 ps
T631 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3229604610 Aug 07 05:45:31 PM PDT 24 Aug 07 05:45:34 PM PDT 24 258417405 ps
T632 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1659051882 Aug 07 05:45:31 PM PDT 24 Aug 07 05:45:33 PM PDT 24 58886918 ps
T633 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1542233494 Aug 07 05:45:41 PM PDT 24 Aug 07 05:45:43 PM PDT 24 215893432 ps
T634 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3826211213 Aug 07 05:46:03 PM PDT 24 Aug 07 05:46:04 PM PDT 24 11517826 ps
T635 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2836092480 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:45 PM PDT 24 167529087 ps
T636 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1127579514 Aug 07 05:45:25 PM PDT 24 Aug 07 05:45:26 PM PDT 24 156679814 ps
T637 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1121445072 Aug 07 05:45:59 PM PDT 24 Aug 07 05:46:00 PM PDT 24 36921641 ps
T638 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1029602703 Aug 07 05:45:25 PM PDT 24 Aug 07 05:45:29 PM PDT 24 211209553 ps
T639 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3824944199 Aug 07 05:46:36 PM PDT 24 Aug 07 05:46:39 PM PDT 24 865701685 ps
T640 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2384790304 Aug 07 05:45:50 PM PDT 24 Aug 07 05:45:53 PM PDT 24 130962918 ps
T641 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4287901599 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:44 PM PDT 24 22040526 ps
T642 /workspace/coverage/cover_reg_top/9.hmac_intr_test.452957566 Aug 07 05:45:37 PM PDT 24 Aug 07 05:45:38 PM PDT 24 35330169 ps
T643 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.338957194 Aug 07 05:45:42 PM PDT 24 Aug 07 05:45:46 PM PDT 24 445114502 ps
T644 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1719506782 Aug 07 05:45:44 PM PDT 24 Aug 07 05:45:47 PM PDT 24 304899413 ps
T645 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.604406621 Aug 07 05:45:33 PM PDT 24 Aug 07 05:45:35 PM PDT 24 456276414 ps
T646 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3395389414 Aug 07 05:45:50 PM PDT 24 Aug 07 05:45:54 PM PDT 24 482822561 ps
T647 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1780140411 Aug 07 05:45:40 PM PDT 24 Aug 07 05:45:43 PM PDT 24 327720287 ps
T648 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2705806353 Aug 07 05:45:55 PM PDT 24 Aug 07 05:45:58 PM PDT 24 186982460 ps
T649 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1252785990 Aug 07 05:46:09 PM PDT 24 Aug 07 05:46:09 PM PDT 24 31050786 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1359966518 Aug 07 05:45:43 PM PDT 24 Aug 07 05:45:44 PM PDT 24 28160888 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.218678777 Aug 07 05:45:46 PM PDT 24 Aug 07 05:45:47 PM PDT 24 34901138 ps
T652 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3864121081 Aug 07 05:45:49 PM PDT 24 Aug 07 05:45:50 PM PDT 24 22238611 ps
T653 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2414555476 Aug 07 05:45:57 PM PDT 24 Aug 07 05:45:58 PM PDT 24 41079342 ps
T654 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2135394876 Aug 07 05:45:28 PM PDT 24 Aug 07 05:45:29 PM PDT 24 14361766 ps
T655 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1387911916 Aug 07 05:45:56 PM PDT 24 Aug 07 05:45:57 PM PDT 24 16082055 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3209258405 Aug 07 05:45:35 PM PDT 24 Aug 07 05:45:36 PM PDT 24 64649173 ps
T657 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2358701358 Aug 07 05:45:17 PM PDT 24 Aug 07 05:45:20 PM PDT 24 149271311 ps
T658 /workspace/coverage/cover_reg_top/1.hmac_intr_test.733876383 Aug 07 05:45:18 PM PDT 24 Aug 07 05:45:19 PM PDT 24 12873202 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.544751971 Aug 07 05:45:23 PM PDT 24 Aug 07 05:45:29 PM PDT 24 1082419081 ps

Test location /workspace/coverage/default/40.hmac_long_msg.2162075323
Short name T5
Test name
Test status
Simulation time 10928030325 ps
CPU time 140.04 seconds
Started Aug 07 05:47:47 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 199912 kb
Host smart-012b2d93-a7e4-498c-b1ab-64b4e9102f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162075323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2162075323
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.523473674
Short name T8
Test name
Test status
Simulation time 317689820450 ps
CPU time 3539.32 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 06:45:22 PM PDT 24
Peak memory 742868 kb
Host smart-7cdf442d-1cf4-4e8a-9902-3afd8b86fece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523473674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.523473674
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2154934677
Short name T52
Test name
Test status
Simulation time 185085155833 ps
CPU time 1324.25 seconds
Started Aug 07 05:47:27 PM PDT 24
Finished Aug 07 06:09:32 PM PDT 24
Peak memory 747508 kb
Host smart-bc35d282-73b4-46cc-a399-98bd14bfaccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154934677 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2154934677
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2549446435
Short name T22
Test name
Test status
Simulation time 90717402616 ps
CPU time 3270.05 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 06:41:03 PM PDT 24
Peak memory 717388 kb
Host smart-a032f70e-8c2b-4f7f-bf72-5c4a9fe36e2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549446435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2549446435
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1296813867
Short name T7
Test name
Test status
Simulation time 30320933966 ps
CPU time 815.77 seconds
Started Aug 07 05:47:58 PM PDT 24
Finished Aug 07 06:01:34 PM PDT 24
Peak memory 650892 kb
Host smart-41d71614-b060-4258-a381-48c0a7b1f3b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296813867 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1296813867
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4026411972
Short name T123
Test name
Test status
Simulation time 425962665 ps
CPU time 4.25 seconds
Started Aug 07 05:45:58 PM PDT 24
Finished Aug 07 05:46:03 PM PDT 24
Peak memory 200096 kb
Host smart-9a221d9e-5db4-4cf7-a17c-33937012f061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026411972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4026411972
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2489214787
Short name T60
Test name
Test status
Simulation time 167980760 ps
CPU time 0.99 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:46:34 PM PDT 24
Peak memory 219516 kb
Host smart-fdf3b9d9-92e1-4fea-849c-117cc5a635de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489214787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2489214787
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3632110498
Short name T82
Test name
Test status
Simulation time 432239937972 ps
CPU time 4043.23 seconds
Started Aug 07 05:48:05 PM PDT 24
Finished Aug 07 06:55:29 PM PDT 24
Peak memory 852820 kb
Host smart-1448eb5d-deab-49de-84ee-326d8be0607e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632110498 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3632110498
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2125993357
Short name T103
Test name
Test status
Simulation time 28660463 ps
CPU time 0.9 seconds
Started Aug 07 05:45:48 PM PDT 24
Finished Aug 07 05:45:49 PM PDT 24
Peak memory 199972 kb
Host smart-bc9ac655-1a8c-4d92-bb5e-784820cf4685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125993357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2125993357
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3595566061
Short name T28
Test name
Test status
Simulation time 30163721057 ps
CPU time 3909.97 seconds
Started Aug 07 05:47:16 PM PDT 24
Finished Aug 07 06:52:27 PM PDT 24
Peak memory 837600 kb
Host smart-861963c9-bce5-46a5-90e3-fdf5bf885560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595566061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3595566061
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1853471762
Short name T37
Test name
Test status
Simulation time 60708064279 ps
CPU time 1238.36 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 06:07:32 PM PDT 24
Peak memory 646908 kb
Host smart-4d68eccb-c94c-4fa5-b3a0-72dd2109c283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853471762 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1853471762
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4067835348
Short name T18
Test name
Test status
Simulation time 5546609049 ps
CPU time 81.68 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:47:57 PM PDT 24
Peak memory 208012 kb
Host smart-1d030af5-769a-480f-8ef3-4c13cabfe092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067835348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4067835348
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1511637852
Short name T124
Test name
Test status
Simulation time 136675630 ps
CPU time 3.98 seconds
Started Aug 07 05:45:47 PM PDT 24
Finished Aug 07 05:45:51 PM PDT 24
Peak memory 200116 kb
Host smart-41926dd5-3fa9-49a3-8fe3-61421ad32c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511637852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1511637852
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.347065436
Short name T174
Test name
Test status
Simulation time 41033878 ps
CPU time 0.58 seconds
Started Aug 07 05:46:20 PM PDT 24
Finished Aug 07 05:46:21 PM PDT 24
Peak memory 195904 kb
Host smart-5564532e-8cc8-4aa7-b3dc-39093ba517b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347065436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.347065436
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3216240425
Short name T121
Test name
Test status
Simulation time 74485415327 ps
CPU time 1949.84 seconds
Started Aug 07 05:46:45 PM PDT 24
Finished Aug 07 06:19:15 PM PDT 24
Peak memory 724428 kb
Host smart-4342003d-eb8b-4327-81c0-310e8aee5a63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216240425 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3216240425
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.338957194
Short name T643
Test name
Test status
Simulation time 445114502 ps
CPU time 4.12 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:46 PM PDT 24
Peak memory 200100 kb
Host smart-fbeb4e16-a223-462b-9e7e-454c289254ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338957194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.338957194
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1719506782
Short name T644
Test name
Test status
Simulation time 304899413 ps
CPU time 3.19 seconds
Started Aug 07 05:45:44 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 200048 kb
Host smart-1e5d26b9-5c01-4a25-93c8-e6b4af1c13dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719506782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1719506782
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1570407891
Short name T9
Test name
Test status
Simulation time 17558055326 ps
CPU time 280.17 seconds
Started Aug 07 05:46:31 PM PDT 24
Finished Aug 07 05:51:11 PM PDT 24
Peak memory 208556 kb
Host smart-e3e2d91a-6bc0-4841-867d-122fe93a621e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570407891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1570407891
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2082167446
Short name T539
Test name
Test status
Simulation time 575683571 ps
CPU time 5.5 seconds
Started Aug 07 05:45:18 PM PDT 24
Finished Aug 07 05:45:24 PM PDT 24
Peak memory 200088 kb
Host smart-2610c383-1a02-4e4a-9442-6c519b7e28be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082167446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2082167446
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.544751971
Short name T659
Test name
Test status
Simulation time 1082419081 ps
CPU time 6.04 seconds
Started Aug 07 05:45:23 PM PDT 24
Finished Aug 07 05:45:29 PM PDT 24
Peak memory 200064 kb
Host smart-120c12cb-d6ed-4ff3-9cd9-2f8d5f9b8774
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544751971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.544751971
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1127579514
Short name T636
Test name
Test status
Simulation time 156679814 ps
CPU time 0.99 seconds
Started Aug 07 05:45:25 PM PDT 24
Finished Aug 07 05:45:26 PM PDT 24
Peak memory 199640 kb
Host smart-7f931648-538b-4cc7-aaf2-eb68b24af8c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127579514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1127579514
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4126572564
Short name T527
Test name
Test status
Simulation time 85933064 ps
CPU time 1.52 seconds
Started Aug 07 05:45:19 PM PDT 24
Finished Aug 07 05:45:20 PM PDT 24
Peak memory 200204 kb
Host smart-ff7fe41e-9c44-44f0-9a7d-b292f9c8f1ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126572564 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4126572564
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4199372994
Short name T614
Test name
Test status
Simulation time 28168766 ps
CPU time 0.8 seconds
Started Aug 07 05:45:23 PM PDT 24
Finished Aug 07 05:45:23 PM PDT 24
Peak memory 199856 kb
Host smart-a3141a91-c7be-4ae0-b47f-4c15b33c96c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199372994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4199372994
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3420446718
Short name T567
Test name
Test status
Simulation time 50745553 ps
CPU time 0.67 seconds
Started Aug 07 05:45:22 PM PDT 24
Finished Aug 07 05:45:23 PM PDT 24
Peak memory 194984 kb
Host smart-694b9088-169a-405b-b6b5-6c20b309356b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420446718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3420446718
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2545132742
Short name T617
Test name
Test status
Simulation time 255135406 ps
CPU time 1.62 seconds
Started Aug 07 05:45:26 PM PDT 24
Finished Aug 07 05:45:27 PM PDT 24
Peak memory 200056 kb
Host smart-73eb30a1-2cff-4be7-be8e-2ad4d778dea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545132742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2545132742
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2358701358
Short name T657
Test name
Test status
Simulation time 149271311 ps
CPU time 3.26 seconds
Started Aug 07 05:45:17 PM PDT 24
Finished Aug 07 05:45:20 PM PDT 24
Peak memory 199984 kb
Host smart-851965db-696f-4958-bd93-709d4ee04a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358701358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2358701358
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.800863980
Short name T609
Test name
Test status
Simulation time 315216170 ps
CPU time 3.91 seconds
Started Aug 07 05:45:20 PM PDT 24
Finished Aug 07 05:45:24 PM PDT 24
Peak memory 200124 kb
Host smart-024b523c-fad1-43a3-ade6-bcbc48761bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800863980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.800863980
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1731291794
Short name T613
Test name
Test status
Simulation time 481504043 ps
CPU time 5.41 seconds
Started Aug 07 05:45:17 PM PDT 24
Finished Aug 07 05:45:23 PM PDT 24
Peak memory 200112 kb
Host smart-8c682546-d768-4193-9316-f2b632ce4778
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731291794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1731291794
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2705000148
Short name T106
Test name
Test status
Simulation time 360191545 ps
CPU time 5.76 seconds
Started Aug 07 05:45:19 PM PDT 24
Finished Aug 07 05:45:24 PM PDT 24
Peak memory 199000 kb
Host smart-325eea5e-2c26-4238-87c8-cde4aaa43951
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705000148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2705000148
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.318475463
Short name T107
Test name
Test status
Simulation time 41152260 ps
CPU time 0.99 seconds
Started Aug 07 05:45:19 PM PDT 24
Finished Aug 07 05:45:20 PM PDT 24
Peak memory 199732 kb
Host smart-7b8e8ae1-dc98-4df5-9e5d-1cc88170c194
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318475463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.318475463
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3188061785
Short name T598
Test name
Test status
Simulation time 68339185 ps
CPU time 1.11 seconds
Started Aug 07 05:45:26 PM PDT 24
Finished Aug 07 05:45:27 PM PDT 24
Peak memory 199928 kb
Host smart-482b9213-fad6-480c-8c23-08fad5a55a41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188061785 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3188061785
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4160843351
Short name T115
Test name
Test status
Simulation time 29053058 ps
CPU time 0.95 seconds
Started Aug 07 05:45:18 PM PDT 24
Finished Aug 07 05:45:19 PM PDT 24
Peak memory 199792 kb
Host smart-edde628e-c96d-4a99-9893-918c50d30b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160843351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4160843351
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.733876383
Short name T658
Test name
Test status
Simulation time 12873202 ps
CPU time 0.56 seconds
Started Aug 07 05:45:18 PM PDT 24
Finished Aug 07 05:45:19 PM PDT 24
Peak memory 195008 kb
Host smart-ab6b67a6-87bd-450c-9b83-84c65cfa5d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733876383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.733876383
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.472455382
Short name T589
Test name
Test status
Simulation time 2030229115 ps
CPU time 2.31 seconds
Started Aug 07 05:45:19 PM PDT 24
Finished Aug 07 05:45:22 PM PDT 24
Peak memory 200104 kb
Host smart-e542c38d-7711-4dac-ad0e-4dfbd5f217a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472455382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.472455382
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2578085017
Short name T604
Test name
Test status
Simulation time 33495331 ps
CPU time 1.95 seconds
Started Aug 07 05:45:19 PM PDT 24
Finished Aug 07 05:45:21 PM PDT 24
Peak memory 200136 kb
Host smart-71a3ecb0-19f1-448f-9a48-cb2ececc6e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578085017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2578085017
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3692360145
Short name T122
Test name
Test status
Simulation time 172766608 ps
CPU time 2.98 seconds
Started Aug 07 05:45:18 PM PDT 24
Finished Aug 07 05:45:21 PM PDT 24
Peak memory 200116 kb
Host smart-08fd84ae-a1dd-4044-ba58-a2e73ba052e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692360145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3692360145
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2292849421
Short name T545
Test name
Test status
Simulation time 156878438724 ps
CPU time 332.44 seconds
Started Aug 07 05:45:45 PM PDT 24
Finished Aug 07 05:51:18 PM PDT 24
Peak memory 216672 kb
Host smart-b7c0c4c0-2925-492d-9174-8a86d686e275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292849421 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2292849421
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3907325558
Short name T619
Test name
Test status
Simulation time 19939466 ps
CPU time 0.69 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 197980 kb
Host smart-f5a238ae-3c12-4d58-85b5-c01615801ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907325558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3907325558
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1664110771
Short name T534
Test name
Test status
Simulation time 39350734 ps
CPU time 0.6 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 195008 kb
Host smart-738f2cb9-b4aa-4a79-9c24-628537043dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664110771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1664110771
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4079931772
Short name T625
Test name
Test status
Simulation time 79284338 ps
CPU time 1.07 seconds
Started Aug 07 05:45:39 PM PDT 24
Finished Aug 07 05:45:41 PM PDT 24
Peak memory 199972 kb
Host smart-53080773-f9be-4e8e-b8c4-a394a331f398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079931772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4079931772
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.365920459
Short name T561
Test name
Test status
Simulation time 215353954 ps
CPU time 4.22 seconds
Started Aug 07 05:45:44 PM PDT 24
Finished Aug 07 05:45:48 PM PDT 24
Peak memory 200040 kb
Host smart-91861484-5585-4a07-98a3-753fd5c1a130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365920459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.365920459
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1822762212
Short name T579
Test name
Test status
Simulation time 68475938 ps
CPU time 2.44 seconds
Started Aug 07 05:45:44 PM PDT 24
Finished Aug 07 05:45:46 PM PDT 24
Peak memory 200120 kb
Host smart-c97bec69-c62b-4690-9623-4d1083b70da8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822762212 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1822762212
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1698608878
Short name T111
Test name
Test status
Simulation time 41381045 ps
CPU time 0.67 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 198220 kb
Host smart-b3893a59-a90c-47e7-a564-002b82bae015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698608878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1698608878
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1072073238
Short name T585
Test name
Test status
Simulation time 46097721 ps
CPU time 0.58 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 194956 kb
Host smart-f93fb809-0321-4a5e-a807-7c75147891e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072073238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1072073238
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.492713314
Short name T603
Test name
Test status
Simulation time 113046427 ps
CPU time 2.28 seconds
Started Aug 07 05:45:46 PM PDT 24
Finished Aug 07 05:45:48 PM PDT 24
Peak memory 200120 kb
Host smart-db9b1e85-3ad5-435b-850e-38d03e3b0d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492713314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.492713314
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2919888835
Short name T627
Test name
Test status
Simulation time 239341747 ps
CPU time 1.41 seconds
Started Aug 07 05:45:41 PM PDT 24
Finished Aug 07 05:45:42 PM PDT 24
Peak memory 200088 kb
Host smart-8b6ca50f-4a90-4aab-9830-bb1c9f11367f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919888835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2919888835
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3104983690
Short name T130
Test name
Test status
Simulation time 439737374 ps
CPU time 4.41 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:46 PM PDT 24
Peak memory 200156 kb
Host smart-0d3ad344-6fac-4ac3-a5e0-b859e1badfb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104983690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3104983690
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.965089390
Short name T572
Test name
Test status
Simulation time 102380266 ps
CPU time 2.4 seconds
Started Aug 07 05:45:44 PM PDT 24
Finished Aug 07 05:45:46 PM PDT 24
Peak memory 200184 kb
Host smart-2e95fa47-b699-4385-b3e0-8d8b5b0c19a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965089390 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.965089390
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4287901599
Short name T641
Test name
Test status
Simulation time 22040526 ps
CPU time 0.73 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:44 PM PDT 24
Peak memory 198092 kb
Host smart-a9743c52-e660-45e9-9778-7697180a6c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287901599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4287901599
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.693968055
Short name T584
Test name
Test status
Simulation time 33314716 ps
CPU time 0.62 seconds
Started Aug 07 05:45:47 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 195376 kb
Host smart-50e917be-e107-4332-a1a1-ec09e8fa9e42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693968055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.693968055
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1542233494
Short name T633
Test name
Test status
Simulation time 215893432 ps
CPU time 1.22 seconds
Started Aug 07 05:45:41 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 200132 kb
Host smart-f2e90e2b-511f-4cde-b2e4-d64e5746981a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542233494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1542233494
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3202287401
Short name T592
Test name
Test status
Simulation time 835102433 ps
CPU time 3.34 seconds
Started Aug 07 05:45:44 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 200156 kb
Host smart-bb5d87c3-f7f8-4194-ac35-ad97e14815b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202287401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3202287401
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.157998316
Short name T602
Test name
Test status
Simulation time 1101124217 ps
CPU time 4.13 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 200116 kb
Host smart-3f9cdb18-4b52-48d5-8147-a0c20a5604a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157998316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.157998316
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1829066040
Short name T537
Test name
Test status
Simulation time 235678291 ps
CPU time 1.23 seconds
Started Aug 07 05:45:45 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 200020 kb
Host smart-b1b475b8-2466-4e87-a10d-04c466e424c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829066040 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1829066040
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1359966518
Short name T650
Test name
Test status
Simulation time 28160888 ps
CPU time 0.81 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:44 PM PDT 24
Peak memory 199600 kb
Host smart-0f621342-1774-451c-9770-0793ab8286ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359966518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1359966518
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3305586526
Short name T591
Test name
Test status
Simulation time 13357353 ps
CPU time 0.58 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 195016 kb
Host smart-eb5be359-8c78-49f4-a4a6-a2ab536ded9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305586526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3305586526
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1410038645
Short name T595
Test name
Test status
Simulation time 40933383 ps
CPU time 1.07 seconds
Started Aug 07 05:45:46 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 200184 kb
Host smart-4d86c74f-8a65-4dbd-8712-4219b014cdbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410038645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1410038645
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2836092480
Short name T635
Test name
Test status
Simulation time 167529087 ps
CPU time 3.39 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:45 PM PDT 24
Peak memory 200000 kb
Host smart-9085928d-56f5-49d4-8430-0861a6e7499a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836092480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2836092480
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2384790304
Short name T640
Test name
Test status
Simulation time 130962918 ps
CPU time 2.57 seconds
Started Aug 07 05:45:50 PM PDT 24
Finished Aug 07 05:45:53 PM PDT 24
Peak memory 215848 kb
Host smart-e2d99b9f-1f4d-4735-beee-31b07d7840d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384790304 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2384790304
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.218678777
Short name T651
Test name
Test status
Simulation time 34901138 ps
CPU time 0.95 seconds
Started Aug 07 05:45:46 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 199928 kb
Host smart-1a5fddce-5886-4ca2-8e3e-1be78deeaa78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218678777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.218678777
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.770111028
Short name T538
Test name
Test status
Simulation time 48144790 ps
CPU time 0.59 seconds
Started Aug 07 05:45:45 PM PDT 24
Finished Aug 07 05:45:46 PM PDT 24
Peak memory 194916 kb
Host smart-6c8072ff-e94f-4de1-98e4-495b135d816a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770111028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.770111028
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2327249064
Short name T113
Test name
Test status
Simulation time 49247339 ps
CPU time 1.08 seconds
Started Aug 07 05:45:47 PM PDT 24
Finished Aug 07 05:45:48 PM PDT 24
Peak memory 200012 kb
Host smart-5656a708-8c0b-47fa-b21f-c4852a39572a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327249064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2327249064
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2098948434
Short name T586
Test name
Test status
Simulation time 749652750 ps
CPU time 3.18 seconds
Started Aug 07 05:45:49 PM PDT 24
Finished Aug 07 05:45:53 PM PDT 24
Peak memory 200112 kb
Host smart-cbbf6966-0ee5-4832-86cd-4145e3fc42b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098948434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2098948434
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3395389414
Short name T646
Test name
Test status
Simulation time 482822561 ps
CPU time 4 seconds
Started Aug 07 05:45:50 PM PDT 24
Finished Aug 07 05:45:54 PM PDT 24
Peak memory 200136 kb
Host smart-3d552159-0a88-4e8c-a568-68f4ecd5ec0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395389414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3395389414
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3387849915
Short name T608
Test name
Test status
Simulation time 51627416 ps
CPU time 3.27 seconds
Started Aug 07 05:45:44 PM PDT 24
Finished Aug 07 05:45:48 PM PDT 24
Peak memory 216564 kb
Host smart-467a136d-bfdd-4e22-92ee-2d52b6b8ef3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387849915 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3387849915
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1861671184
Short name T630
Test name
Test status
Simulation time 38018759 ps
CPU time 0.64 seconds
Started Aug 07 05:45:48 PM PDT 24
Finished Aug 07 05:45:48 PM PDT 24
Peak memory 195064 kb
Host smart-204ebb9d-1d0b-4d12-bd8d-9a0bb680a895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861671184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1861671184
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3864121081
Short name T652
Test name
Test status
Simulation time 22238611 ps
CPU time 1.08 seconds
Started Aug 07 05:45:49 PM PDT 24
Finished Aug 07 05:45:50 PM PDT 24
Peak memory 198604 kb
Host smart-8c292657-a83c-4887-8ac0-f5e23d93b542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864121081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3864121081
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.173254926
Short name T583
Test name
Test status
Simulation time 90806169 ps
CPU time 2.16 seconds
Started Aug 07 05:45:49 PM PDT 24
Finished Aug 07 05:45:51 PM PDT 24
Peak memory 200080 kb
Host smart-172f1f59-f296-486a-8d32-a656b97efe18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173254926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.173254926
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2705806353
Short name T648
Test name
Test status
Simulation time 186982460 ps
CPU time 2.81 seconds
Started Aug 07 05:45:55 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 200180 kb
Host smart-11a54586-6d7a-46a8-97fd-611405db6186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705806353 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2705806353
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3708830600
Short name T607
Test name
Test status
Simulation time 29663801 ps
CPU time 0.94 seconds
Started Aug 07 05:45:48 PM PDT 24
Finished Aug 07 05:45:49 PM PDT 24
Peak memory 199972 kb
Host smart-2a43d91c-b470-473f-8fff-24eb108f9dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708830600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3708830600
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.678916062
Short name T597
Test name
Test status
Simulation time 95334684 ps
CPU time 0.59 seconds
Started Aug 07 05:45:47 PM PDT 24
Finished Aug 07 05:45:48 PM PDT 24
Peak memory 194972 kb
Host smart-385167a7-bd38-4172-830c-868133e2bc08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678916062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.678916062
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1857471888
Short name T575
Test name
Test status
Simulation time 99070185 ps
CPU time 1.77 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:01 PM PDT 24
Peak memory 200100 kb
Host smart-0d6dcfc0-de19-4314-89a2-80643e8c1463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857471888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1857471888
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2208182584
Short name T540
Test name
Test status
Simulation time 365333337 ps
CPU time 1.62 seconds
Started Aug 07 05:45:50 PM PDT 24
Finished Aug 07 05:45:51 PM PDT 24
Peak memory 200152 kb
Host smart-33757a26-5074-467c-aa74-4d4d8fd9d193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208182584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2208182584
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3637167067
Short name T128
Test name
Test status
Simulation time 2003126121 ps
CPU time 4.39 seconds
Started Aug 07 05:45:49 PM PDT 24
Finished Aug 07 05:45:54 PM PDT 24
Peak memory 200124 kb
Host smart-37b121e2-2046-4035-aa6a-be0c0369cde6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637167067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3637167067
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1823268924
Short name T569
Test name
Test status
Simulation time 105430142 ps
CPU time 3.31 seconds
Started Aug 07 05:45:55 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 208424 kb
Host smart-66e59c37-7e91-4211-9c6b-187d5196ac24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823268924 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1823268924
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3319866817
Short name T104
Test name
Test status
Simulation time 63908604 ps
CPU time 0.71 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:00 PM PDT 24
Peak memory 197880 kb
Host smart-ab5c1b46-682d-4e94-8383-55ea8326f664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319866817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3319866817
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1387911916
Short name T655
Test name
Test status
Simulation time 16082055 ps
CPU time 0.59 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:57 PM PDT 24
Peak memory 195116 kb
Host smart-ce65d5c1-8356-44e5-916c-4499c2dccf51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387911916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1387911916
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2931669990
Short name T618
Test name
Test status
Simulation time 63261102 ps
CPU time 1.61 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 200048 kb
Host smart-5d04a3b9-0f0a-4a93-b460-87149d8c6052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931669990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2931669990
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1383335691
Short name T535
Test name
Test status
Simulation time 47630368 ps
CPU time 2.31 seconds
Started Aug 07 05:45:52 PM PDT 24
Finished Aug 07 05:45:55 PM PDT 24
Peak memory 200128 kb
Host smart-f4766821-84b9-4827-a90e-0900862d10a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383335691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1383335691
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2398817566
Short name T74
Test name
Test status
Simulation time 483680468 ps
CPU time 1.81 seconds
Started Aug 07 05:45:54 PM PDT 24
Finished Aug 07 05:45:56 PM PDT 24
Peak memory 199324 kb
Host smart-1a2e86e5-fe74-4337-b467-2bc36193dbfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398817566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2398817566
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3984833703
Short name T549
Test name
Test status
Simulation time 412874959 ps
CPU time 2.26 seconds
Started Aug 07 05:45:54 PM PDT 24
Finished Aug 07 05:45:57 PM PDT 24
Peak memory 199372 kb
Host smart-d2e277cf-0d49-44f7-9e4d-cf5095738a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984833703 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3984833703
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2544827979
Short name T600
Test name
Test status
Simulation time 30122743 ps
CPU time 0.74 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:00 PM PDT 24
Peak memory 198044 kb
Host smart-aa26aed9-dacf-4728-9f2b-591ef4640db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544827979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2544827979
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3225759295
Short name T546
Test name
Test status
Simulation time 57024694 ps
CPU time 0.62 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:00 PM PDT 24
Peak memory 195076 kb
Host smart-4f073ad2-9111-4c0c-936c-dda609ca6a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225759295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3225759295
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.117870621
Short name T114
Test name
Test status
Simulation time 48806570 ps
CPU time 2.08 seconds
Started Aug 07 05:45:52 PM PDT 24
Finished Aug 07 05:45:54 PM PDT 24
Peak memory 200168 kb
Host smart-e05a35a3-629c-4b0f-ba11-63328a98bf8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117870621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.117870621
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1302954149
Short name T558
Test name
Test status
Simulation time 187924223 ps
CPU time 2.63 seconds
Started Aug 07 05:45:50 PM PDT 24
Finished Aug 07 05:45:53 PM PDT 24
Peak memory 200196 kb
Host smart-fb7f26bf-d6fd-48ca-9225-6a4043de2518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302954149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1302954149
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.543928546
Short name T131
Test name
Test status
Simulation time 156582044 ps
CPU time 2.96 seconds
Started Aug 07 05:45:55 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 200240 kb
Host smart-bcedc821-3b60-4bd7-9cb7-51d4e4112f65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543928546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.543928546
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3266088239
Short name T605
Test name
Test status
Simulation time 128163398 ps
CPU time 1.66 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 200036 kb
Host smart-b9dd13b9-aeb1-4480-813f-c9d8d0da8a09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266088239 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3266088239
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2951508286
Short name T568
Test name
Test status
Simulation time 36047376 ps
CPU time 0.75 seconds
Started Aug 07 05:45:53 PM PDT 24
Finished Aug 07 05:45:54 PM PDT 24
Peak memory 198280 kb
Host smart-c8404b96-a6e6-41b5-a992-870015e1eabb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951508286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2951508286
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2414555476
Short name T653
Test name
Test status
Simulation time 41079342 ps
CPU time 0.58 seconds
Started Aug 07 05:45:57 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 195092 kb
Host smart-0f04e73c-6e7f-4114-9f61-ef35a1c1c2ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414555476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2414555476
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.398030951
Short name T616
Test name
Test status
Simulation time 865457530 ps
CPU time 1.84 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 199976 kb
Host smart-3f313e1f-314e-49bc-8ce9-13c53e603d5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398030951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.398030951
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1275731265
Short name T544
Test name
Test status
Simulation time 136027394 ps
CPU time 1.51 seconds
Started Aug 07 05:45:52 PM PDT 24
Finished Aug 07 05:45:54 PM PDT 24
Peak memory 200072 kb
Host smart-5141edba-a586-4ce2-9925-f0a4cd2e925c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275731265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1275731265
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1238561111
Short name T596
Test name
Test status
Simulation time 431875497 ps
CPU time 5.13 seconds
Started Aug 07 05:45:22 PM PDT 24
Finished Aug 07 05:45:27 PM PDT 24
Peak memory 200096 kb
Host smart-d106710b-3887-42a5-9df2-e2a897b489a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238561111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1238561111
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3871334583
Short name T576
Test name
Test status
Simulation time 110257547 ps
CPU time 4.95 seconds
Started Aug 07 05:45:25 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 200112 kb
Host smart-349e4e20-c494-4986-ae5d-d0537fdceb9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871334583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3871334583
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3508104996
Short name T552
Test name
Test status
Simulation time 26092915 ps
CPU time 0.7 seconds
Started Aug 07 05:45:29 PM PDT 24
Finished Aug 07 05:45:29 PM PDT 24
Peak memory 197840 kb
Host smart-0e0158bc-4905-4a13-8d58-86bc80b27412
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508104996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3508104996
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.645705032
Short name T551
Test name
Test status
Simulation time 36931693 ps
CPU time 2.26 seconds
Started Aug 07 05:45:25 PM PDT 24
Finished Aug 07 05:45:27 PM PDT 24
Peak memory 208428 kb
Host smart-477020c4-c979-487f-9297-9753c3510f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645705032 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.645705032
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.488107138
Short name T117
Test name
Test status
Simulation time 53317440 ps
CPU time 0.67 seconds
Started Aug 07 05:45:30 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 197812 kb
Host smart-6d95eb1e-d645-47fd-9574-ad49a6c9b3ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488107138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.488107138
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2847020224
Short name T564
Test name
Test status
Simulation time 23125089 ps
CPU time 0.6 seconds
Started Aug 07 05:45:29 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 195132 kb
Host smart-da8f3da5-832d-422a-b6b0-88360e74a773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847020224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2847020224
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3107260560
Short name T116
Test name
Test status
Simulation time 349079147 ps
CPU time 1.81 seconds
Started Aug 07 05:45:24 PM PDT 24
Finished Aug 07 05:45:26 PM PDT 24
Peak memory 199984 kb
Host smart-1262c836-34ce-413a-abd3-27ace0e7ffc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107260560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3107260560
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1029602703
Short name T638
Test name
Test status
Simulation time 211209553 ps
CPU time 3.7 seconds
Started Aug 07 05:45:25 PM PDT 24
Finished Aug 07 05:45:29 PM PDT 24
Peak memory 200224 kb
Host smart-cc1c889d-bdaf-4adb-9ca9-348afc203adb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029602703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1029602703
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1630396129
Short name T125
Test name
Test status
Simulation time 765531838 ps
CPU time 3.24 seconds
Started Aug 07 05:45:27 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 200064 kb
Host smart-4bb3156f-7a1b-4b0e-a0c1-d2f07929cb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630396129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1630396129
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.86518243
Short name T563
Test name
Test status
Simulation time 48225721 ps
CPU time 0.6 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:56 PM PDT 24
Peak memory 194960 kb
Host smart-b8c91145-5b6e-458b-ad40-28c7fe802f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86518243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.86518243
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3743503799
Short name T531
Test name
Test status
Simulation time 19044572 ps
CPU time 0.57 seconds
Started Aug 07 05:46:03 PM PDT 24
Finished Aug 07 05:46:03 PM PDT 24
Peak memory 195016 kb
Host smart-5e7b68bd-e47d-463d-a21d-3036486dedd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743503799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3743503799
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2951299226
Short name T588
Test name
Test status
Simulation time 17048070 ps
CPU time 0.61 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 194992 kb
Host smart-0c378d74-42e0-419b-979e-5cc5d413cac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951299226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2951299226
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3449392785
Short name T611
Test name
Test status
Simulation time 15168552 ps
CPU time 0.61 seconds
Started Aug 07 05:45:58 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 194948 kb
Host smart-3cacb5d1-ea37-4eb9-a9f9-dd34756fef89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449392785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3449392785
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1140953491
Short name T550
Test name
Test status
Simulation time 41524081 ps
CPU time 0.6 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:00 PM PDT 24
Peak memory 195164 kb
Host smart-8dbb3ca2-8e7c-4e22-bff8-d6906195ff45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140953491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1140953491
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1567942641
Short name T559
Test name
Test status
Simulation time 36058153 ps
CPU time 0.58 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:00 PM PDT 24
Peak memory 194960 kb
Host smart-d163f60d-23f0-42a5-a92b-88994f556665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567942641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1567942641
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.803368321
Short name T612
Test name
Test status
Simulation time 47248909 ps
CPU time 0.6 seconds
Started Aug 07 05:45:58 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 195076 kb
Host smart-870d2011-760f-4606-a957-819da756efc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803368321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.803368321
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.143790025
Short name T574
Test name
Test status
Simulation time 31904813 ps
CPU time 0.61 seconds
Started Aug 07 05:46:02 PM PDT 24
Finished Aug 07 05:46:03 PM PDT 24
Peak memory 195212 kb
Host smart-92963634-11cc-4305-ae70-888fe6eac702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143790025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.143790025
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2062744595
Short name T620
Test name
Test status
Simulation time 55588754 ps
CPU time 0.63 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:57 PM PDT 24
Peak memory 194952 kb
Host smart-06d27829-9a31-42d1-8f18-58442c662759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062744595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2062744595
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.71271918
Short name T580
Test name
Test status
Simulation time 18628401 ps
CPU time 0.57 seconds
Started Aug 07 05:45:58 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 194960 kb
Host smart-ed8bdc97-429d-4562-ad5b-d41eef141cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.71271918
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3773902562
Short name T594
Test name
Test status
Simulation time 214239332 ps
CPU time 5.3 seconds
Started Aug 07 05:45:30 PM PDT 24
Finished Aug 07 05:45:35 PM PDT 24
Peak memory 199920 kb
Host smart-6f79a9fa-6d12-4d9f-a81c-112c6e262389
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773902562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3773902562
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3820493141
Short name T105
Test name
Test status
Simulation time 235915625 ps
CPU time 5.12 seconds
Started Aug 07 05:45:30 PM PDT 24
Finished Aug 07 05:45:35 PM PDT 24
Peak memory 198680 kb
Host smart-3c846f96-03f6-409a-a873-4aa61bc26789
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820493141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3820493141
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2453315682
Short name T548
Test name
Test status
Simulation time 19688983 ps
CPU time 0.99 seconds
Started Aug 07 05:45:23 PM PDT 24
Finished Aug 07 05:45:24 PM PDT 24
Peak memory 199940 kb
Host smart-ff56699b-b880-4e71-93bb-ea6c81db6e77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453315682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2453315682
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1206692865
Short name T555
Test name
Test status
Simulation time 172242612 ps
CPU time 2.89 seconds
Started Aug 07 05:45:35 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 200272 kb
Host smart-c7c0431f-6e02-4dcf-9702-739ec06b81bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206692865 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1206692865
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1502133641
Short name T599
Test name
Test status
Simulation time 107203682 ps
CPU time 0.94 seconds
Started Aug 07 05:45:25 PM PDT 24
Finished Aug 07 05:45:26 PM PDT 24
Peak memory 199948 kb
Host smart-0789b2ba-6e78-4757-9d70-dc8fd6279c31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502133641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1502133641
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2135394876
Short name T654
Test name
Test status
Simulation time 14361766 ps
CPU time 0.64 seconds
Started Aug 07 05:45:28 PM PDT 24
Finished Aug 07 05:45:29 PM PDT 24
Peak memory 195060 kb
Host smart-67983c2f-9c6f-408a-990e-0c0df76f55da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135394876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2135394876
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1659051882
Short name T632
Test name
Test status
Simulation time 58886918 ps
CPU time 1.55 seconds
Started Aug 07 05:45:31 PM PDT 24
Finished Aug 07 05:45:33 PM PDT 24
Peak memory 200108 kb
Host smart-a1211fef-19d4-4ea9-85dc-7103e90c9e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659051882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1659051882
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3229604610
Short name T631
Test name
Test status
Simulation time 258417405 ps
CPU time 3.39 seconds
Started Aug 07 05:45:31 PM PDT 24
Finished Aug 07 05:45:34 PM PDT 24
Peak memory 200112 kb
Host smart-e7cc5f39-f951-4484-b217-93f2dea416f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229604610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3229604610
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2130354056
Short name T132
Test name
Test status
Simulation time 1621606517 ps
CPU time 3.09 seconds
Started Aug 07 05:45:24 PM PDT 24
Finished Aug 07 05:45:28 PM PDT 24
Peak memory 200040 kb
Host smart-a15e60f8-c06c-4179-815c-44cc4ec68281
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130354056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2130354056
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1146844091
Short name T530
Test name
Test status
Simulation time 172217060 ps
CPU time 0.6 seconds
Started Aug 07 05:45:56 PM PDT 24
Finished Aug 07 05:45:57 PM PDT 24
Peak memory 194960 kb
Host smart-58b7a74c-8458-4f52-8a9e-f54bce7e69d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146844091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1146844091
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.545431997
Short name T562
Test name
Test status
Simulation time 43072231 ps
CPU time 0.6 seconds
Started Aug 07 05:45:58 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 195064 kb
Host smart-240b1aaa-a5a2-4cbe-af1d-7fcc64d68621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545431997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.545431997
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1121445072
Short name T637
Test name
Test status
Simulation time 36921641 ps
CPU time 0.58 seconds
Started Aug 07 05:45:59 PM PDT 24
Finished Aug 07 05:46:00 PM PDT 24
Peak memory 194972 kb
Host smart-8b1dd019-da09-4416-8020-ee317cd70cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121445072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1121445072
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1811840984
Short name T547
Test name
Test status
Simulation time 42379007 ps
CPU time 0.58 seconds
Started Aug 07 05:45:57 PM PDT 24
Finished Aug 07 05:45:57 PM PDT 24
Peak memory 194932 kb
Host smart-d8630879-1dc5-4a0b-8a57-a9f9948c2c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811840984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1811840984
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3097226717
Short name T536
Test name
Test status
Simulation time 125518854 ps
CPU time 0.64 seconds
Started Aug 07 05:46:00 PM PDT 24
Finished Aug 07 05:46:01 PM PDT 24
Peak memory 195160 kb
Host smart-f854cd41-9580-4fb6-b0d7-29ef8772eeb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097226717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3097226717
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.227174277
Short name T587
Test name
Test status
Simulation time 27856538 ps
CPU time 0.58 seconds
Started Aug 07 05:45:58 PM PDT 24
Finished Aug 07 05:45:59 PM PDT 24
Peak memory 195064 kb
Host smart-a13ac743-da09-4d80-9b8f-2537563a170b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227174277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.227174277
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3325054588
Short name T570
Test name
Test status
Simulation time 11969190 ps
CPU time 0.62 seconds
Started Aug 07 05:45:57 PM PDT 24
Finished Aug 07 05:45:58 PM PDT 24
Peak memory 194968 kb
Host smart-092a0401-880c-4983-bd1f-2d8d4f0a1444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325054588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3325054588
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2361828168
Short name T553
Test name
Test status
Simulation time 19911903 ps
CPU time 0.64 seconds
Started Aug 07 05:46:03 PM PDT 24
Finished Aug 07 05:46:04 PM PDT 24
Peak memory 195020 kb
Host smart-c6c80d95-294f-4aa0-9e65-b17aedec2d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361828168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2361828168
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1552141461
Short name T566
Test name
Test status
Simulation time 115109352 ps
CPU time 0.6 seconds
Started Aug 07 05:46:04 PM PDT 24
Finished Aug 07 05:46:05 PM PDT 24
Peak memory 195112 kb
Host smart-cffab517-93e1-489f-a4d4-40162f5861e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552141461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1552141461
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1252785990
Short name T649
Test name
Test status
Simulation time 31050786 ps
CPU time 0.61 seconds
Started Aug 07 05:46:09 PM PDT 24
Finished Aug 07 05:46:09 PM PDT 24
Peak memory 194968 kb
Host smart-4159da65-064b-49f2-86b8-dd019458a750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252785990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1252785990
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3159222131
Short name T102
Test name
Test status
Simulation time 628987851 ps
CPU time 3.37 seconds
Started Aug 07 05:45:32 PM PDT 24
Finished Aug 07 05:45:35 PM PDT 24
Peak memory 200048 kb
Host smart-4e213a35-c6d8-4be7-a0ee-7a430b0ae60a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159222131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3159222131
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.638018650
Short name T109
Test name
Test status
Simulation time 5210961227 ps
CPU time 14.95 seconds
Started Aug 07 05:45:34 PM PDT 24
Finished Aug 07 05:45:49 PM PDT 24
Peak memory 200140 kb
Host smart-65df4e87-b1b6-4a35-bc44-81a9b72d4ea1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638018650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.638018650
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1335998206
Short name T556
Test name
Test status
Simulation time 99956806 ps
CPU time 0.87 seconds
Started Aug 07 05:45:32 PM PDT 24
Finished Aug 07 05:45:33 PM PDT 24
Peak memory 199672 kb
Host smart-53466aec-16ec-455b-967d-6cc3920544be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335998206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1335998206
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3968723765
Short name T560
Test name
Test status
Simulation time 256725205 ps
CPU time 1.58 seconds
Started Aug 07 05:45:38 PM PDT 24
Finished Aug 07 05:45:39 PM PDT 24
Peak memory 200140 kb
Host smart-32fa1ebe-9dc4-4898-ad8c-36578e8abcb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968723765 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3968723765
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3419815665
Short name T112
Test name
Test status
Simulation time 53157833 ps
CPU time 0.88 seconds
Started Aug 07 05:45:29 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 199584 kb
Host smart-15547cc3-a22c-4ebc-a027-e0b89ef179ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419815665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3419815665
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3657117920
Short name T565
Test name
Test status
Simulation time 13220620 ps
CPU time 0.57 seconds
Started Aug 07 05:45:32 PM PDT 24
Finished Aug 07 05:45:33 PM PDT 24
Peak memory 195020 kb
Host smart-655ed03e-19a3-422a-895b-9d083f2e8524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657117920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3657117920
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3925656697
Short name T615
Test name
Test status
Simulation time 383129724 ps
CPU time 1.83 seconds
Started Aug 07 05:45:34 PM PDT 24
Finished Aug 07 05:45:36 PM PDT 24
Peak memory 200236 kb
Host smart-82d516df-742e-44dc-beea-5cb73d2c850c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925656697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3925656697
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3807033912
Short name T593
Test name
Test status
Simulation time 88641133 ps
CPU time 1.23 seconds
Started Aug 07 05:45:29 PM PDT 24
Finished Aug 07 05:45:30 PM PDT 24
Peak memory 200064 kb
Host smart-4214167c-5764-4b43-b2ad-4a3829cc8098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807033912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3807033912
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2163591946
Short name T129
Test name
Test status
Simulation time 464515879 ps
CPU time 3.89 seconds
Started Aug 07 05:45:33 PM PDT 24
Finished Aug 07 05:45:37 PM PDT 24
Peak memory 200232 kb
Host smart-b69fef36-d4dd-48d9-96ff-2acc887a9a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163591946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2163591946
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1384961523
Short name T573
Test name
Test status
Simulation time 12408254 ps
CPU time 0.62 seconds
Started Aug 07 05:46:02 PM PDT 24
Finished Aug 07 05:46:02 PM PDT 24
Peak memory 195004 kb
Host smart-25b4abe5-0fc2-4056-90c1-9f09749f2959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384961523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1384961523
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2731273360
Short name T621
Test name
Test status
Simulation time 17882396 ps
CPU time 0.67 seconds
Started Aug 07 05:46:04 PM PDT 24
Finished Aug 07 05:46:04 PM PDT 24
Peak memory 195192 kb
Host smart-d21cbfc8-0fb5-4572-8dae-7d3b44015139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731273360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2731273360
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2044754262
Short name T581
Test name
Test status
Simulation time 25152001 ps
CPU time 0.63 seconds
Started Aug 07 05:46:05 PM PDT 24
Finished Aug 07 05:46:06 PM PDT 24
Peak memory 194928 kb
Host smart-b2e35bb9-8c0e-43ff-b6f6-e0e8d20286b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044754262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2044754262
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1675618058
Short name T554
Test name
Test status
Simulation time 22593919 ps
CPU time 0.58 seconds
Started Aug 07 05:46:02 PM PDT 24
Finished Aug 07 05:46:03 PM PDT 24
Peak memory 194996 kb
Host smart-84eec92f-de9e-4803-8c87-f0126aec3a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675618058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1675618058
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3826211213
Short name T634
Test name
Test status
Simulation time 11517826 ps
CPU time 0.58 seconds
Started Aug 07 05:46:03 PM PDT 24
Finished Aug 07 05:46:04 PM PDT 24
Peak memory 195032 kb
Host smart-c6c707cd-c44f-46fe-a2ff-0ff58fac3a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826211213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3826211213
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4155294183
Short name T532
Test name
Test status
Simulation time 58440001 ps
CPU time 0.61 seconds
Started Aug 07 05:46:01 PM PDT 24
Finished Aug 07 05:46:02 PM PDT 24
Peak memory 195004 kb
Host smart-7b6a9b6c-9ef9-489d-bf8f-cea1f4296320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155294183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4155294183
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2737002955
Short name T606
Test name
Test status
Simulation time 118936490 ps
CPU time 0.62 seconds
Started Aug 07 05:46:09 PM PDT 24
Finished Aug 07 05:46:09 PM PDT 24
Peak memory 195060 kb
Host smart-0a63d91b-d388-43ef-92a3-2f72883fe8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737002955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2737002955
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2625568527
Short name T629
Test name
Test status
Simulation time 24197475 ps
CPU time 0.65 seconds
Started Aug 07 05:46:02 PM PDT 24
Finished Aug 07 05:46:03 PM PDT 24
Peak memory 195060 kb
Host smart-db57541a-5056-44d1-8220-6749229ddbf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625568527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2625568527
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1211429307
Short name T624
Test name
Test status
Simulation time 132584260 ps
CPU time 0.58 seconds
Started Aug 07 05:46:05 PM PDT 24
Finished Aug 07 05:46:06 PM PDT 24
Peak memory 195040 kb
Host smart-5d2dc860-f37d-465d-98a0-fa8d1a9ca51a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211429307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1211429307
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.967680019
Short name T623
Test name
Test status
Simulation time 61088084 ps
CPU time 0.62 seconds
Started Aug 07 05:46:04 PM PDT 24
Finished Aug 07 05:46:05 PM PDT 24
Peak memory 195416 kb
Host smart-99ff0ae7-61c9-4ee8-b0db-2769402d1b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967680019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.967680019
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.195843770
Short name T528
Test name
Test status
Simulation time 272480475 ps
CPU time 1.77 seconds
Started Aug 07 05:45:30 PM PDT 24
Finished Aug 07 05:45:32 PM PDT 24
Peak memory 200068 kb
Host smart-3faa5f12-7bb6-45c1-b0d6-af8baded457d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195843770 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.195843770
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.297817975
Short name T108
Test name
Test status
Simulation time 15258421 ps
CPU time 0.79 seconds
Started Aug 07 05:45:34 PM PDT 24
Finished Aug 07 05:45:35 PM PDT 24
Peak memory 199904 kb
Host smart-0ee20552-1ae1-44b7-8a04-d22244530b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297817975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.297817975
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.70105798
Short name T533
Test name
Test status
Simulation time 14799566 ps
CPU time 0.59 seconds
Started Aug 07 05:45:31 PM PDT 24
Finished Aug 07 05:45:31 PM PDT 24
Peak memory 195024 kb
Host smart-b4020dea-ffec-497f-b4a5-0d3ea1077867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70105798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.70105798
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4102190836
Short name T577
Test name
Test status
Simulation time 216418080 ps
CPU time 1.18 seconds
Started Aug 07 05:45:30 PM PDT 24
Finished Aug 07 05:45:31 PM PDT 24
Peak memory 200172 kb
Host smart-2eef37b1-2198-4215-829a-00b1cf32b9a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102190836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4102190836
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.173980379
Short name T541
Test name
Test status
Simulation time 49096546 ps
CPU time 2.44 seconds
Started Aug 07 05:45:31 PM PDT 24
Finished Aug 07 05:45:33 PM PDT 24
Peak memory 200048 kb
Host smart-f1b624f8-24aa-4c79-a58f-70bfae080997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173980379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.173980379
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.833726646
Short name T127
Test name
Test status
Simulation time 774692750 ps
CPU time 3.24 seconds
Started Aug 07 05:45:34 PM PDT 24
Finished Aug 07 05:45:37 PM PDT 24
Peak memory 200208 kb
Host smart-a07e001b-e0d8-4fed-a4a0-aab31544481f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833726646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.833726646
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3824944199
Short name T639
Test name
Test status
Simulation time 865701685 ps
CPU time 2.51 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:46:39 PM PDT 24
Peak memory 200200 kb
Host smart-8c5b4bab-5fec-4c90-adff-95e8ae85c7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824944199 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3824944199
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3349844577
Short name T601
Test name
Test status
Simulation time 41727879 ps
CPU time 0.81 seconds
Started Aug 07 05:45:41 PM PDT 24
Finished Aug 07 05:45:42 PM PDT 24
Peak memory 199508 kb
Host smart-b3739b62-554d-4292-86ef-386375035b69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349844577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3349844577
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3209258405
Short name T656
Test name
Test status
Simulation time 64649173 ps
CPU time 0.61 seconds
Started Aug 07 05:45:35 PM PDT 24
Finished Aug 07 05:45:36 PM PDT 24
Peak memory 194996 kb
Host smart-f5e7475b-a69d-41e4-a6a4-188d0f7e14a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209258405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3209258405
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1561988709
Short name T578
Test name
Test status
Simulation time 530872720 ps
CPU time 2.28 seconds
Started Aug 07 05:45:38 PM PDT 24
Finished Aug 07 05:45:41 PM PDT 24
Peak memory 200080 kb
Host smart-f6da9580-bec2-4648-8c46-66ff54883c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561988709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1561988709
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.604406621
Short name T645
Test name
Test status
Simulation time 456276414 ps
CPU time 1.73 seconds
Started Aug 07 05:45:33 PM PDT 24
Finished Aug 07 05:45:35 PM PDT 24
Peak memory 200072 kb
Host smart-bb350ef2-dd6e-4434-8bb2-dd9ad95bbace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604406621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.604406621
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3125313399
Short name T126
Test name
Test status
Simulation time 1559651245 ps
CPU time 4.14 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:47 PM PDT 24
Peak memory 200024 kb
Host smart-50e27812-9add-4aee-9daa-d4f4e9427c12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125313399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3125313399
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3450382863
Short name T543
Test name
Test status
Simulation time 209411898 ps
CPU time 2.21 seconds
Started Aug 07 05:45:40 PM PDT 24
Finished Aug 07 05:45:42 PM PDT 24
Peak memory 200216 kb
Host smart-0b742b92-c807-43d7-9c94-586f9fc4a8e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450382863 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3450382863
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1914573662
Short name T628
Test name
Test status
Simulation time 21643427 ps
CPU time 0.72 seconds
Started Aug 07 05:45:40 PM PDT 24
Finished Aug 07 05:45:41 PM PDT 24
Peak memory 197848 kb
Host smart-aa54fc7e-913c-4c87-9751-7843e5f4c57f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914573662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1914573662
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2681248846
Short name T542
Test name
Test status
Simulation time 17291143 ps
CPU time 0.63 seconds
Started Aug 07 05:45:36 PM PDT 24
Finished Aug 07 05:45:37 PM PDT 24
Peak memory 195100 kb
Host smart-9e85eb23-042c-4d53-b9d2-02ed26d103a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681248846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2681248846
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.613614274
Short name T622
Test name
Test status
Simulation time 101996129 ps
CPU time 2 seconds
Started Aug 07 05:45:37 PM PDT 24
Finished Aug 07 05:45:39 PM PDT 24
Peak memory 200176 kb
Host smart-30e929b2-9cb7-4200-beba-ef3cff90e3ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613614274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.613614274
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1267425490
Short name T526
Test name
Test status
Simulation time 115176757 ps
CPU time 1.67 seconds
Started Aug 07 05:45:36 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 200108 kb
Host smart-4275aa8d-7740-440d-96cb-5a4dfc6e2bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267425490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1267425490
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.952746951
Short name T75
Test name
Test status
Simulation time 216191651 ps
CPU time 3.02 seconds
Started Aug 07 05:45:40 PM PDT 24
Finished Aug 07 05:45:44 PM PDT 24
Peak memory 200076 kb
Host smart-adea0d60-7e5d-4288-80cf-980daa1af7cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952746951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.952746951
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1780140411
Short name T647
Test name
Test status
Simulation time 327720287 ps
CPU time 2.24 seconds
Started Aug 07 05:45:40 PM PDT 24
Finished Aug 07 05:45:43 PM PDT 24
Peak memory 200200 kb
Host smart-316e0105-bda3-4ecb-94a0-2174d1b63d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780140411 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1780140411
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.73106548
Short name T110
Test name
Test status
Simulation time 25763549 ps
CPU time 0.8 seconds
Started Aug 07 05:45:38 PM PDT 24
Finished Aug 07 05:45:39 PM PDT 24
Peak memory 199304 kb
Host smart-c56f67b7-04f4-45b9-b146-13a8f4729ac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73106548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.73106548
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3806156665
Short name T529
Test name
Test status
Simulation time 55566326 ps
CPU time 0.59 seconds
Started Aug 07 05:45:37 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 195024 kb
Host smart-5ee93840-f53d-43c5-8c75-9a4a41451117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806156665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3806156665
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2382261383
Short name T118
Test name
Test status
Simulation time 83692039 ps
CPU time 1.82 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:45 PM PDT 24
Peak memory 200064 kb
Host smart-b41e1a26-daa7-481b-bc9c-9e475ef9cef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382261383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2382261383
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.818652045
Short name T610
Test name
Test status
Simulation time 352349523 ps
CPU time 3.42 seconds
Started Aug 07 05:45:38 PM PDT 24
Finished Aug 07 05:45:41 PM PDT 24
Peak memory 200060 kb
Host smart-83b56921-5b57-4abd-8e24-c55200f84c79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818652045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.818652045
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3923145031
Short name T73
Test name
Test status
Simulation time 349554820 ps
CPU time 4.58 seconds
Started Aug 07 05:45:37 PM PDT 24
Finished Aug 07 05:45:42 PM PDT 24
Peak memory 200100 kb
Host smart-884edfdb-9de4-48f1-bb62-d7f2a8787871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923145031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3923145031
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3317594385
Short name T590
Test name
Test status
Simulation time 153065853 ps
CPU time 3.13 seconds
Started Aug 07 05:45:42 PM PDT 24
Finished Aug 07 05:45:45 PM PDT 24
Peak memory 208296 kb
Host smart-0428ae82-b139-432b-8c39-297a3496a596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317594385 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3317594385
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4220612531
Short name T557
Test name
Test status
Simulation time 30042704 ps
CPU time 0.97 seconds
Started Aug 07 05:45:37 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 199940 kb
Host smart-558c0679-c1de-48b2-94b9-3c039685d14b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220612531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4220612531
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.452957566
Short name T642
Test name
Test status
Simulation time 35330169 ps
CPU time 0.55 seconds
Started Aug 07 05:45:37 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 194880 kb
Host smart-d3449b03-edfb-4c87-b541-32982dbf46fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452957566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.452957566
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.258356973
Short name T626
Test name
Test status
Simulation time 340999344 ps
CPU time 1.19 seconds
Started Aug 07 05:45:37 PM PDT 24
Finished Aug 07 05:45:38 PM PDT 24
Peak memory 198464 kb
Host smart-daaba182-e2bd-4cae-9223-68bafc07e33e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258356973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.258356973
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1420046538
Short name T571
Test name
Test status
Simulation time 3508657131 ps
CPU time 3.4 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:46 PM PDT 24
Peak memory 200164 kb
Host smart-70beb8eb-3da3-439e-b790-980b204c0219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420046538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1420046538
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.423406046
Short name T582
Test name
Test status
Simulation time 383489635 ps
CPU time 1.86 seconds
Started Aug 07 05:45:43 PM PDT 24
Finished Aug 07 05:45:45 PM PDT 24
Peak memory 200032 kb
Host smart-ec9c8da9-5e11-4927-b697-d053692787c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423406046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.423406046
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2489222835
Short name T19
Test name
Test status
Simulation time 3711563983 ps
CPU time 97.4 seconds
Started Aug 07 05:46:20 PM PDT 24
Finished Aug 07 05:47:58 PM PDT 24
Peak memory 199872 kb
Host smart-85895b13-7881-4865-8cad-0942ab77b2e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489222835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2489222835
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2346993822
Short name T508
Test name
Test status
Simulation time 31340404051 ps
CPU time 69.33 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 05:47:32 PM PDT 24
Peak memory 208008 kb
Host smart-3421fad7-e6e7-4d8b-b87f-df5b35f9e256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346993822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2346993822
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.841098084
Short name T183
Test name
Test status
Simulation time 1258960980 ps
CPU time 71.89 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 05:47:33 PM PDT 24
Peak memory 364140 kb
Host smart-5aad2a1b-9d68-4753-b89f-dca652fe85b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841098084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.841098084
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4055489022
Short name T227
Test name
Test status
Simulation time 4278343166 ps
CPU time 59.17 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:47:26 PM PDT 24
Peak memory 199872 kb
Host smart-13a7f1ba-331f-4976-a5e1-e8f371201854
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055489022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4055489022
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1081274601
Short name T377
Test name
Test status
Simulation time 30261315753 ps
CPU time 149.12 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 05:48:50 PM PDT 24
Peak memory 199836 kb
Host smart-bf07ed49-ccd6-454a-9a16-2319a4257662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081274601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1081274601
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2239681682
Short name T63
Test name
Test status
Simulation time 202048489 ps
CPU time 0.87 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 05:46:24 PM PDT 24
Peak memory 218316 kb
Host smart-28f58183-fd24-4e2c-84d9-f31a759d6733
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239681682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2239681682
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1684911523
Short name T431
Test name
Test status
Simulation time 314018091 ps
CPU time 13.32 seconds
Started Aug 07 05:46:17 PM PDT 24
Finished Aug 07 05:46:30 PM PDT 24
Peak memory 199796 kb
Host smart-37e03b31-9986-4339-b3c5-85e32ab2df8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684911523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1684911523
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3824203693
Short name T38
Test name
Test status
Simulation time 40612070004 ps
CPU time 1077.12 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 06:04:19 PM PDT 24
Peak memory 652556 kb
Host smart-29ddb822-e312-4cc0-9497-8d46efa8ec5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824203693 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3824203693
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.792015356
Short name T79
Test name
Test status
Simulation time 29526786634 ps
CPU time 959.4 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 06:02:23 PM PDT 24
Peak memory 686204 kb
Host smart-794c2b15-e57e-46e4-a52b-56c52bf377dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792015356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.792015356
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3087595120
Short name T386
Test name
Test status
Simulation time 2676220383 ps
CPU time 40.32 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 05:47:02 PM PDT 24
Peak memory 199860 kb
Host smart-791bb123-baa5-4336-af73-7acc812b25b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3087595120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3087595120
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1709485259
Short name T3
Test name
Test status
Simulation time 8536017249 ps
CPU time 66.31 seconds
Started Aug 07 05:46:25 PM PDT 24
Finished Aug 07 05:47:31 PM PDT 24
Peak memory 199944 kb
Host smart-03362001-63dc-4cc4-be9c-9987b5765495
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1709485259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1709485259
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2959261042
Short name T15
Test name
Test status
Simulation time 21940566097 ps
CPU time 113.49 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 05:48:16 PM PDT 24
Peak memory 199820 kb
Host smart-76b5d299-4765-408b-9a11-af2d2b8909b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2959261042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2959261042
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1105942322
Short name T293
Test name
Test status
Simulation time 50562776825 ps
CPU time 631.6 seconds
Started Aug 07 05:46:25 PM PDT 24
Finished Aug 07 05:56:57 PM PDT 24
Peak memory 199868 kb
Host smart-54618b05-0ffb-40da-bcfe-497095c7e23e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1105942322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1105942322
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.672660705
Short name T68
Test name
Test status
Simulation time 917255233501 ps
CPU time 2776.37 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 06:32:38 PM PDT 24
Peak memory 216248 kb
Host smart-dbca20c1-aea8-4813-a990-9dc28a47e65b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=672660705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.672660705
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1556110335
Short name T264
Test name
Test status
Simulation time 786604668232 ps
CPU time 2625.15 seconds
Started Aug 07 05:46:19 PM PDT 24
Finished Aug 07 06:30:04 PM PDT 24
Peak memory 215224 kb
Host smart-ec125f74-b778-4796-a17a-146647a6a4bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1556110335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1556110335
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4234490251
Short name T243
Test name
Test status
Simulation time 11954751670 ps
CPU time 156.24 seconds
Started Aug 07 05:46:25 PM PDT 24
Finished Aug 07 05:49:01 PM PDT 24
Peak memory 199888 kb
Host smart-f376aee6-a898-461d-88ea-3cca1d82ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234490251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4234490251
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2974726595
Short name T381
Test name
Test status
Simulation time 61551554 ps
CPU time 0.61 seconds
Started Aug 07 05:46:20 PM PDT 24
Finished Aug 07 05:46:21 PM PDT 24
Peak memory 195800 kb
Host smart-4eba40e9-9056-472d-89ff-4d190e62cf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974726595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2974726595
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3719405002
Short name T209
Test name
Test status
Simulation time 1355428488 ps
CPU time 80.49 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 05:47:43 PM PDT 24
Peak memory 199708 kb
Host smart-9c39101c-3319-436f-a813-a149cd055a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719405002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3719405002
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.64772921
Short name T422
Test name
Test status
Simulation time 9414145547 ps
CPU time 78.88 seconds
Started Aug 07 05:46:24 PM PDT 24
Finished Aug 07 05:47:43 PM PDT 24
Peak memory 199932 kb
Host smart-4402f4d1-9fe4-46c7-a283-031a2b355f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64772921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.64772921
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2664113429
Short name T304
Test name
Test status
Simulation time 3694506520 ps
CPU time 326.73 seconds
Started Aug 07 05:46:24 PM PDT 24
Finished Aug 07 05:51:51 PM PDT 24
Peak memory 695728 kb
Host smart-a3259058-5c32-404e-b69f-7a607b6f51da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664113429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2664113429
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3717022819
Short name T361
Test name
Test status
Simulation time 5196050060 ps
CPU time 95.64 seconds
Started Aug 07 05:46:24 PM PDT 24
Finished Aug 07 05:48:00 PM PDT 24
Peak memory 199904 kb
Host smart-72e1b708-9cb0-4a92-a13e-4033181164b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717022819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3717022819
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2028831504
Short name T219
Test name
Test status
Simulation time 53306808013 ps
CPU time 243.44 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 05:50:27 PM PDT 24
Peak memory 208128 kb
Host smart-575a7961-b115-4661-9bf8-bb45ccebccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028831504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2028831504
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2840789570
Short name T64
Test name
Test status
Simulation time 366345875 ps
CPU time 0.96 seconds
Started Aug 07 05:46:25 PM PDT 24
Finished Aug 07 05:46:26 PM PDT 24
Peak memory 219452 kb
Host smart-a8f8163d-766e-42de-b17c-ed2d1f088f85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840789570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2840789570
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1519103755
Short name T340
Test name
Test status
Simulation time 1208537607 ps
CPU time 7.52 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 05:46:29 PM PDT 24
Peak memory 199796 kb
Host smart-c0e36a4a-3974-409a-a9a0-6275c2f17be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519103755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1519103755
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1751090870
Short name T483
Test name
Test status
Simulation time 76591928538 ps
CPU time 1457.48 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 06:10:41 PM PDT 24
Peak memory 739284 kb
Host smart-bff07327-1232-4943-8564-cc9e38385aea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751090870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1751090870
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3773228570
Short name T168
Test name
Test status
Simulation time 15849001636 ps
CPU time 50.04 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 05:47:13 PM PDT 24
Peak memory 199788 kb
Host smart-9bb02228-56f4-40e5-a83c-d3603d1cc254
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3773228570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3773228570
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.777707445
Short name T67
Test name
Test status
Simulation time 7324985838 ps
CPU time 62.38 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 05:47:25 PM PDT 24
Peak memory 199840 kb
Host smart-10b24797-afd9-4d53-9e69-daadfc3f08b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=777707445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.777707445
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.473542861
Short name T335
Test name
Test status
Simulation time 16125875646 ps
CPU time 91.9 seconds
Started Aug 07 05:46:24 PM PDT 24
Finished Aug 07 05:47:56 PM PDT 24
Peak memory 199908 kb
Host smart-0e479a26-d322-4b62-ab56-6aca432c4ffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=473542861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.473542861
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.4095912076
Short name T290
Test name
Test status
Simulation time 109631356012 ps
CPU time 617.26 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 05:56:39 PM PDT 24
Peak memory 199816 kb
Host smart-0f2da928-6ade-4ece-b2a2-10b79453cbe3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4095912076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.4095912076
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1212031693
Short name T397
Test name
Test status
Simulation time 3314101109385 ps
CPU time 2453.83 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 06:27:17 PM PDT 24
Peak memory 215780 kb
Host smart-2e5ddb97-c2df-4f86-90d1-e406dc6789f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1212031693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1212031693
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3563566543
Short name T521
Test name
Test status
Simulation time 264001192912 ps
CPU time 2208.25 seconds
Started Aug 07 05:46:20 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 215484 kb
Host smart-1c89116f-dca0-4e42-b7d2-6a039442522c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3563566543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3563566543
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3586354292
Short name T196
Test name
Test status
Simulation time 3542121144 ps
CPU time 38 seconds
Started Aug 07 05:46:20 PM PDT 24
Finished Aug 07 05:46:59 PM PDT 24
Peak memory 199828 kb
Host smart-2fe43fb5-ca8a-49a6-84c5-c6ab6d6d33fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586354292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3586354292
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2847906495
Short name T308
Test name
Test status
Simulation time 11960523 ps
CPU time 0.58 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:46:49 PM PDT 24
Peak memory 195560 kb
Host smart-b9801029-a97d-4692-87b9-4cb0054a1f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847906495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2847906495
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.791323887
Short name T69
Test name
Test status
Simulation time 513667368 ps
CPU time 28.32 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:47:21 PM PDT 24
Peak memory 199752 kb
Host smart-e2f2b7c8-2dcd-41a9-9dbc-ba38527f0e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791323887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.791323887
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2624009599
Short name T493
Test name
Test status
Simulation time 3346528458 ps
CPU time 42.69 seconds
Started Aug 07 05:46:40 PM PDT 24
Finished Aug 07 05:47:23 PM PDT 24
Peak memory 199988 kb
Host smart-d8052c02-f9f0-49fd-9570-bf9918726f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624009599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2624009599
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.4267564700
Short name T53
Test name
Test status
Simulation time 685938669 ps
CPU time 22.93 seconds
Started Aug 07 05:46:40 PM PDT 24
Finished Aug 07 05:47:03 PM PDT 24
Peak memory 243992 kb
Host smart-9b4b8360-ff17-4311-a673-c33b1acb1512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267564700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.4267564700
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3831526161
Short name T184
Test name
Test status
Simulation time 968949414 ps
CPU time 12.29 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:46:48 PM PDT 24
Peak memory 199700 kb
Host smart-8a830023-ce85-4a64-915f-be7277552c89
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831526161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3831526161
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3308242326
Short name T239
Test name
Test status
Simulation time 3600194215 ps
CPU time 15.63 seconds
Started Aug 07 05:46:37 PM PDT 24
Finished Aug 07 05:46:53 PM PDT 24
Peak memory 199748 kb
Host smart-f4502a29-dfb0-484f-b1fa-403b141b28f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308242326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3308242326
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1774298339
Short name T345
Test name
Test status
Simulation time 555854031 ps
CPU time 9.15 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:46:44 PM PDT 24
Peak memory 199812 kb
Host smart-a2b12c1d-96f5-458a-9bb1-1a569992a7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774298339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1774298339
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3177406222
Short name T195
Test name
Test status
Simulation time 2451326780 ps
CPU time 88.2 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:48:20 PM PDT 24
Peak memory 199836 kb
Host smart-e3a71f3e-9bf0-4725-b29e-cab650e8108b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177406222 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3177406222
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1778086310
Short name T153
Test name
Test status
Simulation time 1608213629 ps
CPU time 77 seconds
Started Aug 07 05:46:34 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 199776 kb
Host smart-557db92d-e191-4dfe-b049-7bcf64e251ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778086310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1778086310
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2536999980
Short name T486
Test name
Test status
Simulation time 25633570 ps
CPU time 0.6 seconds
Started Aug 07 05:46:48 PM PDT 24
Finished Aug 07 05:46:48 PM PDT 24
Peak memory 195736 kb
Host smart-e7a2d24c-3a35-42da-aac0-fe8272ddd5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536999980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2536999980
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1646808607
Short name T336
Test name
Test status
Simulation time 2371087936 ps
CPU time 58.52 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:47:52 PM PDT 24
Peak memory 199816 kb
Host smart-78539000-8ce7-4031-bcee-9adcb2e6d6f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646808607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1646808607
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4168964858
Short name T469
Test name
Test status
Simulation time 245353704 ps
CPU time 12.82 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:47:08 PM PDT 24
Peak memory 199840 kb
Host smart-f5ed93b3-0d88-458b-8620-a7b57386d52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168964858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4168964858
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1787944103
Short name T504
Test name
Test status
Simulation time 7703267849 ps
CPU time 274.54 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:51:24 PM PDT 24
Peak memory 622196 kb
Host smart-30eac2be-da74-4d10-b6c8-50d5e4747e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787944103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1787944103
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2993880433
Short name T312
Test name
Test status
Simulation time 11770513064 ps
CPU time 182.57 seconds
Started Aug 07 05:46:48 PM PDT 24
Finished Aug 07 05:49:50 PM PDT 24
Peak memory 199792 kb
Host smart-5e21ae8c-80c3-4a7d-8d6f-c349a55a17a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993880433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2993880433
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2125650216
Short name T472
Test name
Test status
Simulation time 10706436411 ps
CPU time 177.36 seconds
Started Aug 07 05:46:46 PM PDT 24
Finished Aug 07 05:49:44 PM PDT 24
Peak memory 216472 kb
Host smart-85a6f4dd-5f5d-4896-b573-5cd2abb1995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125650216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2125650216
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.562499164
Short name T436
Test name
Test status
Simulation time 736080818 ps
CPU time 6.37 seconds
Started Aug 07 05:46:50 PM PDT 24
Finished Aug 07 05:46:57 PM PDT 24
Peak memory 199828 kb
Host smart-7e9a0c1d-81a3-4e5c-826b-eb192bb4f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562499164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.562499164
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2564885090
Short name T44
Test name
Test status
Simulation time 5685058529 ps
CPU time 34.48 seconds
Started Aug 07 05:46:41 PM PDT 24
Finished Aug 07 05:47:16 PM PDT 24
Peak memory 199852 kb
Host smart-0004ec63-a4bc-4bdd-a722-d0692fc7890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564885090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2564885090
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2059373185
Short name T375
Test name
Test status
Simulation time 14410738 ps
CPU time 0.58 seconds
Started Aug 07 05:46:42 PM PDT 24
Finished Aug 07 05:46:43 PM PDT 24
Peak memory 195632 kb
Host smart-c69fbbd8-cec4-456b-a3b7-42f888c8ce75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059373185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2059373185
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2768986759
Short name T146
Test name
Test status
Simulation time 250347223 ps
CPU time 14.56 seconds
Started Aug 07 05:46:47 PM PDT 24
Finished Aug 07 05:47:01 PM PDT 24
Peak memory 199860 kb
Host smart-34b9abc7-cc21-40d6-b03a-3884336fdf84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768986759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2768986759
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2175300647
Short name T50
Test name
Test status
Simulation time 4165243977 ps
CPU time 53.93 seconds
Started Aug 07 05:46:48 PM PDT 24
Finished Aug 07 05:47:42 PM PDT 24
Peak memory 199832 kb
Host smart-cc29f9e5-4240-41b0-be15-0534d94fd75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175300647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2175300647
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1859468925
Short name T273
Test name
Test status
Simulation time 72397484553 ps
CPU time 1254.22 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 06:07:45 PM PDT 24
Peak memory 691548 kb
Host smart-76a618ba-c44e-462e-a004-27a5d567696f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859468925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1859468925
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.903306925
Short name T296
Test name
Test status
Simulation time 4918523979 ps
CPU time 87.39 seconds
Started Aug 07 05:46:50 PM PDT 24
Finished Aug 07 05:48:18 PM PDT 24
Peak memory 199840 kb
Host smart-453b11f4-28bc-43be-aa39-defa1d24b782
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903306925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.903306925
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.98519316
Short name T270
Test name
Test status
Simulation time 22462961 ps
CPU time 0.62 seconds
Started Aug 07 05:46:42 PM PDT 24
Finished Aug 07 05:46:43 PM PDT 24
Peak memory 196264 kb
Host smart-03a6766b-b742-4323-8a69-eb77b7eb2972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98519316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.98519316
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2696198087
Short name T286
Test name
Test status
Simulation time 24636189 ps
CPU time 1.41 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:46:51 PM PDT 24
Peak memory 199652 kb
Host smart-15b09cb7-af18-4b83-9b5f-4efa6ad688e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696198087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2696198087
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1138955314
Short name T86
Test name
Test status
Simulation time 208433469779 ps
CPU time 4196.35 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 06:56:50 PM PDT 24
Peak memory 827684 kb
Host smart-de6183d6-8f69-4345-960e-2e5d81ba7a65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138955314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1138955314
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3232352161
Short name T205
Test name
Test status
Simulation time 8537891593 ps
CPU time 93.85 seconds
Started Aug 07 05:46:47 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 199844 kb
Host smart-78ea2211-d7af-410e-8b07-a2b73a403f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232352161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3232352161
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3134320882
Short name T305
Test name
Test status
Simulation time 13718011 ps
CPU time 0.59 seconds
Started Aug 07 05:46:47 PM PDT 24
Finished Aug 07 05:46:48 PM PDT 24
Peak memory 196108 kb
Host smart-540b030b-9fc9-419e-b362-615bcb29a12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134320882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3134320882
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2342103612
Short name T34
Test name
Test status
Simulation time 1151245276 ps
CPU time 65.42 seconds
Started Aug 07 05:46:47 PM PDT 24
Finished Aug 07 05:47:52 PM PDT 24
Peak memory 200028 kb
Host smart-e29807c7-3aac-458e-b878-c00e880311d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342103612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2342103612
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1597738813
Short name T234
Test name
Test status
Simulation time 1591578667 ps
CPU time 21.4 seconds
Started Aug 07 05:46:41 PM PDT 24
Finished Aug 07 05:47:03 PM PDT 24
Peak memory 199712 kb
Host smart-1351e99d-5fab-425f-a795-7db6a917ccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597738813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1597738813
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1499735586
Short name T204
Test name
Test status
Simulation time 19809701852 ps
CPU time 1001.97 seconds
Started Aug 07 05:46:38 PM PDT 24
Finished Aug 07 06:03:20 PM PDT 24
Peak memory 729848 kb
Host smart-0fe78a6c-404b-407e-8df8-87076d468d9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499735586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1499735586
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1063432314
Short name T297
Test name
Test status
Simulation time 7406526343 ps
CPU time 27.36 seconds
Started Aug 07 05:46:46 PM PDT 24
Finished Aug 07 05:47:14 PM PDT 24
Peak memory 199892 kb
Host smart-46e70cbb-d419-4ac6-a5e1-caec3c782de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063432314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1063432314
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3246180855
Short name T445
Test name
Test status
Simulation time 2380995761 ps
CPU time 30.73 seconds
Started Aug 07 05:46:39 PM PDT 24
Finished Aug 07 05:47:10 PM PDT 24
Peak memory 199880 kb
Host smart-52161cce-de6f-4b85-a74e-c979d5a2b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246180855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3246180855
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.959862649
Short name T45
Test name
Test status
Simulation time 635626582 ps
CPU time 13.84 seconds
Started Aug 07 05:46:43 PM PDT 24
Finished Aug 07 05:46:57 PM PDT 24
Peak memory 199804 kb
Host smart-13ee0b2d-f342-459d-ac1a-ba1a0482a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959862649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.959862649
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.555178233
Short name T417
Test name
Test status
Simulation time 12603656234 ps
CPU time 84.8 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:48:14 PM PDT 24
Peak memory 199848 kb
Host smart-93a3c596-e034-4887-a3d7-33d606d5e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555178233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.555178233
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4107579270
Short name T385
Test name
Test status
Simulation time 15764282 ps
CPU time 0.58 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:46:52 PM PDT 24
Peak memory 196536 kb
Host smart-fad70bf5-4b74-4478-bf84-c20ec57eeca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107579270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4107579270
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2438627241
Short name T359
Test name
Test status
Simulation time 2694654851 ps
CPU time 78.41 seconds
Started Aug 07 05:46:40 PM PDT 24
Finished Aug 07 05:47:59 PM PDT 24
Peak memory 199904 kb
Host smart-89e4cb5f-2064-4be5-a2ac-925a450c7abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438627241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2438627241
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4112937544
Short name T506
Test name
Test status
Simulation time 11459380894 ps
CPU time 57.84 seconds
Started Aug 07 05:46:42 PM PDT 24
Finished Aug 07 05:47:40 PM PDT 24
Peak memory 216232 kb
Host smart-1a97c6a9-8757-4ca4-b34e-9ec65680ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112937544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4112937544
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2042069072
Short name T173
Test name
Test status
Simulation time 2978303460 ps
CPU time 131.43 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 05:49:08 PM PDT 24
Peak memory 468112 kb
Host smart-d859061b-f339-4a04-8ae5-1ba91877c218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042069072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2042069072
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3597868310
Short name T362
Test name
Test status
Simulation time 6081487552 ps
CPU time 25.87 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:47:15 PM PDT 24
Peak memory 199824 kb
Host smart-dec7817a-60c1-4720-9551-34625c3edde2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597868310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3597868310
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1275205743
Short name T134
Test name
Test status
Simulation time 6192085850 ps
CPU time 109.91 seconds
Started Aug 07 05:46:43 PM PDT 24
Finished Aug 07 05:48:33 PM PDT 24
Peak memory 200032 kb
Host smart-70cf788f-75e4-4ea8-a569-aedac3bdb4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275205743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1275205743
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3992844622
Short name T230
Test name
Test status
Simulation time 423439319 ps
CPU time 10.44 seconds
Started Aug 07 05:46:48 PM PDT 24
Finished Aug 07 05:46:59 PM PDT 24
Peak memory 199828 kb
Host smart-38e33c92-c9a4-4415-befb-184bb07cce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992844622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3992844622
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1255181735
Short name T456
Test name
Test status
Simulation time 19255222744 ps
CPU time 242.1 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 05:50:56 PM PDT 24
Peak memory 199836 kb
Host smart-4e90f4bb-34c6-4b6e-9cb9-ef842b8904fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255181735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1255181735
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3608180159
Short name T352
Test name
Test status
Simulation time 19377972998 ps
CPU time 90.88 seconds
Started Aug 07 05:46:43 PM PDT 24
Finished Aug 07 05:48:14 PM PDT 24
Peak memory 199860 kb
Host smart-8a5eecbd-e575-47fb-9ec3-55d1efd89bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608180159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3608180159
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4033159543
Short name T415
Test name
Test status
Simulation time 77942519 ps
CPU time 0.56 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:46:52 PM PDT 24
Peak memory 195636 kb
Host smart-d1483476-ee29-42d8-86b3-87b0c8b7f604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033159543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4033159543
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.826752897
Short name T159
Test name
Test status
Simulation time 4846682589 ps
CPU time 57.77 seconds
Started Aug 07 05:46:50 PM PDT 24
Finished Aug 07 05:47:48 PM PDT 24
Peak memory 199820 kb
Host smart-f9ff35c9-916f-47ec-8a2d-83d5414320af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826752897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.826752897
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2844849859
Short name T269
Test name
Test status
Simulation time 323935542 ps
CPU time 4.98 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 05:46:59 PM PDT 24
Peak memory 199744 kb
Host smart-bb74325c-efd7-4454-baec-708638e3a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844849859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2844849859
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.344072174
Short name T33
Test name
Test status
Simulation time 11783999413 ps
CPU time 558.94 seconds
Started Aug 07 05:46:50 PM PDT 24
Finished Aug 07 05:56:09 PM PDT 24
Peak memory 689428 kb
Host smart-9153abcd-19b7-407d-b022-89a4dd01ecde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344072174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.344072174
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1717968985
Short name T346
Test name
Test status
Simulation time 7382898964 ps
CPU time 133.4 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:49:07 PM PDT 24
Peak memory 199844 kb
Host smart-72af1317-618e-4fe5-8c54-ce629c5ecc76
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717968985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1717968985
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.145810311
Short name T429
Test name
Test status
Simulation time 1257736965 ps
CPU time 67.36 seconds
Started Aug 07 05:46:46 PM PDT 24
Finished Aug 07 05:47:54 PM PDT 24
Peak memory 199888 kb
Host smart-5d81c87d-b230-48a2-a6df-8963477dbdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145810311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.145810311
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4245118709
Short name T343
Test name
Test status
Simulation time 749463717 ps
CPU time 6.84 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 05:47:01 PM PDT 24
Peak memory 199844 kb
Host smart-21891e90-331c-4281-af5e-b13d956c2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245118709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4245118709
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1961660288
Short name T13
Test name
Test status
Simulation time 96536794694 ps
CPU time 2898.08 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 06:35:07 PM PDT 24
Peak memory 795992 kb
Host smart-888b5a8f-80bb-49e4-befa-feee03aba2c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961660288 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1961660288
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1998322669
Short name T276
Test name
Test status
Simulation time 16424597107 ps
CPU time 49.14 seconds
Started Aug 07 05:46:50 PM PDT 24
Finished Aug 07 05:47:39 PM PDT 24
Peak memory 199816 kb
Host smart-665dadb7-6d5c-49fb-b2c1-4e1e5893645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998322669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1998322669
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1120858060
Short name T155
Test name
Test status
Simulation time 14060974 ps
CPU time 0.6 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:46:54 PM PDT 24
Peak memory 194844 kb
Host smart-c408ba62-a8e3-4ee3-a3fd-ff9bea0747e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120858060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1120858060
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.831642382
Short name T509
Test name
Test status
Simulation time 1001102263 ps
CPU time 55.88 seconds
Started Aug 07 05:46:43 PM PDT 24
Finished Aug 07 05:47:39 PM PDT 24
Peak memory 199776 kb
Host smart-624da56d-294f-4425-9d06-18de49271ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831642382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.831642382
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1618582283
Short name T426
Test name
Test status
Simulation time 492079398 ps
CPU time 9.38 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:47:05 PM PDT 24
Peak memory 198848 kb
Host smart-f3bcbdbf-0da3-4c52-9c59-916e20a43c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618582283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1618582283
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.131279071
Short name T434
Test name
Test status
Simulation time 1998043489 ps
CPU time 319.95 seconds
Started Aug 07 05:46:43 PM PDT 24
Finished Aug 07 05:52:03 PM PDT 24
Peak memory 641056 kb
Host smart-39627a51-b755-4664-ad31-ff10a52f2b44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131279071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.131279071
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2935607538
Short name T56
Test name
Test status
Simulation time 603681895 ps
CPU time 20.55 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:47:13 PM PDT 24
Peak memory 200012 kb
Host smart-cc5f014f-496c-4ccf-a0be-b808c5bc89b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935607538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2935607538
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.950074344
Short name T144
Test name
Test status
Simulation time 22940299946 ps
CPU time 137.31 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:49:13 PM PDT 24
Peak memory 199848 kb
Host smart-ce0b1de2-9c69-4bf7-8689-9bdb34e4a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950074344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.950074344
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.56396932
Short name T363
Test name
Test status
Simulation time 272909700 ps
CPU time 3.28 seconds
Started Aug 07 05:46:47 PM PDT 24
Finished Aug 07 05:46:51 PM PDT 24
Peak memory 200064 kb
Host smart-bea53e5e-9adc-40ad-a654-8c18ff73b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56396932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.56396932
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2102985346
Short name T295
Test name
Test status
Simulation time 508588749913 ps
CPU time 2972.96 seconds
Started Aug 07 05:46:47 PM PDT 24
Finished Aug 07 06:36:20 PM PDT 24
Peak memory 783192 kb
Host smart-21ac51ae-fca3-4132-8371-58fb7623d4b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102985346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2102985346
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.909334747
Short name T92
Test name
Test status
Simulation time 88137519651 ps
CPU time 135.32 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:49:06 PM PDT 24
Peak memory 199816 kb
Host smart-d3e652ad-e121-4fb1-833c-949a0ba8b818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909334747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.909334747
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3780227458
Short name T499
Test name
Test status
Simulation time 13164135 ps
CPU time 0.57 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:46:55 PM PDT 24
Peak memory 194792 kb
Host smart-a0542bcc-c1c1-4014-a85d-ec8297b384b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780227458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3780227458
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3913401809
Short name T282
Test name
Test status
Simulation time 890593641 ps
CPU time 50.18 seconds
Started Aug 07 05:46:45 PM PDT 24
Finished Aug 07 05:47:36 PM PDT 24
Peak memory 199820 kb
Host smart-b88da6eb-11b7-4ca0-99ff-dfd6c994e636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913401809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3913401809
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1658715258
Short name T332
Test name
Test status
Simulation time 3281316337 ps
CPU time 14.9 seconds
Started Aug 07 05:46:48 PM PDT 24
Finished Aug 07 05:47:03 PM PDT 24
Peak memory 199844 kb
Host smart-5e434490-5e54-4aa0-b55b-e0375d5681af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658715258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1658715258
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.430765691
Short name T71
Test name
Test status
Simulation time 5086799531 ps
CPU time 409.95 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:53:41 PM PDT 24
Peak memory 663664 kb
Host smart-09ebb42f-38d3-4116-82e7-7ecc8f6ad6c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430765691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.430765691
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.747765581
Short name T259
Test name
Test status
Simulation time 23028184514 ps
CPU time 45.76 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:47:39 PM PDT 24
Peak memory 199892 kb
Host smart-bf885990-2deb-4201-954a-21bfc4555cb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747765581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.747765581
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2965452699
Short name T390
Test name
Test status
Simulation time 8810396130 ps
CPU time 153.42 seconds
Started Aug 07 05:46:59 PM PDT 24
Finished Aug 07 05:49:32 PM PDT 24
Peak memory 216000 kb
Host smart-c7854ae5-58c2-4703-9ce7-6c3aa7c4977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965452699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2965452699
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2452355367
Short name T289
Test name
Test status
Simulation time 317418825 ps
CPU time 15.08 seconds
Started Aug 07 05:47:00 PM PDT 24
Finished Aug 07 05:47:15 PM PDT 24
Peak memory 199724 kb
Host smart-1b686bb9-872b-439e-adcc-dc7cddb1a7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452355367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2452355367
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1702795583
Short name T291
Test name
Test status
Simulation time 1653127260845 ps
CPU time 2611.8 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 06:30:21 PM PDT 24
Peak memory 713536 kb
Host smart-2a942478-74ea-471b-a1f3-24c4a20997ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702795583 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1702795583
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3920003716
Short name T164
Test name
Test status
Simulation time 6594334293 ps
CPU time 83.41 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:48:12 PM PDT 24
Peak memory 199912 kb
Host smart-58ad53a6-eec2-45d7-a30a-14f3d5a65842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920003716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3920003716
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.232339226
Short name T176
Test name
Test status
Simulation time 47231251 ps
CPU time 0.57 seconds
Started Aug 07 05:46:49 PM PDT 24
Finished Aug 07 05:46:50 PM PDT 24
Peak memory 195528 kb
Host smart-d6c9bb95-4215-44f6-b4cc-b3cad5c54d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232339226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.232339226
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1627397754
Short name T450
Test name
Test status
Simulation time 842034531 ps
CPU time 10.71 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:47:02 PM PDT 24
Peak memory 198792 kb
Host smart-3ecbcb3d-3cfa-4f72-a0cd-31113ab11f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627397754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1627397754
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3229984150
Short name T372
Test name
Test status
Simulation time 210027638 ps
CPU time 2.74 seconds
Started Aug 07 05:46:45 PM PDT 24
Finished Aug 07 05:46:48 PM PDT 24
Peak memory 199748 kb
Host smart-dd2816a1-2acb-4be1-9a5b-f1420b4f956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229984150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3229984150
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3265306152
Short name T42
Test name
Test status
Simulation time 1053699497 ps
CPU time 161.77 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:49:33 PM PDT 24
Peak memory 438212 kb
Host smart-cd5e1a36-7ce1-4581-9230-d458fe07c530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3265306152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3265306152
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3756637858
Short name T425
Test name
Test status
Simulation time 8576347150 ps
CPU time 114.44 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:48:50 PM PDT 24
Peak memory 199984 kb
Host smart-06313229-ab90-48a8-bbf9-958058b10547
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756637858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3756637858
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1032959639
Short name T6
Test name
Test status
Simulation time 5670435868 ps
CPU time 28.66 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 05:47:23 PM PDT 24
Peak memory 199772 kb
Host smart-293ec0d7-55c9-428c-aacf-eaccc2bc5dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032959639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1032959639
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3234834215
Short name T326
Test name
Test status
Simulation time 1216893278 ps
CPU time 14.11 seconds
Started Aug 07 05:47:00 PM PDT 24
Finished Aug 07 05:47:14 PM PDT 24
Peak memory 199788 kb
Host smart-3c4c62d1-57e8-4448-aaff-628b7071381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234834215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3234834215
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3232547859
Short name T288
Test name
Test status
Simulation time 44836307415 ps
CPU time 1638.4 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 06:14:12 PM PDT 24
Peak memory 715544 kb
Host smart-c788d04f-9384-4d18-8d65-8bef5cb92f81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232547859 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3232547859
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2243047394
Short name T321
Test name
Test status
Simulation time 1578521148 ps
CPU time 78.21 seconds
Started Aug 07 05:46:46 PM PDT 24
Finished Aug 07 05:48:04 PM PDT 24
Peak memory 199824 kb
Host smart-14d4fe69-881f-4ae7-98ac-1dd1e147b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243047394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2243047394
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2124681987
Short name T16
Test name
Test status
Simulation time 15109268 ps
CPU time 0.62 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:46:59 PM PDT 24
Peak memory 196496 kb
Host smart-35622ae3-0f9c-4d09-87d5-94d3e79eb108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124681987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2124681987
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3390412264
Short name T203
Test name
Test status
Simulation time 648298403 ps
CPU time 25.2 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 05:47:19 PM PDT 24
Peak memory 199772 kb
Host smart-5a6bec97-c00d-43ef-958e-dcf8ebb7e520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390412264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3390412264
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.828511342
Short name T197
Test name
Test status
Simulation time 392152179 ps
CPU time 7.48 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:46:59 PM PDT 24
Peak memory 199792 kb
Host smart-611f0691-7630-4960-a5ba-c0f608e0f836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828511342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.828511342
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1825220880
Short name T328
Test name
Test status
Simulation time 386154298 ps
CPU time 7.66 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:47:03 PM PDT 24
Peak memory 199904 kb
Host smart-4eee8c97-9cbd-4134-a7df-2c4d3299e025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825220880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1825220880
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1650943347
Short name T368
Test name
Test status
Simulation time 2076885977 ps
CPU time 7.28 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:47:00 PM PDT 24
Peak memory 199620 kb
Host smart-478c6421-2fa8-482d-bc21-81b3d30c59c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650943347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1650943347
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2536391052
Short name T350
Test name
Test status
Simulation time 19154576165 ps
CPU time 124.26 seconds
Started Aug 07 05:46:46 PM PDT 24
Finished Aug 07 05:48:51 PM PDT 24
Peak memory 199908 kb
Host smart-478822b2-5e36-450a-b4bb-6acb7e6bed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536391052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2536391052
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2759916067
Short name T430
Test name
Test status
Simulation time 1314828732 ps
CPU time 10.84 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:47:03 PM PDT 24
Peak memory 199708 kb
Host smart-023a6e57-f90f-4fd6-a236-32c1ebc0c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759916067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2759916067
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3818368826
Short name T61
Test name
Test status
Simulation time 76836507984 ps
CPU time 448.88 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:54:20 PM PDT 24
Peak memory 199872 kb
Host smart-7a6a1108-eb05-47cb-9b90-d7a6e916a01f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818368826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3818368826
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3087091126
Short name T120
Test name
Test status
Simulation time 2703959020 ps
CPU time 60.7 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:47:53 PM PDT 24
Peak memory 199896 kb
Host smart-cf2609ce-5a61-4790-a103-8b33cb89c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087091126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3087091126
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2016647716
Short name T261
Test name
Test status
Simulation time 25271950 ps
CPU time 0.59 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 05:46:30 PM PDT 24
Peak memory 195876 kb
Host smart-751e79ad-e1f8-4f06-a797-4cf94d19c3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016647716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2016647716
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3659212262
Short name T242
Test name
Test status
Simulation time 1720879763 ps
CPU time 51.44 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 05:47:14 PM PDT 24
Peak memory 199852 kb
Host smart-8b3df465-df94-4cfe-a985-a43114aa1779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659212262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3659212262
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.483321924
Short name T465
Test name
Test status
Simulation time 2178234729 ps
CPU time 38.32 seconds
Started Aug 07 05:46:18 PM PDT 24
Finished Aug 07 05:46:57 PM PDT 24
Peak memory 199844 kb
Host smart-a05baf42-6af4-4a0b-84d3-5535f11678eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483321924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.483321924
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4120365137
Short name T416
Test name
Test status
Simulation time 4696663858 ps
CPU time 980.4 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 06:02:43 PM PDT 24
Peak memory 733544 kb
Host smart-fd5dfee0-4f03-46b5-a02f-950eec179b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120365137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4120365137
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3554155836
Short name T339
Test name
Test status
Simulation time 11848562884 ps
CPU time 155.39 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 05:48:57 PM PDT 24
Peak memory 199860 kb
Host smart-19e90fc8-a1cb-4189-92d2-d8f847c5d4f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554155836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3554155836
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3305857265
Short name T309
Test name
Test status
Simulation time 28054929347 ps
CPU time 113.62 seconds
Started Aug 07 05:46:20 PM PDT 24
Finished Aug 07 05:48:14 PM PDT 24
Peak memory 208052 kb
Host smart-2cc7b727-a820-41ea-a9a9-113acaccd7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305857265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3305857265
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3326433322
Short name T65
Test name
Test status
Simulation time 153874725 ps
CPU time 0.89 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 05:46:30 PM PDT 24
Peak memory 218408 kb
Host smart-cc40de60-f99c-48d1-92cb-dcc4fdafc81f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326433322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3326433322
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1825798304
Short name T412
Test name
Test status
Simulation time 320284249 ps
CPU time 6.25 seconds
Started Aug 07 05:46:39 PM PDT 24
Finished Aug 07 05:46:46 PM PDT 24
Peak memory 199832 kb
Host smart-7e90f6e7-447e-42c1-b66e-aa74527a6499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825798304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1825798304
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.762639338
Short name T163
Test name
Test status
Simulation time 298185354678 ps
CPU time 879.15 seconds
Started Aug 07 05:46:32 PM PDT 24
Finished Aug 07 06:01:12 PM PDT 24
Peak memory 650852 kb
Host smart-fc1fafc8-60ff-4f76-94c8-6ae915d745a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762639338 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.762639338
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3071825947
Short name T77
Test name
Test status
Simulation time 88556915397 ps
CPU time 3424.88 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 06:43:34 PM PDT 24
Peak memory 763772 kb
Host smart-e5259e66-538c-4820-91fb-c25bfcacdc69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071825947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3071825947
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3159884640
Short name T180
Test name
Test status
Simulation time 1201649839 ps
CPU time 42.55 seconds
Started Aug 07 05:46:24 PM PDT 24
Finished Aug 07 05:47:07 PM PDT 24
Peak memory 199864 kb
Host smart-601731d1-525e-43a6-817f-ce72d66438a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3159884640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3159884640
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2594853533
Short name T191
Test name
Test status
Simulation time 4375438187 ps
CPU time 68.03 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 05:47:32 PM PDT 24
Peak memory 199700 kb
Host smart-68cd90a7-e09b-4473-8fbd-e216696faee7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2594853533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2594853533
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2151921933
Short name T360
Test name
Test status
Simulation time 3139401241 ps
CPU time 77.54 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:47:45 PM PDT 24
Peak memory 199836 kb
Host smart-5198c8ef-6f67-4cb8-980d-625786f17e02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2151921933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2151921933
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.4222816065
Short name T435
Test name
Test status
Simulation time 111569353704 ps
CPU time 693.34 seconds
Started Aug 07 05:46:21 PM PDT 24
Finished Aug 07 05:57:55 PM PDT 24
Peak memory 199864 kb
Host smart-eb535b40-7cb7-484f-b7e9-a1d7e88c4bda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4222816065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.4222816065
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.537396218
Short name T494
Test name
Test status
Simulation time 266403732085 ps
CPU time 2398.75 seconds
Started Aug 07 05:46:22 PM PDT 24
Finished Aug 07 06:26:21 PM PDT 24
Peak memory 215828 kb
Host smart-c1178474-b17a-4940-864e-6ec0b1142c21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=537396218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.537396218
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2349159779
Short name T165
Test name
Test status
Simulation time 43463779109 ps
CPU time 2180.1 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 208012 kb
Host smart-44102c60-a564-4420-a04c-bacf6e9ede2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2349159779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2349159779
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1215026921
Short name T216
Test name
Test status
Simulation time 12451182714 ps
CPU time 58.91 seconds
Started Aug 07 05:46:23 PM PDT 24
Finished Aug 07 05:47:22 PM PDT 24
Peak memory 199884 kb
Host smart-c27413e5-2e7f-4b04-ad2b-cf094da01cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215026921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1215026921
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1570556559
Short name T510
Test name
Test status
Simulation time 25541111 ps
CPU time 0.57 seconds
Started Aug 07 05:47:00 PM PDT 24
Finished Aug 07 05:47:01 PM PDT 24
Peak memory 193900 kb
Host smart-ecac01e2-f354-4e8f-afbc-32c2527cbdb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570556559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1570556559
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1289863777
Short name T448
Test name
Test status
Simulation time 3413331649 ps
CPU time 44.21 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:47:40 PM PDT 24
Peak memory 199832 kb
Host smart-4db3437a-ad0c-47f4-917f-3da16a8cfa46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289863777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1289863777
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1651805159
Short name T307
Test name
Test status
Simulation time 507545092 ps
CPU time 14.48 seconds
Started Aug 07 05:47:02 PM PDT 24
Finished Aug 07 05:47:16 PM PDT 24
Peak memory 199788 kb
Host smart-8806250b-3fd0-4e3c-a475-5a6a0bb8445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651805159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1651805159
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4253028128
Short name T179
Test name
Test status
Simulation time 12982982536 ps
CPU time 1295.84 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 06:08:31 PM PDT 24
Peak memory 758044 kb
Host smart-5497da03-de1b-4105-8c3a-6fb048bf5de5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253028128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4253028128
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2136559661
Short name T400
Test name
Test status
Simulation time 3831076422 ps
CPU time 55.83 seconds
Started Aug 07 05:47:02 PM PDT 24
Finished Aug 07 05:47:58 PM PDT 24
Peak memory 199680 kb
Host smart-8302dba4-7b92-4a6e-9bbe-78e5fe0bc715
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136559661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2136559661
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2841110103
Short name T149
Test name
Test status
Simulation time 2845502468 ps
CPU time 153.92 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:49:32 PM PDT 24
Peak memory 199832 kb
Host smart-377477c5-289d-41b8-b6ad-8413c0116585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841110103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2841110103
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.452929177
Short name T514
Test name
Test status
Simulation time 239132561 ps
CPU time 7.24 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 05:47:01 PM PDT 24
Peak memory 199812 kb
Host smart-d34a947d-5f6c-4c01-a000-4f95dd501c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452929177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.452929177
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1189066400
Short name T35
Test name
Test status
Simulation time 179654636529 ps
CPU time 2052.81 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 06:21:05 PM PDT 24
Peak memory 788668 kb
Host smart-61939b0c-8ab6-4222-ad0a-6c75b8abd9fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189066400 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1189066400
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3837318068
Short name T437
Test name
Test status
Simulation time 589778248 ps
CPU time 25.18 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:47:23 PM PDT 24
Peak memory 199776 kb
Host smart-6cf466c7-57e0-42a5-9a13-72c11b8e6be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837318068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3837318068
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3855215769
Short name T433
Test name
Test status
Simulation time 54493207 ps
CPU time 0.62 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:46:59 PM PDT 24
Peak memory 196560 kb
Host smart-d002c6dd-d422-44a6-a662-dd7bf5f0165b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855215769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3855215769
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.831010023
Short name T330
Test name
Test status
Simulation time 344490231 ps
CPU time 18.53 seconds
Started Aug 07 05:46:56 PM PDT 24
Finished Aug 07 05:47:15 PM PDT 24
Peak memory 199776 kb
Host smart-8f759916-7f19-46e1-b9f8-b8d616f43879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831010023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.831010023
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1274116490
Short name T365
Test name
Test status
Simulation time 17616958753 ps
CPU time 62.05 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:47:58 PM PDT 24
Peak memory 208056 kb
Host smart-bbd5f180-abec-4cf1-bbd5-97b431ead922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274116490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1274116490
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.947033826
Short name T213
Test name
Test status
Simulation time 7774735987 ps
CPU time 1544.6 seconds
Started Aug 07 05:47:02 PM PDT 24
Finished Aug 07 06:12:47 PM PDT 24
Peak memory 789960 kb
Host smart-ea700bcf-1d58-4d1d-8ec8-b6a06070701f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=947033826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.947033826
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.865673858
Short name T94
Test name
Test status
Simulation time 16249127377 ps
CPU time 66.25 seconds
Started Aug 07 05:47:01 PM PDT 24
Finished Aug 07 05:48:07 PM PDT 24
Peak memory 199800 kb
Host smart-7f00ecb9-e0e0-4a23-9f56-9687e617a424
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865673858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.865673858
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.498326620
Short name T236
Test name
Test status
Simulation time 16646997436 ps
CPU time 149.8 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 05:49:27 PM PDT 24
Peak memory 199772 kb
Host smart-43b3516e-1f94-461c-a16c-a20c036df3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498326620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.498326620
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1812188135
Short name T364
Test name
Test status
Simulation time 703545719 ps
CPU time 11.92 seconds
Started Aug 07 05:47:06 PM PDT 24
Finished Aug 07 05:47:18 PM PDT 24
Peak memory 199804 kb
Host smart-be86c1cb-d7f0-4aad-baac-c6eddd5158e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812188135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1812188135
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2277386605
Short name T460
Test name
Test status
Simulation time 15949175773 ps
CPU time 481.75 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:55:00 PM PDT 24
Peak memory 493088 kb
Host smart-7c27ad0c-6516-49fb-80a3-04d9986fcd72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277386605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2277386605
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1966147754
Short name T190
Test name
Test status
Simulation time 5687253270 ps
CPU time 106.81 seconds
Started Aug 07 05:46:59 PM PDT 24
Finished Aug 07 05:48:46 PM PDT 24
Peak memory 199852 kb
Host smart-23ff9c47-c93c-43a4-8046-9d0c5bbce165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966147754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1966147754
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3566529055
Short name T355
Test name
Test status
Simulation time 32759326 ps
CPU time 0.6 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:46:54 PM PDT 24
Peak memory 195508 kb
Host smart-0d6929fe-41cf-464b-9846-d5f1ba04975c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566529055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3566529055
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3946357232
Short name T487
Test name
Test status
Simulation time 113528975 ps
CPU time 3.65 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 05:47:01 PM PDT 24
Peak memory 199656 kb
Host smart-e79d7c23-da10-4ce9-bb88-8722188c9ea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946357232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3946357232
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2963244969
Short name T247
Test name
Test status
Simulation time 7568218655 ps
CPU time 32.92 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:47:25 PM PDT 24
Peak memory 199884 kb
Host smart-4f039501-da5f-46b9-b72b-d442eb5d1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963244969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2963244969
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2553163514
Short name T523
Test name
Test status
Simulation time 6124538934 ps
CPU time 1081.88 seconds
Started Aug 07 05:46:54 PM PDT 24
Finished Aug 07 06:04:57 PM PDT 24
Peak memory 760084 kb
Host smart-3f7632c8-90d9-4492-b4b8-a6148fa0330b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553163514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2553163514
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2618501708
Short name T268
Test name
Test status
Simulation time 2932691971 ps
CPU time 158.12 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:49:37 PM PDT 24
Peak memory 199868 kb
Host smart-50824d2f-368f-4fd7-add0-33cc8d1d3df7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618501708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2618501708
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2263690966
Short name T479
Test name
Test status
Simulation time 10523132483 ps
CPU time 187.94 seconds
Started Aug 07 05:46:59 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 208100 kb
Host smart-7ad3799d-2b7c-491b-bc2c-28ab168aaf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263690966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2263690966
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2368971135
Short name T262
Test name
Test status
Simulation time 224989276 ps
CPU time 10.33 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:47:09 PM PDT 24
Peak memory 199760 kb
Host smart-e679eb0d-3679-4c26-ad38-2ddefe69af38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368971135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2368971135
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3399347283
Short name T136
Test name
Test status
Simulation time 86139238305 ps
CPU time 1985.78 seconds
Started Aug 07 05:47:01 PM PDT 24
Finished Aug 07 06:20:07 PM PDT 24
Peak memory 762316 kb
Host smart-a5a65f07-0fe1-4c88-898e-9017a99dabd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399347283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3399347283
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1856113606
Short name T299
Test name
Test status
Simulation time 18758846779 ps
CPU time 128.26 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:49:07 PM PDT 24
Peak memory 199772 kb
Host smart-b047b4f7-b0df-4b4d-85bf-af220db4eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856113606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1856113606
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4174457645
Short name T217
Test name
Test status
Simulation time 10694099 ps
CPU time 0.55 seconds
Started Aug 07 05:46:55 PM PDT 24
Finished Aug 07 05:46:56 PM PDT 24
Peak memory 194696 kb
Host smart-ee7ca0db-9fbb-423d-b78f-258aff9de5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174457645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4174457645
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1726428126
Short name T210
Test name
Test status
Simulation time 12919974999 ps
CPU time 85.98 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:48:18 PM PDT 24
Peak memory 199840 kb
Host smart-d6b927ec-6daf-4fba-a996-5cc83e5ecd7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726428126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1726428126
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4178657306
Short name T70
Test name
Test status
Simulation time 6896149802 ps
CPU time 22.94 seconds
Started Aug 07 05:46:53 PM PDT 24
Finished Aug 07 05:47:16 PM PDT 24
Peak memory 216040 kb
Host smart-6da539e3-0f85-466c-b3c5-f630a703bee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178657306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4178657306
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2783115482
Short name T351
Test name
Test status
Simulation time 40707017279 ps
CPU time 971.96 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 06:03:05 PM PDT 24
Peak memory 535648 kb
Host smart-e1f0d047-4a4c-488a-8be0-c33aee2f34d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2783115482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2783115482
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1769090798
Short name T157
Test name
Test status
Simulation time 1312000249 ps
CPU time 70.02 seconds
Started Aug 07 05:46:51 PM PDT 24
Finished Aug 07 05:48:01 PM PDT 24
Peak memory 199856 kb
Host smart-f2beb024-4e4e-46d6-9552-650f672b45f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769090798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1769090798
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1654088604
Short name T81
Test name
Test status
Simulation time 58934641048 ps
CPU time 173.22 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:49:52 PM PDT 24
Peak memory 200124 kb
Host smart-cdbba3a7-2fa3-42ae-b076-9a4dbb846f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654088604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1654088604
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2061799942
Short name T265
Test name
Test status
Simulation time 718925154 ps
CPU time 8.32 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:47:00 PM PDT 24
Peak memory 199820 kb
Host smart-6cf4a126-36cd-4052-a239-a9e916dc379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061799942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2061799942
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1558450642
Short name T84
Test name
Test status
Simulation time 315335113969 ps
CPU time 1649.65 seconds
Started Aug 07 05:47:01 PM PDT 24
Finished Aug 07 06:14:31 PM PDT 24
Peak memory 716144 kb
Host smart-a8b27689-e275-46ef-ab6f-8c1e74a4c338
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558450642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1558450642
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1863358351
Short name T329
Test name
Test status
Simulation time 42020426191 ps
CPU time 116.39 seconds
Started Aug 07 05:46:52 PM PDT 24
Finished Aug 07 05:48:48 PM PDT 24
Peak memory 199948 kb
Host smart-4fab5559-a7b7-4968-8561-bd0a2dde2860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863358351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1863358351
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.338750462
Short name T392
Test name
Test status
Simulation time 13592675 ps
CPU time 0.58 seconds
Started Aug 07 05:46:59 PM PDT 24
Finished Aug 07 05:47:00 PM PDT 24
Peak memory 195900 kb
Host smart-2903a778-2737-4bdf-9a46-f774f64f0082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338750462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.338750462
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3594967624
Short name T384
Test name
Test status
Simulation time 422757787 ps
CPU time 24.83 seconds
Started Aug 07 05:47:00 PM PDT 24
Finished Aug 07 05:47:25 PM PDT 24
Peak memory 199740 kb
Host smart-388d29c5-0d21-48c0-a89f-4cf6887331fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594967624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3594967624
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2391844897
Short name T318
Test name
Test status
Simulation time 996133355 ps
CPU time 3.82 seconds
Started Aug 07 05:47:07 PM PDT 24
Finished Aug 07 05:47:11 PM PDT 24
Peak memory 199728 kb
Host smart-9158dfac-9805-48cc-b0fa-41c46c35e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391844897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2391844897
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.267287029
Short name T31
Test name
Test status
Simulation time 17912858422 ps
CPU time 765.1 seconds
Started Aug 07 05:47:03 PM PDT 24
Finished Aug 07 05:59:49 PM PDT 24
Peak memory 655728 kb
Host smart-1b404299-e905-4871-b569-6393e6df2709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267287029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.267287029
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3554503789
Short name T406
Test name
Test status
Simulation time 12311087252 ps
CPU time 152.19 seconds
Started Aug 07 05:46:59 PM PDT 24
Finished Aug 07 05:49:31 PM PDT 24
Peak memory 199740 kb
Host smart-62385419-5904-4f47-8870-882d19b71ffe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554503789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3554503789
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3465717963
Short name T455
Test name
Test status
Simulation time 675504317 ps
CPU time 25.43 seconds
Started Aug 07 05:47:07 PM PDT 24
Finished Aug 07 05:47:33 PM PDT 24
Peak memory 199776 kb
Host smart-c3ff8371-28fc-4fbc-bdc1-e174b6f9f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465717963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3465717963
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.4287808654
Short name T252
Test name
Test status
Simulation time 100414524 ps
CPU time 0.93 seconds
Started Aug 07 05:47:03 PM PDT 24
Finished Aug 07 05:47:04 PM PDT 24
Peak memory 198924 kb
Host smart-64764ffb-c4c1-4ab0-9045-05091f26ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287808654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.4287808654
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3816415407
Short name T87
Test name
Test status
Simulation time 257909380961 ps
CPU time 1351.67 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 06:09:29 PM PDT 24
Peak memory 713392 kb
Host smart-40cd801c-044e-43d1-bc1b-8e8ffb2cc33f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816415407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3816415407
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1024390336
Short name T399
Test name
Test status
Simulation time 756286741 ps
CPU time 10.87 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:47:09 PM PDT 24
Peak memory 199740 kb
Host smart-31b0d96e-8eb1-4ca6-a413-89be7adb2392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024390336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1024390336
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3861513131
Short name T254
Test name
Test status
Simulation time 21843826 ps
CPU time 0.57 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 05:46:58 PM PDT 24
Peak memory 196552 kb
Host smart-5bef42a5-1213-41bf-ac36-5f2e1b67524d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861513131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3861513131
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3851108674
Short name T12
Test name
Test status
Simulation time 1023596342 ps
CPU time 46.45 seconds
Started Aug 07 05:47:00 PM PDT 24
Finished Aug 07 05:47:46 PM PDT 24
Peak memory 199780 kb
Host smart-48063cf3-17ba-4f6d-82a4-2cd8b3bc233e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3851108674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3851108674
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.490044075
Short name T488
Test name
Test status
Simulation time 288181187 ps
CPU time 4.27 seconds
Started Aug 07 05:46:56 PM PDT 24
Finished Aug 07 05:47:00 PM PDT 24
Peak memory 199780 kb
Host smart-836aedda-4e47-4885-8e58-71e52b1834ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490044075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.490044075
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2648616080
Short name T224
Test name
Test status
Simulation time 7602746216 ps
CPU time 700.19 seconds
Started Aug 07 05:47:03 PM PDT 24
Finished Aug 07 05:58:43 PM PDT 24
Peak memory 686120 kb
Host smart-2093a8e8-fb7c-4b06-8c22-aa18e53246f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648616080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2648616080
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3440938176
Short name T389
Test name
Test status
Simulation time 3265764304 ps
CPU time 85.45 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:48:24 PM PDT 24
Peak memory 199848 kb
Host smart-5efde5ca-4127-4811-80bd-ba7f2a18344c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440938176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3440938176
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.454449297
Short name T255
Test name
Test status
Simulation time 3130213907 ps
CPU time 164.14 seconds
Started Aug 07 05:47:03 PM PDT 24
Finished Aug 07 05:49:47 PM PDT 24
Peak memory 199944 kb
Host smart-000317d2-862a-42e2-acfe-bc5425ee386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454449297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.454449297
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4112977702
Short name T441
Test name
Test status
Simulation time 2260189598 ps
CPU time 7.4 seconds
Started Aug 07 05:46:58 PM PDT 24
Finished Aug 07 05:47:05 PM PDT 24
Peak memory 199908 kb
Host smart-cf802114-f0c4-433a-b786-2a8db132d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112977702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4112977702
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2059677143
Short name T300
Test name
Test status
Simulation time 25964313646 ps
CPU time 1696.69 seconds
Started Aug 07 05:46:56 PM PDT 24
Finished Aug 07 06:15:13 PM PDT 24
Peak memory 785420 kb
Host smart-f3867d11-5d69-4446-9f51-72d026784288
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059677143 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2059677143
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2335354603
Short name T496
Test name
Test status
Simulation time 5213098777 ps
CPU time 61.72 seconds
Started Aug 07 05:46:59 PM PDT 24
Finished Aug 07 05:48:00 PM PDT 24
Peak memory 199760 kb
Host smart-a86da367-8e95-4d68-841b-387c18d72cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335354603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2335354603
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2011012821
Short name T440
Test name
Test status
Simulation time 22839728 ps
CPU time 0.62 seconds
Started Aug 07 05:47:06 PM PDT 24
Finished Aug 07 05:47:07 PM PDT 24
Peak memory 194844 kb
Host smart-6dd3e272-ddb6-400c-98c1-b65ecb0bb98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011012821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2011012821
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2164272705
Short name T338
Test name
Test status
Simulation time 611047562 ps
CPU time 33.75 seconds
Started Aug 07 05:47:02 PM PDT 24
Finished Aug 07 05:47:36 PM PDT 24
Peak memory 199872 kb
Host smart-f6b4a3ff-50c1-4ac7-9594-645c4699e14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164272705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2164272705
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1760219175
Short name T520
Test name
Test status
Simulation time 6096033449 ps
CPU time 62.22 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 05:48:00 PM PDT 24
Peak memory 208012 kb
Host smart-5d9027f0-f4e5-4f0e-83b2-d3d1941318e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760219175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1760219175
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2545756893
Short name T142
Test name
Test status
Simulation time 15760198768 ps
CPU time 622.42 seconds
Started Aug 07 05:46:57 PM PDT 24
Finished Aug 07 05:57:20 PM PDT 24
Peak memory 681872 kb
Host smart-b9ce0bed-de8a-46bf-bd56-3d5069667dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545756893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2545756893
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3973886076
Short name T473
Test name
Test status
Simulation time 7056339676 ps
CPU time 86.25 seconds
Started Aug 07 05:47:04 PM PDT 24
Finished Aug 07 05:48:30 PM PDT 24
Peak memory 199860 kb
Host smart-b5cb7c6f-00ea-4f54-9fce-1ca844c0990d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973886076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3973886076
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.83628163
Short name T49
Test name
Test status
Simulation time 4360707133 ps
CPU time 33.81 seconds
Started Aug 07 05:47:06 PM PDT 24
Finished Aug 07 05:47:40 PM PDT 24
Peak memory 199760 kb
Host smart-418cc4f6-c076-41a4-9d3d-4e41aff5e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83628163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.83628163
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.25275161
Short name T331
Test name
Test status
Simulation time 315602903 ps
CPU time 6 seconds
Started Aug 07 05:46:56 PM PDT 24
Finished Aug 07 05:47:02 PM PDT 24
Peak memory 199800 kb
Host smart-8122a994-79b5-4a40-a1e9-195f6de71ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25275161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.25275161
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.187991717
Short name T357
Test name
Test status
Simulation time 16855338894 ps
CPU time 2201.65 seconds
Started Aug 07 05:47:06 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 724116 kb
Host smart-db4efb95-5d92-4396-928d-1365021ebd3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187991717 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.187991717
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.329077498
Short name T374
Test name
Test status
Simulation time 5260131357 ps
CPU time 61.97 seconds
Started Aug 07 05:47:06 PM PDT 24
Finished Aug 07 05:48:08 PM PDT 24
Peak memory 199896 kb
Host smart-71945c16-1ff8-44ee-b9bc-9a10cfe51209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329077498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.329077498
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.753175636
Short name T320
Test name
Test status
Simulation time 11956971 ps
CPU time 0.59 seconds
Started Aug 07 05:47:12 PM PDT 24
Finished Aug 07 05:47:12 PM PDT 24
Peak memory 195552 kb
Host smart-3fd0058b-33b3-410f-9bc4-deec48f80ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753175636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.753175636
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3935188364
Short name T379
Test name
Test status
Simulation time 1241876087 ps
CPU time 38.23 seconds
Started Aug 07 05:47:03 PM PDT 24
Finished Aug 07 05:47:41 PM PDT 24
Peak memory 199824 kb
Host smart-864d7ad0-ca14-4a4b-ba51-b123d6fe14fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935188364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3935188364
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3906102376
Short name T482
Test name
Test status
Simulation time 19274967161 ps
CPU time 835.56 seconds
Started Aug 07 05:47:05 PM PDT 24
Finished Aug 07 06:01:01 PM PDT 24
Peak memory 714116 kb
Host smart-9549f22a-9d44-4ede-a4f3-3cacd4989ca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906102376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3906102376
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3029866841
Short name T475
Test name
Test status
Simulation time 216654577 ps
CPU time 11.79 seconds
Started Aug 07 05:47:13 PM PDT 24
Finished Aug 07 05:47:25 PM PDT 24
Peak memory 199640 kb
Host smart-2cd201ee-adda-4a0a-bc3f-38465fac27e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029866841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3029866841
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1738181010
Short name T414
Test name
Test status
Simulation time 6655750711 ps
CPU time 180.29 seconds
Started Aug 07 05:47:09 PM PDT 24
Finished Aug 07 05:50:10 PM PDT 24
Peak memory 199944 kb
Host smart-95615d55-d5ae-47d3-b140-9cab8fe90362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738181010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1738181010
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3243043591
Short name T158
Test name
Test status
Simulation time 175671111 ps
CPU time 3.53 seconds
Started Aug 07 05:47:06 PM PDT 24
Finished Aug 07 05:47:10 PM PDT 24
Peak memory 199780 kb
Host smart-6ea8fef6-b015-449b-b805-3c888325fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243043591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3243043591
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.891855877
Short name T481
Test name
Test status
Simulation time 53357734030 ps
CPU time 1955.76 seconds
Started Aug 07 05:47:14 PM PDT 24
Finished Aug 07 06:19:50 PM PDT 24
Peak memory 772948 kb
Host smart-9180e4d2-82d8-4f33-bbf7-f0fae78b469d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891855877 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.891855877
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2229385778
Short name T89
Test name
Test status
Simulation time 13111621516 ps
CPU time 100.99 seconds
Started Aug 07 05:47:12 PM PDT 24
Finished Aug 07 05:48:53 PM PDT 24
Peak memory 199916 kb
Host smart-559a66de-5bab-4791-b46f-9aa3bc1cc776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229385778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2229385778
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4160459799
Short name T58
Test name
Test status
Simulation time 12040669 ps
CPU time 0.59 seconds
Started Aug 07 05:47:16 PM PDT 24
Finished Aug 07 05:47:16 PM PDT 24
Peak memory 195636 kb
Host smart-0719a0bf-dbf6-4fe4-83e9-c15be3cfe4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160459799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4160459799
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2087571543
Short name T25
Test name
Test status
Simulation time 1559977832 ps
CPU time 86.56 seconds
Started Aug 07 05:47:19 PM PDT 24
Finished Aug 07 05:48:46 PM PDT 24
Peak memory 199784 kb
Host smart-e2c6755a-a52d-45df-a65f-23786d48927b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087571543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2087571543
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2877000640
Short name T519
Test name
Test status
Simulation time 503530600 ps
CPU time 9.8 seconds
Started Aug 07 05:47:12 PM PDT 24
Finished Aug 07 05:47:22 PM PDT 24
Peak memory 199784 kb
Host smart-4393ca27-cb43-4540-b84c-245619058fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877000640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2877000640
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2252329085
Short name T96
Test name
Test status
Simulation time 10793645748 ps
CPU time 536.85 seconds
Started Aug 07 05:47:13 PM PDT 24
Finished Aug 07 05:56:10 PM PDT 24
Peak memory 721272 kb
Host smart-8b2d5ade-2c06-4c6f-a608-885559c2d272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252329085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2252329085
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3963554021
Short name T188
Test name
Test status
Simulation time 4026591040 ps
CPU time 59.86 seconds
Started Aug 07 05:47:11 PM PDT 24
Finished Aug 07 05:48:11 PM PDT 24
Peak memory 199868 kb
Host smart-287b2bb6-3811-4585-b3b0-bdc7693f0332
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963554021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3963554021
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2037395410
Short name T284
Test name
Test status
Simulation time 96301822141 ps
CPU time 159.78 seconds
Started Aug 07 05:47:12 PM PDT 24
Finished Aug 07 05:49:51 PM PDT 24
Peak memory 208104 kb
Host smart-0ae424aa-cb40-4ed1-bc3e-9f9b7d5ec430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037395410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2037395410
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.4017000782
Short name T410
Test name
Test status
Simulation time 932828191 ps
CPU time 11.93 seconds
Started Aug 07 05:47:10 PM PDT 24
Finished Aug 07 05:47:22 PM PDT 24
Peak memory 199772 kb
Host smart-10967f09-a7b6-4f7d-8167-d433f8b8ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017000782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.4017000782
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2248687073
Short name T302
Test name
Test status
Simulation time 63692173900 ps
CPU time 1475 seconds
Started Aug 07 05:47:15 PM PDT 24
Finished Aug 07 06:11:50 PM PDT 24
Peak memory 705680 kb
Host smart-dbdf0893-d0d0-4043-a77d-0295a38355ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248687073 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2248687073
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2353326196
Short name T263
Test name
Test status
Simulation time 36582288434 ps
CPU time 112.65 seconds
Started Aug 07 05:47:13 PM PDT 24
Finished Aug 07 05:49:06 PM PDT 24
Peak memory 199832 kb
Host smart-330c38cb-cae7-4244-b12c-91993c319d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353326196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2353326196
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3069061268
Short name T178
Test name
Test status
Simulation time 11774337 ps
CPU time 0.6 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:47:17 PM PDT 24
Peak memory 195592 kb
Host smart-8becee04-7288-4e50-ac0d-b0ef95a11488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069061268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3069061268
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2192013942
Short name T20
Test name
Test status
Simulation time 5136590134 ps
CPU time 18.67 seconds
Started Aug 07 05:47:15 PM PDT 24
Finished Aug 07 05:47:33 PM PDT 24
Peak memory 199832 kb
Host smart-17c7c87b-16e6-464b-9e91-ab2f7427a01a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192013942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2192013942
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.872688388
Short name T391
Test name
Test status
Simulation time 9579770048 ps
CPU time 10.87 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:47:28 PM PDT 24
Peak memory 199844 kb
Host smart-3ed18712-1ca7-40df-a8cb-d5e9f26e19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872688388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.872688388
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1072638005
Short name T167
Test name
Test status
Simulation time 1623797490 ps
CPU time 222.47 seconds
Started Aug 07 05:47:14 PM PDT 24
Finished Aug 07 05:50:57 PM PDT 24
Peak memory 495708 kb
Host smart-7b1c60e7-ebd7-48a7-829a-e94d5020ba1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072638005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1072638005
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1444470116
Short name T513
Test name
Test status
Simulation time 931857603 ps
CPU time 51.03 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:48:08 PM PDT 24
Peak memory 199776 kb
Host smart-c51c572a-04f0-4a12-bef2-ae299ad8d32c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444470116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1444470116
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1472698554
Short name T229
Test name
Test status
Simulation time 2666569574 ps
CPU time 48.06 seconds
Started Aug 07 05:47:15 PM PDT 24
Finished Aug 07 05:48:04 PM PDT 24
Peak memory 199772 kb
Host smart-7d4e3960-7e00-41e5-ac9d-d0dc3352fe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472698554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1472698554
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1151258185
Short name T489
Test name
Test status
Simulation time 134558026 ps
CPU time 2.02 seconds
Started Aug 07 05:47:15 PM PDT 24
Finished Aug 07 05:47:17 PM PDT 24
Peak memory 199804 kb
Host smart-34038537-7d48-46c7-bb7b-726b0721a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151258185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1151258185
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1482210978
Short name T324
Test name
Test status
Simulation time 22079813271 ps
CPU time 74.81 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:48:35 PM PDT 24
Peak memory 199892 kb
Host smart-546ee299-9d5f-44f7-8319-1dfb907e9cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482210978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1482210978
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.759172415
Short name T470
Test name
Test status
Simulation time 44101963 ps
CPU time 0.61 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 05:46:30 PM PDT 24
Peak memory 195892 kb
Host smart-c60c7d2b-3d4e-4b51-ab13-b06faebbd0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759172415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.759172415
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.822703733
Short name T317
Test name
Test status
Simulation time 1108251508 ps
CPU time 58.44 seconds
Started Aug 07 05:46:31 PM PDT 24
Finished Aug 07 05:47:29 PM PDT 24
Peak memory 199828 kb
Host smart-20f62161-d520-48e6-92bb-1740e1841527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822703733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.822703733
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3246686025
Short name T462
Test name
Test status
Simulation time 705389829 ps
CPU time 36.96 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:47:10 PM PDT 24
Peak memory 199840 kb
Host smart-ce9e37a6-1cd4-4b06-89d7-5f9e59df325f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246686025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3246686025
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.459475584
Short name T267
Test name
Test status
Simulation time 3565726642 ps
CPU time 358.46 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:52:26 PM PDT 24
Peak memory 667988 kb
Host smart-14c9b1b6-2516-4202-a934-f3dccc6ec670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459475584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.459475584
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3723225495
Short name T272
Test name
Test status
Simulation time 15866506608 ps
CPU time 183.88 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 05:49:32 PM PDT 24
Peak memory 199904 kb
Host smart-99c67410-d01d-490c-b5a9-40cbf83eff71
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723225495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3723225495
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2952747931
Short name T341
Test name
Test status
Simulation time 1482296275 ps
CPU time 81.64 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:47:49 PM PDT 24
Peak memory 199792 kb
Host smart-3ece3af5-9d9c-4ca9-a581-75cfe1411e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952747931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2952747931
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.1754701456
Short name T371
Test name
Test status
Simulation time 2258869287 ps
CPU time 10.18 seconds
Started Aug 07 05:46:31 PM PDT 24
Finished Aug 07 05:46:41 PM PDT 24
Peak memory 199932 kb
Host smart-7665fd6c-6203-4576-858a-fc53f54409c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754701456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1754701456
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4123799338
Short name T85
Test name
Test status
Simulation time 246947477416 ps
CPU time 2183.55 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 704708 kb
Host smart-2ae4de55-6f25-40be-80b5-fa4d361fe131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123799338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4123799338
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.527278040
Short name T461
Test name
Test status
Simulation time 26192640927 ps
CPU time 40.28 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:47:10 PM PDT 24
Peak memory 199840 kb
Host smart-c18c0e59-205b-4bef-87be-0d3694af7445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=527278040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.527278040
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.239746652
Short name T287
Test name
Test status
Simulation time 15452469727 ps
CPU time 56.95 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 05:47:25 PM PDT 24
Peak memory 199908 kb
Host smart-9daa6632-9e99-425a-bef0-d4eea565b64c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=239746652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.239746652
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2418974140
Short name T260
Test name
Test status
Simulation time 2156147306 ps
CPU time 66.48 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:47:37 PM PDT 24
Peak memory 199884 kb
Host smart-463c917b-7fc9-4c7b-8db8-79ad5d8576e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2418974140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2418974140
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3795311805
Short name T503
Test name
Test status
Simulation time 21138462503 ps
CPU time 581.2 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:56:09 PM PDT 24
Peak memory 199676 kb
Host smart-3c1b085c-ef8b-4d48-a147-1c38611c5634
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3795311805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3795311805
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.202682720
Short name T474
Test name
Test status
Simulation time 41992200422 ps
CPU time 2393.91 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 06:26:22 PM PDT 24
Peak memory 215548 kb
Host smart-7e342bf5-2942-4f52-ad1e-1cca51d54969
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=202682720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.202682720
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3391208728
Short name T220
Test name
Test status
Simulation time 533992417126 ps
CPU time 2424.27 seconds
Started Aug 07 05:46:26 PM PDT 24
Finished Aug 07 06:26:51 PM PDT 24
Peak memory 216260 kb
Host smart-2d73670d-0d1d-42d7-8cb7-0cdf651c8f93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3391208728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3391208728
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3129798219
Short name T471
Test name
Test status
Simulation time 1662133711 ps
CPU time 74.92 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:47:46 PM PDT 24
Peak memory 199788 kb
Host smart-c98c0917-6cf0-46e2-9a28-b1280e0d90ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129798219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3129798219
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1740462046
Short name T241
Test name
Test status
Simulation time 14374161 ps
CPU time 0.6 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:47:21 PM PDT 24
Peak memory 195540 kb
Host smart-ade2ff50-52df-4bdb-954d-516525966d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740462046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1740462046
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2780308411
Short name T46
Test name
Test status
Simulation time 1115706570 ps
CPU time 64.87 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:48:22 PM PDT 24
Peak memory 199852 kb
Host smart-e4e64f8b-d556-4ae1-afc4-2090d121cd49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2780308411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2780308411
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1817123202
Short name T383
Test name
Test status
Simulation time 389582086 ps
CPU time 1.65 seconds
Started Aug 07 05:47:15 PM PDT 24
Finished Aug 07 05:47:17 PM PDT 24
Peak memory 199660 kb
Host smart-9875b622-5979-48ca-b18f-2f13514c63d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817123202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1817123202
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.469823138
Short name T160
Test name
Test status
Simulation time 617722974 ps
CPU time 40.11 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:47:58 PM PDT 24
Peak memory 316664 kb
Host smart-8ec83691-4206-49fd-a8f0-7a6dc3fc8552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469823138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.469823138
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3530913926
Short name T334
Test name
Test status
Simulation time 1262895198 ps
CPU time 37.32 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:47:54 PM PDT 24
Peak memory 199780 kb
Host smart-51197458-6b12-4958-b1cd-c8346897f52f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530913926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3530913926
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.6681592
Short name T452
Test name
Test status
Simulation time 2200047392 ps
CPU time 118.83 seconds
Started Aug 07 05:47:16 PM PDT 24
Finished Aug 07 05:49:15 PM PDT 24
Peak memory 199812 kb
Host smart-716c5ce0-ddf2-4d03-a5d4-bfdbd3ff1265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6681592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.6681592
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2948418470
Short name T427
Test name
Test status
Simulation time 3462596195 ps
CPU time 9.43 seconds
Started Aug 07 05:47:16 PM PDT 24
Finished Aug 07 05:47:26 PM PDT 24
Peak memory 199868 kb
Host smart-21bd3980-05b2-48c0-ba8a-e3e4c4972b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948418470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2948418470
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.915719448
Short name T454
Test name
Test status
Simulation time 63318244325 ps
CPU time 1233.35 seconds
Started Aug 07 05:49:41 PM PDT 24
Finished Aug 07 06:10:15 PM PDT 24
Peak memory 680732 kb
Host smart-1eec8baf-63f0-45f8-8303-0c2945181eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915719448 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.915719448
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1867483250
Short name T27
Test name
Test status
Simulation time 854874606 ps
CPU time 42.32 seconds
Started Aug 07 05:47:17 PM PDT 24
Finished Aug 07 05:47:59 PM PDT 24
Peak memory 199776 kb
Host smart-3223c522-c657-4bd4-b1df-6143256412ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867483250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1867483250
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2623085297
Short name T507
Test name
Test status
Simulation time 13561465 ps
CPU time 0.56 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:47:20 PM PDT 24
Peak memory 195696 kb
Host smart-5432b0db-f963-4a2d-9d25-a15684b67f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623085297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2623085297
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3328001371
Short name T43
Test name
Test status
Simulation time 660819323 ps
CPU time 18.01 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:47:39 PM PDT 24
Peak memory 199876 kb
Host smart-6902e245-6b51-4c70-aab0-fb9f58023757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328001371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3328001371
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3914789497
Short name T41
Test name
Test status
Simulation time 1565748997 ps
CPU time 28.72 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:47:49 PM PDT 24
Peak memory 199792 kb
Host smart-b2a3578f-2215-4543-96ed-66555fc0ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914789497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3914789497
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2140307325
Short name T337
Test name
Test status
Simulation time 5104985425 ps
CPU time 292.7 seconds
Started Aug 07 05:47:21 PM PDT 24
Finished Aug 07 05:52:14 PM PDT 24
Peak memory 603140 kb
Host smart-72002a5c-c1be-4071-9dca-832d0d55cf14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140307325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2140307325
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1936758604
Short name T491
Test name
Test status
Simulation time 139488539 ps
CPU time 7.86 seconds
Started Aug 07 05:47:22 PM PDT 24
Finished Aug 07 05:47:30 PM PDT 24
Peak memory 199724 kb
Host smart-e48335d0-1ce1-46b3-8988-56e2e3ab7a80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936758604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1936758604
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4199464765
Short name T301
Test name
Test status
Simulation time 7754911478 ps
CPU time 136.26 seconds
Started Aug 07 05:47:25 PM PDT 24
Finished Aug 07 05:49:41 PM PDT 24
Peak memory 199888 kb
Host smart-022e9f9d-77d9-410b-a678-9e46d3b87311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199464765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4199464765
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2268875076
Short name T439
Test name
Test status
Simulation time 164003875 ps
CPU time 3.22 seconds
Started Aug 07 05:47:19 PM PDT 24
Finished Aug 07 05:47:23 PM PDT 24
Peak memory 199792 kb
Host smart-abc3f5b8-2578-4f01-ae73-ccb9246d663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268875076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2268875076
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.434462196
Short name T48
Test name
Test status
Simulation time 123909149827 ps
CPU time 4971.36 seconds
Started Aug 07 05:47:25 PM PDT 24
Finished Aug 07 07:10:17 PM PDT 24
Peak memory 837720 kb
Host smart-8d15c05f-709c-4f3b-842a-ca772c8271e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434462196 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.434462196
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.176612315
Short name T90
Test name
Test status
Simulation time 6455955452 ps
CPU time 79.69 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:48:40 PM PDT 24
Peak memory 199812 kb
Host smart-cec54442-5133-4ca9-859b-3d12ebdf0dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176612315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.176612315
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2747219011
Short name T402
Test name
Test status
Simulation time 15217883 ps
CPU time 0.6 seconds
Started Aug 07 05:49:42 PM PDT 24
Finished Aug 07 05:49:43 PM PDT 24
Peak memory 195876 kb
Host smart-2823e33e-a969-4f4c-b174-170d6ebad5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747219011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2747219011
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3263485421
Short name T447
Test name
Test status
Simulation time 2760132552 ps
CPU time 12.11 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:47:33 PM PDT 24
Peak memory 199812 kb
Host smart-49a9b11d-ac9b-4e7c-97d9-214de730d88b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263485421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3263485421
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3675671695
Short name T143
Test name
Test status
Simulation time 11001071560 ps
CPU time 43.94 seconds
Started Aug 07 05:47:27 PM PDT 24
Finished Aug 07 05:48:11 PM PDT 24
Peak memory 199788 kb
Host smart-98b1c02c-5c83-40b4-a67f-ebd7fb8b66fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675671695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3675671695
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2068779143
Short name T256
Test name
Test status
Simulation time 19814179914 ps
CPU time 1010.72 seconds
Started Aug 07 05:47:22 PM PDT 24
Finished Aug 07 06:04:13 PM PDT 24
Peak memory 766784 kb
Host smart-170d65ac-9bb0-4d25-aa33-dc4ed1794fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068779143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2068779143
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1117982011
Short name T55
Test name
Test status
Simulation time 8673639036 ps
CPU time 54.59 seconds
Started Aug 07 05:47:27 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 199792 kb
Host smart-40bd04a4-266b-4fa4-8d7a-33cc2c693ffa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117982011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1117982011
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3411825869
Short name T200
Test name
Test status
Simulation time 5442875095 ps
CPU time 97.85 seconds
Started Aug 07 05:47:20 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 199896 kb
Host smart-714bf644-b8af-4dbf-887a-6898f24c6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411825869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3411825869
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2704034436
Short name T235
Test name
Test status
Simulation time 147837528 ps
CPU time 2 seconds
Started Aug 07 05:47:21 PM PDT 24
Finished Aug 07 05:47:23 PM PDT 24
Peak memory 199632 kb
Host smart-717142db-1ab2-49b5-996d-d5538c9333d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704034436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2704034436
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1224246291
Short name T348
Test name
Test status
Simulation time 1989958001 ps
CPU time 92.44 seconds
Started Aug 07 05:47:27 PM PDT 24
Finished Aug 07 05:48:59 PM PDT 24
Peak memory 440864 kb
Host smart-858fda96-786a-4385-8b11-3aeb8ceded64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224246291 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1224246291
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1534980443
Short name T500
Test name
Test status
Simulation time 48937984995 ps
CPU time 139.02 seconds
Started Aug 07 05:47:26 PM PDT 24
Finished Aug 07 05:49:45 PM PDT 24
Peak memory 199832 kb
Host smart-a6c4f448-416d-4164-a2d7-a0169c730016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534980443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1534980443
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3552244665
Short name T398
Test name
Test status
Simulation time 16133672 ps
CPU time 0.6 seconds
Started Aug 07 05:47:25 PM PDT 24
Finished Aug 07 05:47:26 PM PDT 24
Peak memory 195876 kb
Host smart-ecee3570-16d0-4ee3-bd45-bd4b3ffe2334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552244665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3552244665
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1665536477
Short name T21
Test name
Test status
Simulation time 5047916903 ps
CPU time 63.64 seconds
Started Aug 07 05:47:25 PM PDT 24
Finished Aug 07 05:48:29 PM PDT 24
Peak memory 199864 kb
Host smart-c2e59ebb-9257-4f69-8a35-b4b844006929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665536477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1665536477
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3912102330
Short name T137
Test name
Test status
Simulation time 1124578653 ps
CPU time 57.26 seconds
Started Aug 07 05:47:24 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 199892 kb
Host smart-1900954c-cb39-4e62-8f48-5eae56defc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912102330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3912102330
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3377359585
Short name T36
Test name
Test status
Simulation time 4724772467 ps
CPU time 800.35 seconds
Started Aug 07 05:47:25 PM PDT 24
Finished Aug 07 06:00:46 PM PDT 24
Peak memory 699304 kb
Host smart-d05f4335-4ecc-48a2-82ba-514df4174457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377359585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3377359585
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1566406723
Short name T354
Test name
Test status
Simulation time 9315350807 ps
CPU time 90.8 seconds
Started Aug 07 05:47:24 PM PDT 24
Finished Aug 07 05:48:55 PM PDT 24
Peak memory 199884 kb
Host smart-b513fbe4-e7d0-40b1-aa7e-c9493dc51a50
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566406723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1566406723
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2616541040
Short name T4
Test name
Test status
Simulation time 3017982996 ps
CPU time 167.44 seconds
Started Aug 07 05:47:25 PM PDT 24
Finished Aug 07 05:50:13 PM PDT 24
Peak memory 199972 kb
Host smart-1432c03f-55d5-4faa-9210-4225f88577ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616541040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2616541040
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1251605067
Short name T310
Test name
Test status
Simulation time 128312542 ps
CPU time 2.58 seconds
Started Aug 07 05:47:51 PM PDT 24
Finished Aug 07 05:47:53 PM PDT 24
Peak memory 199880 kb
Host smart-31dd932b-33c9-4699-a693-7533e50680f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251605067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1251605067
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1030128565
Short name T26
Test name
Test status
Simulation time 19993680171 ps
CPU time 125.64 seconds
Started Aug 07 05:47:22 PM PDT 24
Finished Aug 07 05:49:28 PM PDT 24
Peak memory 199948 kb
Host smart-7e04c595-92a8-4700-a3a2-43c6a11368ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030128565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1030128565
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2674877061
Short name T459
Test name
Test status
Simulation time 11698455 ps
CPU time 0.61 seconds
Started Aug 07 05:47:30 PM PDT 24
Finished Aug 07 05:47:31 PM PDT 24
Peak memory 195872 kb
Host smart-990dd157-e84e-4d57-bd87-238079919383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674877061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2674877061
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2236354719
Short name T245
Test name
Test status
Simulation time 3692542656 ps
CPU time 48.7 seconds
Started Aug 07 05:47:28 PM PDT 24
Finished Aug 07 05:48:17 PM PDT 24
Peak memory 200080 kb
Host smart-3ba2402b-767a-4825-b6e3-fe309ede313d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236354719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2236354719
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.31789780
Short name T501
Test name
Test status
Simulation time 4585368864 ps
CPU time 20.55 seconds
Started Aug 07 05:47:31 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 199876 kb
Host smart-17c9bcd4-b02d-4173-92f2-76845f47a07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31789780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.31789780
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.551384610
Short name T311
Test name
Test status
Simulation time 4427996903 ps
CPU time 701.51 seconds
Started Aug 07 05:47:32 PM PDT 24
Finished Aug 07 05:59:13 PM PDT 24
Peak memory 661740 kb
Host smart-8073fff3-7597-422e-b691-9d8e5414b8fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551384610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.551384610
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2679299623
Short name T516
Test name
Test status
Simulation time 62659112650 ps
CPU time 147.89 seconds
Started Aug 07 05:47:35 PM PDT 24
Finished Aug 07 05:50:03 PM PDT 24
Peak memory 199860 kb
Host smart-f4b4fb42-42ca-4cf2-b26e-96f0a49a8b3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679299623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2679299623
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.32311799
Short name T135
Test name
Test status
Simulation time 6410714328 ps
CPU time 109.02 seconds
Started Aug 07 05:47:28 PM PDT 24
Finished Aug 07 05:49:17 PM PDT 24
Peak memory 216140 kb
Host smart-7cd61e8e-2cab-4008-8ca5-56dd49c88a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32311799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.32311799
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2772287049
Short name T524
Test name
Test status
Simulation time 217123747 ps
CPU time 3.82 seconds
Started Aug 07 05:47:27 PM PDT 24
Finished Aug 07 05:47:31 PM PDT 24
Peak memory 199660 kb
Host smart-c7fde14e-c179-4153-b74f-7eadf7b3fd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772287049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2772287049
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2792020283
Short name T449
Test name
Test status
Simulation time 69265957272 ps
CPU time 1808.04 seconds
Started Aug 07 05:47:32 PM PDT 24
Finished Aug 07 06:17:41 PM PDT 24
Peak memory 708712 kb
Host smart-55585827-ae23-44c4-ab91-c78ab8b0b32b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792020283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2792020283
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1142616014
Short name T275
Test name
Test status
Simulation time 6488082591 ps
CPU time 119.42 seconds
Started Aug 07 05:47:32 PM PDT 24
Finished Aug 07 05:49:32 PM PDT 24
Peak memory 199860 kb
Host smart-7bbdf5a6-6fa5-4de1-96ce-872a4209affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142616014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1142616014
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3489551403
Short name T253
Test name
Test status
Simulation time 33160563 ps
CPU time 0.59 seconds
Started Aug 07 05:47:36 PM PDT 24
Finished Aug 07 05:47:37 PM PDT 24
Peak memory 194788 kb
Host smart-f8734b5c-2b48-49e3-a40e-928e7814aae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489551403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3489551403
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1941849073
Short name T477
Test name
Test status
Simulation time 538539219 ps
CPU time 31.1 seconds
Started Aug 07 05:47:31 PM PDT 24
Finished Aug 07 05:48:02 PM PDT 24
Peak memory 199740 kb
Host smart-46376caa-ac67-4200-86b3-f24e7f195b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941849073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1941849073
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1768371939
Short name T303
Test name
Test status
Simulation time 753725182 ps
CPU time 39.7 seconds
Started Aug 07 05:47:31 PM PDT 24
Finished Aug 07 05:48:11 PM PDT 24
Peak memory 199868 kb
Host smart-831bc5b6-dd92-40cf-8cab-c31125608f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768371939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1768371939
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3253448519
Short name T457
Test name
Test status
Simulation time 14577124272 ps
CPU time 595.93 seconds
Started Aug 07 05:47:33 PM PDT 24
Finished Aug 07 05:57:29 PM PDT 24
Peak memory 667196 kb
Host smart-d140319a-b50d-452e-8c1f-3a4b404518f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253448519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3253448519
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2563044563
Short name T214
Test name
Test status
Simulation time 10370468322 ps
CPU time 159.03 seconds
Started Aug 07 05:47:32 PM PDT 24
Finished Aug 07 05:50:11 PM PDT 24
Peak memory 199872 kb
Host smart-5ffee50b-a765-466e-a6ed-577abbf0cef1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563044563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2563044563
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.4153580526
Short name T497
Test name
Test status
Simulation time 4671433371 ps
CPU time 68.13 seconds
Started Aug 07 05:47:33 PM PDT 24
Finished Aug 07 05:48:41 PM PDT 24
Peak memory 199848 kb
Host smart-a8f7f08a-eb45-44fb-bb96-e171762fe260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153580526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.4153580526
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2275970239
Short name T502
Test name
Test status
Simulation time 799792135 ps
CPU time 12.96 seconds
Started Aug 07 05:47:32 PM PDT 24
Finished Aug 07 05:47:45 PM PDT 24
Peak memory 199796 kb
Host smart-95bf8988-d201-41c1-9a4e-32f3c2a33e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275970239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2275970239
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1965669512
Short name T258
Test name
Test status
Simulation time 281874762 ps
CPU time 12.56 seconds
Started Aug 07 05:47:36 PM PDT 24
Finished Aug 07 05:47:48 PM PDT 24
Peak memory 199776 kb
Host smart-f4fcab6f-2ad7-4a77-beb2-206e04064fff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965669512 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1965669512
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.800094688
Short name T446
Test name
Test status
Simulation time 34179088651 ps
CPU time 125.99 seconds
Started Aug 07 05:47:37 PM PDT 24
Finished Aug 07 05:49:43 PM PDT 24
Peak memory 199920 kb
Host smart-d6b198fd-de81-44ad-ac7a-21794daccfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800094688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.800094688
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2106777509
Short name T490
Test name
Test status
Simulation time 181562425 ps
CPU time 0.59 seconds
Started Aug 07 05:47:35 PM PDT 24
Finished Aug 07 05:47:36 PM PDT 24
Peak memory 195868 kb
Host smart-76622674-3b63-459d-93d4-2c11fece6a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106777509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2106777509
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2651879890
Short name T248
Test name
Test status
Simulation time 6888896729 ps
CPU time 77.7 seconds
Started Aug 07 05:47:37 PM PDT 24
Finished Aug 07 05:48:54 PM PDT 24
Peak memory 199820 kb
Host smart-f7e23ade-6174-4982-ab61-f91f6df6caa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651879890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2651879890
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1590761808
Short name T154
Test name
Test status
Simulation time 801777666 ps
CPU time 11.19 seconds
Started Aug 07 05:47:39 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 199804 kb
Host smart-1356614c-60c3-4b8f-a377-6a97deb09dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590761808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1590761808
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2452087901
Short name T250
Test name
Test status
Simulation time 23391115370 ps
CPU time 441.41 seconds
Started Aug 07 05:47:34 PM PDT 24
Finished Aug 07 05:54:56 PM PDT 24
Peak memory 682004 kb
Host smart-5de7439c-687e-4443-8d52-c10a8b799a89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452087901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2452087901
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.46409191
Short name T347
Test name
Test status
Simulation time 5173452065 ps
CPU time 142.76 seconds
Started Aug 07 05:47:38 PM PDT 24
Finished Aug 07 05:50:02 PM PDT 24
Peak memory 199812 kb
Host smart-c549183d-88e5-45a2-9aa2-77bd60b2ec7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46409191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.46409191
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2844854807
Short name T198
Test name
Test status
Simulation time 54655253715 ps
CPU time 180.04 seconds
Started Aug 07 05:47:34 PM PDT 24
Finished Aug 07 05:50:35 PM PDT 24
Peak memory 199824 kb
Host smart-f0e70b18-d829-4412-9322-caf3bf6f9062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844854807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2844854807
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2095036210
Short name T424
Test name
Test status
Simulation time 4872356454 ps
CPU time 14.47 seconds
Started Aug 07 05:47:38 PM PDT 24
Finished Aug 07 05:47:52 PM PDT 24
Peak memory 199784 kb
Host smart-b0e1fe1c-2d4a-4aca-bca3-c4a2551b694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095036210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2095036210
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.429920460
Short name T498
Test name
Test status
Simulation time 61997261965 ps
CPU time 1140.05 seconds
Started Aug 07 05:47:40 PM PDT 24
Finished Aug 07 06:06:41 PM PDT 24
Peak memory 723628 kb
Host smart-a86c0091-ed52-4603-bcb8-f8f6c1a91b0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429920460 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.429920460
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3036189058
Short name T292
Test name
Test status
Simulation time 11034110604 ps
CPU time 97.57 seconds
Started Aug 07 05:47:43 PM PDT 24
Finished Aug 07 05:49:21 PM PDT 24
Peak memory 199916 kb
Host smart-9f46fdc0-3dac-4796-b934-94b964263e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036189058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3036189058
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.380321549
Short name T467
Test name
Test status
Simulation time 197182213 ps
CPU time 0.58 seconds
Started Aug 07 05:47:38 PM PDT 24
Finished Aug 07 05:47:39 PM PDT 24
Peak memory 195868 kb
Host smart-3a6acba8-4386-4953-bfad-e8f994399ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380321549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.380321549
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4081055717
Short name T419
Test name
Test status
Simulation time 845295546 ps
CPU time 49.64 seconds
Started Aug 07 05:47:36 PM PDT 24
Finished Aug 07 05:48:26 PM PDT 24
Peak memory 199808 kb
Host smart-d1cf3373-dea2-474a-a7c9-f15b6fa0867a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081055717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4081055717
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2723883238
Short name T162
Test name
Test status
Simulation time 1084634158 ps
CPU time 18.7 seconds
Started Aug 07 05:47:35 PM PDT 24
Finished Aug 07 05:47:54 PM PDT 24
Peak memory 199776 kb
Host smart-b85b502f-d2b7-455d-b6dc-1f099abecab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723883238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2723883238
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1987166647
Short name T193
Test name
Test status
Simulation time 4168817319 ps
CPU time 673.24 seconds
Started Aug 07 05:47:36 PM PDT 24
Finished Aug 07 05:58:49 PM PDT 24
Peak memory 645516 kb
Host smart-0b420777-7b6a-42e7-9a14-f8a3356c3d8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987166647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1987166647
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.944232404
Short name T342
Test name
Test status
Simulation time 6726838942 ps
CPU time 63.36 seconds
Started Aug 07 05:47:35 PM PDT 24
Finished Aug 07 05:48:39 PM PDT 24
Peak memory 199860 kb
Host smart-2c3303dd-510d-4f1b-96d7-97c292dae099
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944232404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.944232404
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2106720526
Short name T151
Test name
Test status
Simulation time 15556474268 ps
CPU time 125.56 seconds
Started Aug 07 05:49:42 PM PDT 24
Finished Aug 07 05:51:48 PM PDT 24
Peak memory 199936 kb
Host smart-c5ec02c0-e986-482a-9478-fd5bd24b88d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106720526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2106720526
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2072130717
Short name T30
Test name
Test status
Simulation time 169280746 ps
CPU time 3.32 seconds
Started Aug 07 05:47:34 PM PDT 24
Finished Aug 07 05:47:38 PM PDT 24
Peak memory 199824 kb
Host smart-09b9f6dc-7727-4d35-acd6-dadaa3d1d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072130717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2072130717
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3356458208
Short name T237
Test name
Test status
Simulation time 56189570673 ps
CPU time 937.74 seconds
Started Aug 07 05:47:40 PM PDT 24
Finished Aug 07 06:03:18 PM PDT 24
Peak memory 199796 kb
Host smart-f7dc6a93-577e-41a3-a7af-a5221045047c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356458208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3356458208
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.647430428
Short name T378
Test name
Test status
Simulation time 5066458961 ps
CPU time 69.38 seconds
Started Aug 07 05:47:34 PM PDT 24
Finished Aug 07 05:48:44 PM PDT 24
Peak memory 199840 kb
Host smart-34260823-6f48-420b-b0ff-dcd9a3749fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647430428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.647430428
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3208027433
Short name T517
Test name
Test status
Simulation time 80915066 ps
CPU time 0.61 seconds
Started Aug 07 05:47:42 PM PDT 24
Finished Aug 07 05:47:43 PM PDT 24
Peak memory 195908 kb
Host smart-15a3b788-ac33-4e46-b6db-c363b26946a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208027433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3208027433
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1556451668
Short name T182
Test name
Test status
Simulation time 22672348862 ps
CPU time 81.61 seconds
Started Aug 07 05:47:36 PM PDT 24
Finished Aug 07 05:48:57 PM PDT 24
Peak memory 208084 kb
Host smart-daed0f0c-9dbf-4a5e-b4dd-32f4893cfd9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556451668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1556451668
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3159256833
Short name T443
Test name
Test status
Simulation time 36657779774 ps
CPU time 59.55 seconds
Started Aug 07 05:47:35 PM PDT 24
Finished Aug 07 05:48:35 PM PDT 24
Peak memory 216264 kb
Host smart-d6f7e21f-a174-427c-941b-65f6e21416ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159256833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3159256833
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2434757398
Short name T366
Test name
Test status
Simulation time 943983570 ps
CPU time 162.42 seconds
Started Aug 07 05:47:36 PM PDT 24
Finished Aug 07 05:50:19 PM PDT 24
Peak memory 467176 kb
Host smart-5200b2de-3a4e-47d7-8c7c-8bc2adaa9345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434757398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2434757398
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3064304916
Short name T444
Test name
Test status
Simulation time 2956809975 ps
CPU time 37.51 seconds
Started Aug 07 05:47:41 PM PDT 24
Finished Aug 07 05:48:19 PM PDT 24
Peak memory 199924 kb
Host smart-7b58f5fd-2c54-485a-bd0b-e057debfb1fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064304916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3064304916
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.209470691
Short name T207
Test name
Test status
Simulation time 3228988951 ps
CPU time 44.09 seconds
Started Aug 07 05:47:37 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 199756 kb
Host smart-536d3e99-7e4d-4f77-a204-118a9f10bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209470691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.209470691
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3025504581
Short name T395
Test name
Test status
Simulation time 237413270 ps
CPU time 3.79 seconds
Started Aug 07 05:47:34 PM PDT 24
Finished Aug 07 05:47:38 PM PDT 24
Peak memory 199772 kb
Host smart-2a76038e-0d58-47fc-bafc-adc22370a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025504581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3025504581
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3868254580
Short name T222
Test name
Test status
Simulation time 145751015851 ps
CPU time 784.59 seconds
Started Aug 07 05:47:41 PM PDT 24
Finished Aug 07 06:00:46 PM PDT 24
Peak memory 691532 kb
Host smart-3ed1293c-aabf-4bc2-8584-a96dcfcac578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868254580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3868254580
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.93276967
Short name T238
Test name
Test status
Simulation time 2110350985 ps
CPU time 26.92 seconds
Started Aug 07 05:47:43 PM PDT 24
Finished Aug 07 05:48:10 PM PDT 24
Peak memory 199824 kb
Host smart-95a19359-0a09-4a11-abb6-99a3b368eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93276967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.93276967
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2521248841
Short name T319
Test name
Test status
Simulation time 16905592 ps
CPU time 0.58 seconds
Started Aug 07 05:47:43 PM PDT 24
Finished Aug 07 05:47:44 PM PDT 24
Peak memory 195556 kb
Host smart-7aaf6b65-5d0a-4601-a26b-031b2b7114fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521248841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2521248841
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1735423703
Short name T231
Test name
Test status
Simulation time 208830417 ps
CPU time 11.18 seconds
Started Aug 07 05:47:39 PM PDT 24
Finished Aug 07 05:47:50 PM PDT 24
Peak memory 199788 kb
Host smart-21ba6607-4c7b-4e3c-8681-813e699126ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735423703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1735423703
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.76715523
Short name T175
Test name
Test status
Simulation time 6565235378 ps
CPU time 30.48 seconds
Started Aug 07 05:47:42 PM PDT 24
Finished Aug 07 05:48:12 PM PDT 24
Peak memory 199932 kb
Host smart-08f384d8-823f-4a94-9db8-657ce8c2f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76715523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.76715523
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3649560524
Short name T246
Test name
Test status
Simulation time 5904507728 ps
CPU time 1048.52 seconds
Started Aug 07 05:47:44 PM PDT 24
Finished Aug 07 06:05:13 PM PDT 24
Peak memory 685772 kb
Host smart-3556f142-a073-4b4e-b163-ebfa66aba8c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649560524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3649560524
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1911548787
Short name T333
Test name
Test status
Simulation time 2103764849 ps
CPU time 33.9 seconds
Started Aug 07 05:47:44 PM PDT 24
Finished Aug 07 05:48:18 PM PDT 24
Peak memory 199744 kb
Host smart-babcd2fb-a9b3-479a-bac1-245226d31522
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911548787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1911548787
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3404193267
Short name T271
Test name
Test status
Simulation time 153874151 ps
CPU time 8.44 seconds
Started Aug 07 05:47:40 PM PDT 24
Finished Aug 07 05:47:49 PM PDT 24
Peak memory 199804 kb
Host smart-bf14f7d2-9240-41ec-9118-b892fd3fc7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404193267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3404193267
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2001748847
Short name T466
Test name
Test status
Simulation time 1842509608 ps
CPU time 8.43 seconds
Started Aug 07 05:47:42 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 200060 kb
Host smart-498c0f11-41b1-4297-95c6-9bda8c5dba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001748847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2001748847
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2343473601
Short name T428
Test name
Test status
Simulation time 118720123168 ps
CPU time 3572.13 seconds
Started Aug 07 05:47:43 PM PDT 24
Finished Aug 07 06:47:15 PM PDT 24
Peak memory 795304 kb
Host smart-acdc4722-10fe-44df-9912-81fa53029adc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343473601 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2343473601
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2118448194
Short name T505
Test name
Test status
Simulation time 2063982265 ps
CPU time 36.16 seconds
Started Aug 07 05:47:40 PM PDT 24
Finished Aug 07 05:48:16 PM PDT 24
Peak memory 199756 kb
Host smart-0cee4b6f-270f-4795-a41d-2d5501000621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118448194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2118448194
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2933147992
Short name T192
Test name
Test status
Simulation time 15560769 ps
CPU time 0.57 seconds
Started Aug 07 05:46:32 PM PDT 24
Finished Aug 07 05:46:33 PM PDT 24
Peak memory 194908 kb
Host smart-80928240-d81f-4da3-a37b-6294e7c38169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933147992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2933147992
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1980882040
Short name T464
Test name
Test status
Simulation time 1653140428 ps
CPU time 24.41 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 05:46:53 PM PDT 24
Peak memory 199736 kb
Host smart-220974da-fa08-4a1b-8b1e-5571e72e7add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980882040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1980882040
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.265050388
Short name T285
Test name
Test status
Simulation time 2563627028 ps
CPU time 25.17 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:46:53 PM PDT 24
Peak memory 199864 kb
Host smart-90a4ad1d-84ab-47e4-90e4-062235fedf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265050388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.265050388
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1411379077
Short name T54
Test name
Test status
Simulation time 1877175953 ps
CPU time 311.64 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:51:42 PM PDT 24
Peak memory 603980 kb
Host smart-9cc846ce-d701-4f64-a182-c0739c0dd78c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411379077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1411379077
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1201806280
Short name T95
Test name
Test status
Simulation time 41098707817 ps
CPU time 130.24 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:48:37 PM PDT 24
Peak memory 199856 kb
Host smart-b7924b3d-6c42-4008-91a2-e92b9ecf1e04
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201806280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1201806280
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2170998848
Short name T515
Test name
Test status
Simulation time 12562795994 ps
CPU time 217.94 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 05:50:08 PM PDT 24
Peak memory 199840 kb
Host smart-ab89690f-e7de-41f8-96bb-846d691dc6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170998848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2170998848
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4084540990
Short name T62
Test name
Test status
Simulation time 253359516 ps
CPU time 1.14 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 05:46:29 PM PDT 24
Peak memory 219456 kb
Host smart-1c77f6f8-d53a-4cb8-8f84-068a452ec410
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084540990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4084540990
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.978324554
Short name T420
Test name
Test status
Simulation time 1020650386 ps
CPU time 12.52 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 05:46:41 PM PDT 24
Peak memory 199724 kb
Host smart-37dc9dec-53cc-49e4-8801-59d609052256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978324554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.978324554
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2905389114
Short name T83
Test name
Test status
Simulation time 194226523863 ps
CPU time 374.16 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:52:44 PM PDT 24
Peak memory 199928 kb
Host smart-ce6d219c-eb5c-4b6d-967f-4bb606130fec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905389114 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2905389114
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1648886783
Short name T78
Test name
Test status
Simulation time 69283187089 ps
CPU time 8908.75 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 08:14:59 PM PDT 24
Peak memory 867240 kb
Host smart-8856bf20-c714-440c-9fc5-b07e41797d05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648886783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1648886783
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1487913121
Short name T522
Test name
Test status
Simulation time 27109326199 ps
CPU time 49.48 seconds
Started Aug 07 05:46:31 PM PDT 24
Finished Aug 07 05:47:20 PM PDT 24
Peak memory 199848 kb
Host smart-87ad11f4-5fa2-4249-937e-495ed244457e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1487913121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1487913121
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.118484301
Short name T432
Test name
Test status
Simulation time 23335254951 ps
CPU time 58.98 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:47:26 PM PDT 24
Peak memory 199868 kb
Host smart-73fb30d7-3f7b-4081-ab1e-a998f98ecfc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=118484301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.118484301
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2803905334
Short name T40
Test name
Test status
Simulation time 12471625760 ps
CPU time 142.89 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:48:50 PM PDT 24
Peak memory 199896 kb
Host smart-8a88a65b-58c2-48aa-85d2-c0d717ce4e38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2803905334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2803905334
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2396379310
Short name T380
Test name
Test status
Simulation time 193066230599 ps
CPU time 642 seconds
Started Aug 07 05:46:32 PM PDT 24
Finished Aug 07 05:57:14 PM PDT 24
Peak memory 199764 kb
Host smart-7ec2277e-81ea-43f1-b135-d558fc0efeb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2396379310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2396379310
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1131681842
Short name T409
Test name
Test status
Simulation time 270652929546 ps
CPU time 2272.84 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 215868 kb
Host smart-84571d75-b355-45c8-b77a-e99d8d9ddcc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1131681842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1131681842
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3729436995
Short name T57
Test name
Test status
Simulation time 133137428498 ps
CPU time 2387.44 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 06:26:16 PM PDT 24
Peak memory 216236 kb
Host smart-ecd1e152-45bf-40c8-b5cb-bb8cdd055990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3729436995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3729436995
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.4209718857
Short name T370
Test name
Test status
Simulation time 1584841716 ps
CPU time 9.84 seconds
Started Aug 07 05:46:31 PM PDT 24
Finished Aug 07 05:46:41 PM PDT 24
Peak memory 199716 kb
Host smart-1e096744-eaf0-4b04-8f8c-f02b740a7e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209718857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.4209718857
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4095471728
Short name T476
Test name
Test status
Simulation time 82960154 ps
CPU time 0.56 seconds
Started Aug 07 05:47:45 PM PDT 24
Finished Aug 07 05:47:46 PM PDT 24
Peak memory 195904 kb
Host smart-3c301bfc-5b1f-496b-a36d-951e4d815845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095471728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4095471728
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3151335033
Short name T492
Test name
Test status
Simulation time 2565410523 ps
CPU time 77.03 seconds
Started Aug 07 05:47:45 PM PDT 24
Finished Aug 07 05:49:02 PM PDT 24
Peak memory 199832 kb
Host smart-cbd30105-d49b-4519-95e9-d7c701ef6f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151335033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3151335033
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2441077993
Short name T218
Test name
Test status
Simulation time 247368705 ps
CPU time 3.56 seconds
Started Aug 07 05:47:47 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 199776 kb
Host smart-dc72e2c2-10ff-46ee-9471-6f41e1083fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441077993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2441077993
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.429399695
Short name T215
Test name
Test status
Simulation time 16704739651 ps
CPU time 711.89 seconds
Started Aug 07 05:47:46 PM PDT 24
Finished Aug 07 05:59:39 PM PDT 24
Peak memory 710144 kb
Host smart-706ca450-99e8-4c27-9d0f-9246b44eed62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429399695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.429399695
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1636812608
Short name T249
Test name
Test status
Simulation time 35702308647 ps
CPU time 286.46 seconds
Started Aug 07 05:47:45 PM PDT 24
Finished Aug 07 05:52:32 PM PDT 24
Peak memory 199780 kb
Host smart-4f7231fc-1aa6-4c83-8e64-c65584f56bdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636812608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1636812608
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_smoke.1412644781
Short name T367
Test name
Test status
Simulation time 1325128654 ps
CPU time 11.5 seconds
Started Aug 07 05:47:54 PM PDT 24
Finished Aug 07 05:48:05 PM PDT 24
Peak memory 199796 kb
Host smart-72268088-3843-43a2-8384-43b0fb41ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412644781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1412644781
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3344008496
Short name T211
Test name
Test status
Simulation time 20963286491 ps
CPU time 1363.27 seconds
Started Aug 07 05:47:43 PM PDT 24
Finished Aug 07 06:10:27 PM PDT 24
Peak memory 750340 kb
Host smart-c8a260f2-15fe-485c-9ed8-d2bf5288d75d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344008496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3344008496
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1764993303
Short name T91
Test name
Test status
Simulation time 3923534718 ps
CPU time 84.9 seconds
Started Aug 07 05:47:48 PM PDT 24
Finished Aug 07 05:49:13 PM PDT 24
Peak memory 199836 kb
Host smart-e4e085ba-2f14-4b7f-bae4-f6f872c7614e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764993303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1764993303
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2941904673
Short name T403
Test name
Test status
Simulation time 26101906 ps
CPU time 0.58 seconds
Started Aug 07 05:47:53 PM PDT 24
Finished Aug 07 05:47:54 PM PDT 24
Peak memory 196512 kb
Host smart-b9c913bc-b165-4906-b60f-022a38b95858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941904673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2941904673
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.30531040
Short name T189
Test name
Test status
Simulation time 3427095283 ps
CPU time 49.11 seconds
Started Aug 07 05:47:54 PM PDT 24
Finished Aug 07 05:48:43 PM PDT 24
Peak memory 199880 kb
Host smart-f4b441c3-171a-4a92-a7a7-78d63b31dd59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30531040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.30531040
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.940064657
Short name T388
Test name
Test status
Simulation time 2737592290 ps
CPU time 8.19 seconds
Started Aug 07 05:47:44 PM PDT 24
Finished Aug 07 05:47:52 PM PDT 24
Peak memory 199760 kb
Host smart-4b7432ad-0544-4731-b834-9f17d2c0c12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940064657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.940064657
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2679049963
Short name T93
Test name
Test status
Simulation time 20670819726 ps
CPU time 1135.61 seconds
Started Aug 07 05:47:44 PM PDT 24
Finished Aug 07 06:06:40 PM PDT 24
Peak memory 762244 kb
Host smart-86a2d89f-77a9-4c5e-a607-b5a0c9d9f57c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679049963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2679049963
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2701259974
Short name T322
Test name
Test status
Simulation time 34100009781 ps
CPU time 104.66 seconds
Started Aug 07 05:47:52 PM PDT 24
Finished Aug 07 05:49:37 PM PDT 24
Peak memory 199900 kb
Host smart-fb51f567-2e4b-48db-a0b7-2e3d6a0d7633
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701259974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2701259974
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4257221076
Short name T147
Test name
Test status
Simulation time 15097931370 ps
CPU time 140.12 seconds
Started Aug 07 05:47:46 PM PDT 24
Finished Aug 07 05:50:07 PM PDT 24
Peak memory 199908 kb
Host smart-870f74c9-7d35-40c6-99bc-8edc4161f276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257221076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4257221076
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4170803867
Short name T396
Test name
Test status
Simulation time 90173997 ps
CPU time 1.87 seconds
Started Aug 07 05:47:42 PM PDT 24
Finished Aug 07 05:47:44 PM PDT 24
Peak memory 199848 kb
Host smart-729d069b-bf65-435a-899f-f9b473fa1bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170803867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4170803867
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.4142785535
Short name T97
Test name
Test status
Simulation time 114361291523 ps
CPU time 846.43 seconds
Started Aug 07 05:47:52 PM PDT 24
Finished Aug 07 06:01:59 PM PDT 24
Peak memory 216220 kb
Host smart-96fe1b43-f521-468b-bf21-dfcae0f7d4f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142785535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.4142785535
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2645490263
Short name T257
Test name
Test status
Simulation time 24558155277 ps
CPU time 77 seconds
Started Aug 07 05:47:51 PM PDT 24
Finished Aug 07 05:49:08 PM PDT 24
Peak memory 199872 kb
Host smart-7d096e84-e1b4-4ada-a612-9a31cd73f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645490263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2645490263
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.344652331
Short name T233
Test name
Test status
Simulation time 54355198 ps
CPU time 0.58 seconds
Started Aug 07 05:47:50 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 195872 kb
Host smart-d21feecf-b77f-4edd-a22c-1c29d06e4986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344652331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.344652331
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2862863208
Short name T353
Test name
Test status
Simulation time 1799640504 ps
CPU time 104.81 seconds
Started Aug 07 05:47:50 PM PDT 24
Finished Aug 07 05:49:35 PM PDT 24
Peak memory 199792 kb
Host smart-2968aae8-b99c-4f6b-9394-9c492eee433a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862863208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2862863208
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1663719073
Short name T413
Test name
Test status
Simulation time 2998441622 ps
CPU time 54.44 seconds
Started Aug 07 05:47:52 PM PDT 24
Finished Aug 07 05:48:46 PM PDT 24
Peak memory 199880 kb
Host smart-065ea388-21fc-4a7b-b813-fdff060a4b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663719073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1663719073
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.4284265357
Short name T2
Test name
Test status
Simulation time 7399421583 ps
CPU time 582.04 seconds
Started Aug 07 05:47:54 PM PDT 24
Finished Aug 07 05:57:36 PM PDT 24
Peak memory 507640 kb
Host smart-e2fee7ba-74dc-4fcb-b54e-802ef4b3634d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284265357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4284265357
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3336286447
Short name T194
Test name
Test status
Simulation time 1730164724 ps
CPU time 91.8 seconds
Started Aug 07 05:47:49 PM PDT 24
Finished Aug 07 05:49:21 PM PDT 24
Peak memory 199776 kb
Host smart-4f9f7919-4bb7-4578-8d40-3a37f2bbc6da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336286447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3336286447
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3163657664
Short name T442
Test name
Test status
Simulation time 73652904655 ps
CPU time 59.59 seconds
Started Aug 07 05:47:53 PM PDT 24
Finished Aug 07 05:48:53 PM PDT 24
Peak memory 200096 kb
Host smart-5427fa6f-041d-4406-9611-8620b1960be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163657664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3163657664
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3895265974
Short name T170
Test name
Test status
Simulation time 558419614 ps
CPU time 8.33 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 199724 kb
Host smart-c255d847-acc9-4782-b205-9132299b45eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895265974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3895265974
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3849571718
Short name T401
Test name
Test status
Simulation time 100823457657 ps
CPU time 2331.38 seconds
Started Aug 07 05:47:50 PM PDT 24
Finished Aug 07 06:26:42 PM PDT 24
Peak memory 769824 kb
Host smart-0fa184c8-aa0f-4d75-b357-9708cd3a3e9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849571718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3849571718
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3983382707
Short name T478
Test name
Test status
Simulation time 6767859939 ps
CPU time 70.99 seconds
Started Aug 07 05:47:51 PM PDT 24
Finished Aug 07 05:49:02 PM PDT 24
Peak memory 199852 kb
Host smart-a3ec6341-536e-4bf5-816e-c45c02c29094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983382707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3983382707
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2478028175
Short name T166
Test name
Test status
Simulation time 91345491 ps
CPU time 0.53 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:47:57 PM PDT 24
Peak memory 195452 kb
Host smart-82c1908a-c91e-4816-9c36-8fab8c9a0290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478028175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2478028175
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.166441088
Short name T281
Test name
Test status
Simulation time 561301407 ps
CPU time 8.72 seconds
Started Aug 07 05:47:50 PM PDT 24
Finished Aug 07 05:47:59 PM PDT 24
Peak memory 199792 kb
Host smart-2c2945f0-25ac-490b-8f77-d5719aac97ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166441088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.166441088
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2978709882
Short name T187
Test name
Test status
Simulation time 14671895129 ps
CPU time 14.6 seconds
Started Aug 07 05:47:52 PM PDT 24
Finished Aug 07 05:48:07 PM PDT 24
Peak memory 199788 kb
Host smart-ca307630-2dda-4750-add3-066f261bc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978709882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2978709882
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2133745694
Short name T72
Test name
Test status
Simulation time 76046897503 ps
CPU time 1150.38 seconds
Started Aug 07 05:47:49 PM PDT 24
Finished Aug 07 06:07:00 PM PDT 24
Peak memory 751336 kb
Host smart-35d2209d-bc83-44f7-b37f-cb0313735041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133745694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2133745694
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1654414666
Short name T298
Test name
Test status
Simulation time 7254534869 ps
CPU time 48.49 seconds
Started Aug 07 05:47:56 PM PDT 24
Finished Aug 07 05:48:44 PM PDT 24
Peak memory 199868 kb
Host smart-9d05ae96-56c0-42cc-913a-f32ebe1975d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654414666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1654414666
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1289416797
Short name T1
Test name
Test status
Simulation time 6156585823 ps
CPU time 76.16 seconds
Started Aug 07 05:47:53 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 199912 kb
Host smart-3e9fbd9d-22e5-4029-ac15-313feea08568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289416797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1289416797
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2024832423
Short name T277
Test name
Test status
Simulation time 1316587352 ps
CPU time 14.87 seconds
Started Aug 07 05:47:51 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 199880 kb
Host smart-e91b8f44-a07b-42bf-b386-183445f46522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024832423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2024832423
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1294172970
Short name T99
Test name
Test status
Simulation time 116766838957 ps
CPU time 2334.5 seconds
Started Aug 07 05:47:55 PM PDT 24
Finished Aug 07 06:26:50 PM PDT 24
Peak memory 745596 kb
Host smart-d2586628-022e-49f3-bdbd-66a2120581e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294172970 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1294172970
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2609236561
Short name T518
Test name
Test status
Simulation time 11216803004 ps
CPU time 132.81 seconds
Started Aug 07 05:47:55 PM PDT 24
Finished Aug 07 05:50:09 PM PDT 24
Peak memory 199840 kb
Host smart-09c47227-67c6-46fd-bcfa-295c374ef457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609236561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2609236561
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3105000739
Short name T394
Test name
Test status
Simulation time 29360236 ps
CPU time 0.56 seconds
Started Aug 07 05:47:53 PM PDT 24
Finished Aug 07 05:47:53 PM PDT 24
Peak memory 194716 kb
Host smart-e876ab27-34fa-402c-9cc3-3edbf7d0d3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105000739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3105000739
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3300133239
Short name T314
Test name
Test status
Simulation time 861558515 ps
CPU time 46.3 seconds
Started Aug 07 05:47:56 PM PDT 24
Finished Aug 07 05:48:42 PM PDT 24
Peak memory 199808 kb
Host smart-cd14c4d7-7ca9-42ca-aa75-ec1c5cc12dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300133239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3300133239
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1893801545
Short name T208
Test name
Test status
Simulation time 3138375841 ps
CPU time 27.95 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:48:25 PM PDT 24
Peak memory 199740 kb
Host smart-a5be1f2a-f843-4ff1-942d-16843a281e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893801545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1893801545
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2663963632
Short name T17
Test name
Test status
Simulation time 1346673269 ps
CPU time 204.73 seconds
Started Aug 07 05:47:54 PM PDT 24
Finished Aug 07 05:51:19 PM PDT 24
Peak memory 444304 kb
Host smart-f2896897-2621-4070-a3e3-56ed67bc6258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663963632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2663963632
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3882437886
Short name T294
Test name
Test status
Simulation time 5939934588 ps
CPU time 100.17 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:49:37 PM PDT 24
Peak memory 199780 kb
Host smart-bf7f785f-1e7a-4712-b9d8-96686df6a80a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882437886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3882437886
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2440043414
Short name T169
Test name
Test status
Simulation time 1773821953 ps
CPU time 22.1 seconds
Started Aug 07 05:47:55 PM PDT 24
Finished Aug 07 05:48:17 PM PDT 24
Peak memory 199784 kb
Host smart-45909605-cff7-427a-83bd-a16c8f5a818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440043414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2440043414
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1895185704
Short name T232
Test name
Test status
Simulation time 289145159 ps
CPU time 12.06 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:48:09 PM PDT 24
Peak memory 199716 kb
Host smart-3b8354b3-7a1c-40e0-9d67-7232fd1f465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895185704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1895185704
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1220979977
Short name T411
Test name
Test status
Simulation time 462538601 ps
CPU time 6.49 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:48:04 PM PDT 24
Peak memory 199764 kb
Host smart-be2efa6d-dc96-488e-b9e9-9ef7c3c3d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220979977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1220979977
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2444882722
Short name T145
Test name
Test status
Simulation time 12601726 ps
CPU time 0.59 seconds
Started Aug 07 05:49:42 PM PDT 24
Finished Aug 07 05:49:43 PM PDT 24
Peak memory 196492 kb
Host smart-6020709a-b772-41c8-954c-ab15e53a1530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444882722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2444882722
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3542344360
Short name T369
Test name
Test status
Simulation time 1440446551 ps
CPU time 31.65 seconds
Started Aug 07 05:48:04 PM PDT 24
Finished Aug 07 05:48:36 PM PDT 24
Peak memory 199736 kb
Host smart-20a57629-fe43-4e8f-b1e2-4a3d2a6ddfb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542344360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3542344360
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4121326778
Short name T283
Test name
Test status
Simulation time 1092585841 ps
CPU time 20.68 seconds
Started Aug 07 05:47:59 PM PDT 24
Finished Aug 07 05:48:20 PM PDT 24
Peak memory 199800 kb
Host smart-5624409a-feb3-4db3-a531-ffd481bd0dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121326778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4121326778
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2419694025
Short name T280
Test name
Test status
Simulation time 1618251395 ps
CPU time 152.28 seconds
Started Aug 07 05:48:01 PM PDT 24
Finished Aug 07 05:50:33 PM PDT 24
Peak memory 345784 kb
Host smart-ffd8fd27-ced6-428f-8dd2-9bc2d7a61a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419694025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2419694025
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4225190716
Short name T358
Test name
Test status
Simulation time 4691541327 ps
CPU time 132.46 seconds
Started Aug 07 05:48:03 PM PDT 24
Finished Aug 07 05:50:16 PM PDT 24
Peak memory 199904 kb
Host smart-531e3606-8d9a-4311-8ce8-4f0972e901a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225190716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4225190716
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1134346156
Short name T316
Test name
Test status
Simulation time 859500339 ps
CPU time 50.64 seconds
Started Aug 07 05:48:01 PM PDT 24
Finished Aug 07 05:48:52 PM PDT 24
Peak memory 199828 kb
Host smart-bce56413-9943-4ef2-88d6-2af14f90d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134346156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1134346156
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1383103705
Short name T408
Test name
Test status
Simulation time 350511784 ps
CPU time 6.46 seconds
Started Aug 07 05:47:57 PM PDT 24
Finished Aug 07 05:48:04 PM PDT 24
Peak memory 199792 kb
Host smart-6754021c-08b5-456a-a5d2-1077f97e283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383103705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1383103705
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3930620263
Short name T274
Test name
Test status
Simulation time 359015854249 ps
CPU time 2980.62 seconds
Started Aug 07 05:48:01 PM PDT 24
Finished Aug 07 06:37:42 PM PDT 24
Peak memory 754440 kb
Host smart-0c6ffe5c-47a3-42ed-a417-204f5401cb5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930620263 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3930620263
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4086577179
Short name T511
Test name
Test status
Simulation time 542508110 ps
CPU time 16.5 seconds
Started Aug 07 05:48:00 PM PDT 24
Finished Aug 07 05:48:16 PM PDT 24
Peak memory 199804 kb
Host smart-999d9a2b-1e1a-40d5-bc8c-4b183780f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086577179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4086577179
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.4060596636
Short name T325
Test name
Test status
Simulation time 64109150 ps
CPU time 0.6 seconds
Started Aug 07 05:48:05 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 195904 kb
Host smart-67506a82-9117-4bd4-9002-9657569fe341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060596636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.4060596636
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1241552649
Short name T39
Test name
Test status
Simulation time 7661106972 ps
CPU time 103.32 seconds
Started Aug 07 05:48:02 PM PDT 24
Finished Aug 07 05:49:45 PM PDT 24
Peak memory 199816 kb
Host smart-2fef5665-ffa5-4b61-b89d-69f9fe828767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241552649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1241552649
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2418956084
Short name T140
Test name
Test status
Simulation time 279357763 ps
CPU time 15.47 seconds
Started Aug 07 05:48:00 PM PDT 24
Finished Aug 07 05:48:15 PM PDT 24
Peak memory 199872 kb
Host smart-26fd59f4-db1b-4f7f-83a4-8fd8fd3ddf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418956084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2418956084
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1428567349
Short name T101
Test name
Test status
Simulation time 18418923407 ps
CPU time 1955.97 seconds
Started Aug 07 05:48:00 PM PDT 24
Finished Aug 07 06:20:37 PM PDT 24
Peak memory 776964 kb
Host smart-ecb9187a-cce0-404e-9f72-eb55d56c3a74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428567349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1428567349
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3760188446
Short name T29
Test name
Test status
Simulation time 4462967223 ps
CPU time 78.42 seconds
Started Aug 07 05:48:01 PM PDT 24
Finished Aug 07 05:49:19 PM PDT 24
Peak memory 199860 kb
Host smart-e4b9e472-8da2-4d96-8e07-0696c0c6258c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760188446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3760188446
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4278251835
Short name T356
Test name
Test status
Simulation time 1842826681 ps
CPU time 38.69 seconds
Started Aug 07 05:48:01 PM PDT 24
Finished Aug 07 05:48:40 PM PDT 24
Peak memory 199768 kb
Host smart-f4760970-fdcd-4307-8471-589d86a1ed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278251835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4278251835
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3687632224
Short name T323
Test name
Test status
Simulation time 1361085402 ps
CPU time 6.11 seconds
Started Aug 07 05:48:01 PM PDT 24
Finished Aug 07 05:48:07 PM PDT 24
Peak memory 199836 kb
Host smart-ea787754-7ca2-43a4-86c7-84f919f1696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687632224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3687632224
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1579858824
Short name T404
Test name
Test status
Simulation time 182275205286 ps
CPU time 2287.23 seconds
Started Aug 07 05:48:05 PM PDT 24
Finished Aug 07 06:26:13 PM PDT 24
Peak memory 794888 kb
Host smart-e0340b4b-a233-4715-ad5a-d0bf976ef1da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579858824 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1579858824
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3090914137
Short name T148
Test name
Test status
Simulation time 15299040236 ps
CPU time 96.31 seconds
Started Aug 07 05:48:02 PM PDT 24
Finished Aug 07 05:49:38 PM PDT 24
Peak memory 199928 kb
Host smart-1de0e22a-c5f4-4aeb-a61c-44aad6e2cb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090914137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3090914137
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2302534035
Short name T313
Test name
Test status
Simulation time 48238104 ps
CPU time 0.64 seconds
Started Aug 07 05:48:02 PM PDT 24
Finished Aug 07 05:48:03 PM PDT 24
Peak memory 195788 kb
Host smart-389259ef-74a0-461e-a635-0702095252ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302534035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2302534035
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1153724015
Short name T11
Test name
Test status
Simulation time 3596386987 ps
CPU time 53.03 seconds
Started Aug 07 05:48:06 PM PDT 24
Finished Aug 07 05:48:59 PM PDT 24
Peak memory 199868 kb
Host smart-58dde01a-abf9-400a-aa34-4c7d1b669841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153724015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1153724015
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1702588160
Short name T172
Test name
Test status
Simulation time 1187310014 ps
CPU time 17.22 seconds
Started Aug 07 05:48:05 PM PDT 24
Finished Aug 07 05:48:22 PM PDT 24
Peak memory 199844 kb
Host smart-70e9431c-0bfe-43d9-9ec5-bd2a282faea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702588160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1702588160
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2010178381
Short name T223
Test name
Test status
Simulation time 1494351161 ps
CPU time 49.06 seconds
Started Aug 07 05:48:07 PM PDT 24
Finished Aug 07 05:48:56 PM PDT 24
Peak memory 329344 kb
Host smart-45396f90-e26d-445d-9612-8d2093939019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010178381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2010178381
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4120508538
Short name T525
Test name
Test status
Simulation time 2827408722 ps
CPU time 82.3 seconds
Started Aug 07 05:49:43 PM PDT 24
Finished Aug 07 05:51:05 PM PDT 24
Peak memory 199780 kb
Host smart-f8f357df-ba55-4c39-a92a-73463e0cb864
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120508538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4120508538
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4168562565
Short name T240
Test name
Test status
Simulation time 20013758043 ps
CPU time 140.36 seconds
Started Aug 07 05:48:05 PM PDT 24
Finished Aug 07 05:50:26 PM PDT 24
Peak memory 199896 kb
Host smart-777ee44d-7fd9-46b0-9770-787bb1f7179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168562565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4168562565
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.93896075
Short name T150
Test name
Test status
Simulation time 59625599 ps
CPU time 1.88 seconds
Started Aug 07 05:48:04 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 199796 kb
Host smart-3366832f-995c-43c0-95ca-ff7120056c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93896075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.93896075
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.299915971
Short name T373
Test name
Test status
Simulation time 515972361 ps
CPU time 23.89 seconds
Started Aug 07 05:48:06 PM PDT 24
Finished Aug 07 05:48:30 PM PDT 24
Peak memory 199784 kb
Host smart-82deb66b-0545-418f-a279-624f080258f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299915971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.299915971
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1661786073
Short name T266
Test name
Test status
Simulation time 14499566 ps
CPU time 0.58 seconds
Started Aug 07 05:48:10 PM PDT 24
Finished Aug 07 05:48:10 PM PDT 24
Peak memory 195512 kb
Host smart-45378ed8-1a46-483a-a3b7-69cb97d7eefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661786073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1661786073
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3552778552
Short name T251
Test name
Test status
Simulation time 2610188751 ps
CPU time 74.4 seconds
Started Aug 07 05:48:06 PM PDT 24
Finished Aug 07 05:49:20 PM PDT 24
Peak memory 199928 kb
Host smart-f365181f-fc66-45df-887b-7bed56c009ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552778552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3552778552
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1666044818
Short name T139
Test name
Test status
Simulation time 162132695 ps
CPU time 8.58 seconds
Started Aug 07 05:48:08 PM PDT 24
Finished Aug 07 05:48:17 PM PDT 24
Peak memory 199844 kb
Host smart-ef9f0d88-0d81-4f71-966e-6d763c012772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666044818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1666044818
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.808614909
Short name T349
Test name
Test status
Simulation time 13618974290 ps
CPU time 525.95 seconds
Started Aug 07 05:48:10 PM PDT 24
Finished Aug 07 05:56:56 PM PDT 24
Peak memory 631488 kb
Host smart-92e52511-69ed-45b8-8253-0e0d26b76cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808614909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.808614909
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1372426064
Short name T66
Test name
Test status
Simulation time 2304350879 ps
CPU time 28.9 seconds
Started Aug 07 05:48:11 PM PDT 24
Finished Aug 07 05:48:40 PM PDT 24
Peak memory 199860 kb
Host smart-acdfa2c3-94a0-4986-b711-0ed9c94891e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372426064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1372426064
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4038888934
Short name T279
Test name
Test status
Simulation time 6883437545 ps
CPU time 34.61 seconds
Started Aug 07 05:48:04 PM PDT 24
Finished Aug 07 05:48:39 PM PDT 24
Peak memory 199824 kb
Host smart-52c7f4cf-8317-464b-b369-52040de43e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038888934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4038888934
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1578810311
Short name T226
Test name
Test status
Simulation time 47767304 ps
CPU time 1.06 seconds
Started Aug 07 05:48:02 PM PDT 24
Finished Aug 07 05:48:04 PM PDT 24
Peak memory 199660 kb
Host smart-173ccce9-470b-4cc1-9ed6-1dfe59c10cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578810311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1578810311
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4193094790
Short name T306
Test name
Test status
Simulation time 58320821609 ps
CPU time 1654.92 seconds
Started Aug 07 05:48:11 PM PDT 24
Finished Aug 07 06:15:46 PM PDT 24
Peak memory 785112 kb
Host smart-b23a5359-f3f7-43d9-b88e-db9e4c159e87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193094790 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4193094790
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1682035950
Short name T244
Test name
Test status
Simulation time 46951853706 ps
CPU time 141.2 seconds
Started Aug 07 05:48:09 PM PDT 24
Finished Aug 07 05:50:31 PM PDT 24
Peak memory 199852 kb
Host smart-6904a796-d9a3-43a5-a8a3-d744227acafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682035950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1682035950
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.875610449
Short name T47
Test name
Test status
Simulation time 15428080 ps
CPU time 0.58 seconds
Started Aug 07 05:48:18 PM PDT 24
Finished Aug 07 05:48:18 PM PDT 24
Peak memory 194844 kb
Host smart-49fae979-a50a-44b3-a874-e9f0ad329ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875610449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.875610449
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4220963513
Short name T405
Test name
Test status
Simulation time 1388208549 ps
CPU time 81.54 seconds
Started Aug 07 05:48:09 PM PDT 24
Finished Aug 07 05:49:30 PM PDT 24
Peak memory 199800 kb
Host smart-8437cb45-3490-4d78-8689-7b717e6b88e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220963513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4220963513
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3700310715
Short name T24
Test name
Test status
Simulation time 228689140 ps
CPU time 11.5 seconds
Started Aug 07 05:49:45 PM PDT 24
Finished Aug 07 05:49:56 PM PDT 24
Peak memory 199784 kb
Host smart-6fdd80c5-4190-4b10-9f46-509c3d9d8df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700310715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3700310715
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1913078872
Short name T423
Test name
Test status
Simulation time 1229937932 ps
CPU time 228.31 seconds
Started Aug 07 05:48:11 PM PDT 24
Finished Aug 07 05:51:59 PM PDT 24
Peak memory 601924 kb
Host smart-d6a2ffa2-f6af-4d70-b832-4aac7a5ea096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913078872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1913078872
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.722427678
Short name T225
Test name
Test status
Simulation time 386751547 ps
CPU time 22.74 seconds
Started Aug 07 05:48:15 PM PDT 24
Finished Aug 07 05:48:38 PM PDT 24
Peak memory 199860 kb
Host smart-982a9160-48b6-4504-8354-89f75b1e6d2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722427678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.722427678
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2205672493
Short name T206
Test name
Test status
Simulation time 937218128 ps
CPU time 48.36 seconds
Started Aug 07 05:48:09 PM PDT 24
Finished Aug 07 05:48:58 PM PDT 24
Peak memory 199800 kb
Host smart-4c7f0a8b-89e3-4bb7-83c0-fa787c3dda25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205672493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2205672493
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1792449923
Short name T221
Test name
Test status
Simulation time 3763316425 ps
CPU time 11.32 seconds
Started Aug 07 05:48:13 PM PDT 24
Finished Aug 07 05:48:24 PM PDT 24
Peak memory 199880 kb
Host smart-56f1348e-f18a-44fc-a0f9-39b1d4b31a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792449923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1792449923
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1695106991
Short name T376
Test name
Test status
Simulation time 122886472806 ps
CPU time 3465.36 seconds
Started Aug 07 05:48:15 PM PDT 24
Finished Aug 07 06:46:01 PM PDT 24
Peak memory 805148 kb
Host smart-fc9762db-6f4a-47a7-b75c-302f6173fa6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695106991 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1695106991
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.685545253
Short name T119
Test name
Test status
Simulation time 1963178052 ps
CPU time 77.88 seconds
Started Aug 07 05:48:14 PM PDT 24
Finished Aug 07 05:49:32 PM PDT 24
Peak memory 199728 kb
Host smart-22000667-9321-4060-a03e-c14700c00b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685545253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.685545253
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4053454045
Short name T59
Test name
Test status
Simulation time 15638200 ps
CPU time 0.6 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:46:35 PM PDT 24
Peak memory 195808 kb
Host smart-7b7da639-3fdd-418a-ba43-8c10f138a0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053454045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4053454045
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2189483085
Short name T387
Test name
Test status
Simulation time 4552104702 ps
CPU time 59.31 seconds
Started Aug 07 05:46:27 PM PDT 24
Finished Aug 07 05:47:27 PM PDT 24
Peak memory 208116 kb
Host smart-d0581bde-702a-4346-937e-0cc06437c6de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189483085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2189483085
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.526722853
Short name T23
Test name
Test status
Simulation time 1169743202 ps
CPU time 62.07 seconds
Started Aug 07 05:46:29 PM PDT 24
Finished Aug 07 05:47:31 PM PDT 24
Peak memory 199776 kb
Host smart-ee94d117-9ed7-4ea6-be4a-7d6301a50918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526722853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.526722853
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.239849390
Short name T438
Test name
Test status
Simulation time 10629271808 ps
CPU time 1008.12 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 06:03:22 PM PDT 24
Peak memory 702696 kb
Host smart-a7db0561-3a53-4215-aaeb-44294044a422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239849390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.239849390
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.38040282
Short name T512
Test name
Test status
Simulation time 8137037450 ps
CPU time 143.91 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:48:54 PM PDT 24
Peak memory 199872 kb
Host smart-fdb4ffa8-1898-49fd-869c-db5f9e00ddb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.38040282
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3317682772
Short name T451
Test name
Test status
Simulation time 26781007202 ps
CPU time 82.21 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 199784 kb
Host smart-27d7193c-42a3-4195-ab0f-601ee861e178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317682772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3317682772
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.153087429
Short name T468
Test name
Test status
Simulation time 320163001 ps
CPU time 5.54 seconds
Started Aug 07 05:46:30 PM PDT 24
Finished Aug 07 05:46:36 PM PDT 24
Peak memory 199820 kb
Host smart-019aea42-dabc-44fe-ae97-1b471b96991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153087429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.153087429
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.349401062
Short name T480
Test name
Test status
Simulation time 86233769677 ps
CPU time 2243.92 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 773376 kb
Host smart-584a3d38-36fc-41a0-ad26-bca230e34488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349401062 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.349401062
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3688859551
Short name T14
Test name
Test status
Simulation time 57477006226 ps
CPU time 574.63 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:56:10 PM PDT 24
Peak memory 443600 kb
Host smart-4312576f-35ef-477f-817b-358a88579c72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688859551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3688859551
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.759928122
Short name T185
Test name
Test status
Simulation time 9295969692 ps
CPU time 100.17 seconds
Started Aug 07 05:46:28 PM PDT 24
Finished Aug 07 05:48:08 PM PDT 24
Peak memory 199836 kb
Host smart-7d82320d-e821-47a7-b0bd-2784d076eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759928122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.759928122
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.195498567
Short name T485
Test name
Test status
Simulation time 136907945 ps
CPU time 0.57 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:46:33 PM PDT 24
Peak memory 196568 kb
Host smart-0157f1b9-b4aa-419d-88d5-8089c34dab31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195498567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.195498567
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.173586597
Short name T199
Test name
Test status
Simulation time 3352585344 ps
CPU time 42.34 seconds
Started Aug 07 05:46:45 PM PDT 24
Finished Aug 07 05:47:28 PM PDT 24
Peak memory 199824 kb
Host smart-a7ada1fb-9238-406c-9501-edf3dbc27162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173586597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.173586597
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3219452605
Short name T327
Test name
Test status
Simulation time 5095728218 ps
CPU time 880.61 seconds
Started Aug 07 05:46:38 PM PDT 24
Finished Aug 07 06:01:19 PM PDT 24
Peak memory 663424 kb
Host smart-3091ec0c-fae4-4ec8-9051-76652e3ab940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219452605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3219452605
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2872234183
Short name T484
Test name
Test status
Simulation time 1917783992 ps
CPU time 97.28 seconds
Started Aug 07 05:46:37 PM PDT 24
Finished Aug 07 05:48:14 PM PDT 24
Peak memory 199824 kb
Host smart-0b46b758-22c3-4f82-b8bc-720575590d9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872234183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2872234183
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3335185852
Short name T186
Test name
Test status
Simulation time 2876182379 ps
CPU time 58.25 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:47:35 PM PDT 24
Peak memory 199948 kb
Host smart-32bace9c-f962-4c87-9ce7-6559869abf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335185852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3335185852
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3105927111
Short name T212
Test name
Test status
Simulation time 55738621 ps
CPU time 2.64 seconds
Started Aug 07 05:46:45 PM PDT 24
Finished Aug 07 05:46:48 PM PDT 24
Peak memory 199740 kb
Host smart-0063f9bc-0472-44df-a260-59e22bcfc78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105927111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3105927111
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1851873148
Short name T278
Test name
Test status
Simulation time 11259635415 ps
CPU time 140.52 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:48:56 PM PDT 24
Peak memory 199932 kb
Host smart-c4d61c19-15dd-4ad7-a261-8466c57c4253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851873148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1851873148
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.108849247
Short name T88
Test name
Test status
Simulation time 30196229425 ps
CPU time 92.38 seconds
Started Aug 07 05:46:34 PM PDT 24
Finished Aug 07 05:48:06 PM PDT 24
Peak memory 199840 kb
Host smart-dbc4d4f4-f767-4661-877d-3d0a6a53c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108849247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.108849247
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1356529383
Short name T315
Test name
Test status
Simulation time 15739227 ps
CPU time 0.68 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:46:34 PM PDT 24
Peak memory 195428 kb
Host smart-0c03e73a-1077-4be3-b8df-4638303cd136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356529383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1356529383
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3425106689
Short name T51
Test name
Test status
Simulation time 4499578713 ps
CPU time 58.39 seconds
Started Aug 07 05:46:40 PM PDT 24
Finished Aug 07 05:47:38 PM PDT 24
Peak memory 199940 kb
Host smart-67c3f1f0-15e9-4765-88e4-d14a1589cded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425106689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3425106689
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1535279777
Short name T138
Test name
Test status
Simulation time 287889149 ps
CPU time 14.37 seconds
Started Aug 07 05:46:40 PM PDT 24
Finished Aug 07 05:46:55 PM PDT 24
Peak memory 199888 kb
Host smart-738efa5a-cd45-4ae9-b8ca-88788fb166ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535279777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1535279777
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1572068783
Short name T418
Test name
Test status
Simulation time 17812693327 ps
CPU time 1752.65 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 06:15:47 PM PDT 24
Peak memory 765812 kb
Host smart-21a8210d-38f3-436c-b7a4-b0b56531d0b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572068783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1572068783
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.4267614348
Short name T133
Test name
Test status
Simulation time 5231856813 ps
CPU time 147.02 seconds
Started Aug 07 05:46:37 PM PDT 24
Finished Aug 07 05:49:05 PM PDT 24
Peak memory 199892 kb
Host smart-5da884f6-5fa5-431f-9b6c-9ab19de47d63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267614348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.4267614348
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2257312399
Short name T421
Test name
Test status
Simulation time 6328687747 ps
CPU time 107.94 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:48:21 PM PDT 24
Peak memory 207968 kb
Host smart-4e48b352-1082-4a06-bb5c-47d30d4b4477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257312399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2257312399
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1995489537
Short name T201
Test name
Test status
Simulation time 534903331 ps
CPU time 7.84 seconds
Started Aug 07 05:46:34 PM PDT 24
Finished Aug 07 05:46:42 PM PDT 24
Peak memory 199780 kb
Host smart-0c53a452-e055-44dd-b331-b765b6e61853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995489537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1995489537
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.4255510059
Short name T453
Test name
Test status
Simulation time 15644164142 ps
CPU time 111.02 seconds
Started Aug 07 05:46:32 PM PDT 24
Finished Aug 07 05:48:23 PM PDT 24
Peak memory 216296 kb
Host smart-3e5ac57a-c361-4623-a69c-4605814da30b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255510059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.4255510059
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2703970290
Short name T80
Test name
Test status
Simulation time 43480986519 ps
CPU time 1125.21 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 06:05:22 PM PDT 24
Peak memory 491316 kb
Host smart-113d5ed9-d9c6-4385-ba5a-5773da080269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703970290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2703970290
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3049521428
Short name T32
Test name
Test status
Simulation time 898676349 ps
CPU time 44.89 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:47:18 PM PDT 24
Peak memory 199772 kb
Host smart-3c01b4e1-a694-4757-b152-8535af4cadeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049521428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3049521428
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1904474028
Short name T407
Test name
Test status
Simulation time 49307011 ps
CPU time 0.57 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:46:34 PM PDT 24
Peak memory 195908 kb
Host smart-5d0daf89-94d2-49a5-98ab-b7adcb26e69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904474028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1904474028
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1260612382
Short name T152
Test name
Test status
Simulation time 641386947 ps
CPU time 9.42 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:46:44 PM PDT 24
Peak memory 199768 kb
Host smart-daf8037e-2b66-4963-a632-8de51e10f8fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260612382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1260612382
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2149287714
Short name T177
Test name
Test status
Simulation time 3198209178 ps
CPU time 56.08 seconds
Started Aug 07 05:46:32 PM PDT 24
Finished Aug 07 05:47:28 PM PDT 24
Peak memory 199868 kb
Host smart-379863be-15d6-41c3-99c8-19e4fa032640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149287714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2149287714
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.145718085
Short name T382
Test name
Test status
Simulation time 411847473 ps
CPU time 7.49 seconds
Started Aug 07 05:46:34 PM PDT 24
Finished Aug 07 05:46:42 PM PDT 24
Peak memory 199788 kb
Host smart-148bc8f8-b689-4878-90e3-96653b787b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145718085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.145718085
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3198271104
Short name T161
Test name
Test status
Simulation time 2418084580 ps
CPU time 33.89 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:47:09 PM PDT 24
Peak memory 199772 kb
Host smart-78ea7861-cde4-46e7-80bf-4437038be958
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198271104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3198271104
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1267779082
Short name T100
Test name
Test status
Simulation time 19918524733 ps
CPU time 240.13 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:50:36 PM PDT 24
Peak memory 216300 kb
Host smart-a8ee8cfe-3ab6-492c-8594-468ad83a7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267779082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1267779082
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3781392135
Short name T393
Test name
Test status
Simulation time 805965748 ps
CPU time 3.67 seconds
Started Aug 07 05:46:37 PM PDT 24
Finished Aug 07 05:46:41 PM PDT 24
Peak memory 199844 kb
Host smart-4c5861f8-781d-4da3-91f3-a8a74274fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781392135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3781392135
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.257043260
Short name T98
Test name
Test status
Simulation time 42884175916 ps
CPU time 541.99 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:55:38 PM PDT 24
Peak memory 216048 kb
Host smart-06b8406c-954d-4342-a47d-48e60fe487df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257043260 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.257043260
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.653064829
Short name T10
Test name
Test status
Simulation time 67463645628 ps
CPU time 549.53 seconds
Started Aug 07 05:46:37 PM PDT 24
Finished Aug 07 05:55:47 PM PDT 24
Peak memory 347100 kb
Host smart-7c5328ca-15ba-4251-b805-7a533edbae59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653064829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.653064829
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1841030290
Short name T344
Test name
Test status
Simulation time 19910154886 ps
CPU time 74.57 seconds
Started Aug 07 05:46:33 PM PDT 24
Finished Aug 07 05:47:48 PM PDT 24
Peak memory 199900 kb
Host smart-299eb551-97f1-4706-8c1e-a94280a25653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841030290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1841030290
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4258185995
Short name T181
Test name
Test status
Simulation time 25086622 ps
CPU time 0.59 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:46:37 PM PDT 24
Peak memory 195896 kb
Host smart-4b3a4703-01f2-4301-959b-790df22ee216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258185995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4258185995
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2851640625
Short name T171
Test name
Test status
Simulation time 2454315076 ps
CPU time 67.32 seconds
Started Aug 07 05:46:36 PM PDT 24
Finished Aug 07 05:47:43 PM PDT 24
Peak memory 199884 kb
Host smart-78df3e5e-2af7-4d4b-9639-9c49baa493b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851640625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2851640625
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3474941733
Short name T463
Test name
Test status
Simulation time 11336039009 ps
CPU time 41.75 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:47:17 PM PDT 24
Peak memory 199844 kb
Host smart-811d44df-d592-48be-8d14-fb4099679c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474941733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3474941733
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2310249633
Short name T228
Test name
Test status
Simulation time 972045514 ps
CPU time 147.42 seconds
Started Aug 07 05:46:38 PM PDT 24
Finished Aug 07 05:49:06 PM PDT 24
Peak memory 409908 kb
Host smart-18cf3243-4056-432e-902c-eae171cf62b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310249633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2310249633
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1875099918
Short name T495
Test name
Test status
Simulation time 8525393402 ps
CPU time 151.2 seconds
Started Aug 07 05:46:38 PM PDT 24
Finished Aug 07 05:49:09 PM PDT 24
Peak memory 199916 kb
Host smart-80442e26-bc73-4a32-9e0a-e5aceb36c051
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875099918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1875099918
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1277241487
Short name T202
Test name
Test status
Simulation time 11747044792 ps
CPU time 76.83 seconds
Started Aug 07 05:46:34 PM PDT 24
Finished Aug 07 05:47:51 PM PDT 24
Peak memory 199900 kb
Host smart-085015e3-1dc8-40c6-ae06-2a6c4833908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277241487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1277241487
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.254864120
Short name T458
Test name
Test status
Simulation time 173742677 ps
CPU time 4.25 seconds
Started Aug 07 05:46:37 PM PDT 24
Finished Aug 07 05:46:41 PM PDT 24
Peak memory 199776 kb
Host smart-2f5e15f0-aa70-4050-9e67-7ce64f340af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254864120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.254864120
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2625577825
Short name T141
Test name
Test status
Simulation time 126123135794 ps
CPU time 2897.22 seconds
Started Aug 07 05:46:41 PM PDT 24
Finished Aug 07 06:34:59 PM PDT 24
Peak memory 817548 kb
Host smart-fdc43895-8f29-482c-a095-1bb5243d987c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625577825 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2625577825
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1708138279
Short name T76
Test name
Test status
Simulation time 1245216221325 ps
CPU time 9183.71 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 08:19:40 PM PDT 24
Peak memory 863860 kb
Host smart-3befef0c-0e75-4f9d-b97b-91a0ff852850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708138279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1708138279
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.858916057
Short name T156
Test name
Test status
Simulation time 14002565435 ps
CPU time 114.57 seconds
Started Aug 07 05:46:35 PM PDT 24
Finished Aug 07 05:48:29 PM PDT 24
Peak memory 199876 kb
Host smart-2e2b81c7-7244-4a8c-ab2f-c819b0f93b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858916057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.858916057
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%