Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17483738	1			T1	1259		T2	3829		T3	20838
all_values[1]	17483738	1			T1	1259		T2	3829		T3	20838
all_values[2]	17483738	1			T1	1259		T2	3829		T3	20838

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229511

1

T1

146

T5

337

T15

3

auto[1]

52221703

1

T1

3631

T2

11487

T3

62514

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44729226

1

T1

2956

T2

8858

T3

55870

auto[1]

7721988

1

T1

821

T2

2629

T3

6644

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90966	1			T5	335		T18	823		T7	7
all_values[0]	auto[0]	auto[1]	370	1			T5	2		T18	4		T7	7
all_values[0]	auto[1]	auto[0]	17373184	1			T1	1251		T2	3819		T3	20818
all_values[0]	auto[1]	auto[1]	19218	1			T1	8		T2	10		T3	20
all_values[1]	auto[0]	auto[0]	67021	1			T1	73		T15	3		T7	10
all_values[1]	auto[0]	auto[1]	224	1			T7	4		T43	1		T20	1
all_values[1]	auto[1]	auto[0]	17416149	1			T1	1186		T2	3829		T3	20838
all_values[1]	auto[1]	auto[1]	344	1			T7	10		T43	2		T20	2
all_values[2]	auto[0]	auto[0]	32920	1			T1	73		T19	51		T18	240
all_values[2]	auto[0]	auto[1]	38010	1			T19	1		T18	70		T7	7
all_values[2]	auto[1]	auto[0]	9748986	1			T1	373		T2	1210		T3	14214
all_values[2]	auto[1]	auto[1]	7663822	1			T1	813		T2	2619		T3	6624