Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131640

1

T1

670

T2

18

T3

32

auto[1]

112966

1

T1

432

T2

6

T3

22

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	93927	1			T1	486		T2	11		T3	20
len_1026_2046	7632	1			T1	54		T3	1		T5	2
len_514_1022	3901	1			T1	4		T18	9		T32	1
len_2_510	3028	1			T1	4		T18	7		T32	2
len_2056	158	1			T18	3		T7	2		T45	2
len_2048	420	1			T13	2		T7	5		T55	3
len_2040	194	1			T18	5		T7	3		T80	4
len_1032	124	1			T18	2		T7	6		T45	3
len_1024	1768	1			T1	1		T3	1		T5	3
len_1016	151	1			T19	3		T18	3		T7	5
len_520	330	1			T15	5		T7	12		T80	9
len_512	311	1			T1	2		T2	1		T13	1
len_504	142	1			T6	1		T7	5		T45	3
len_8	977	1			T4	5		T14	6		T15	12
len_0	9240	1			T3	5		T6	1		T13	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

116

1

T2

1

T13

2

T7

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	52828	1			T1	330		T2	8		T3	10
auto[0]	len_1026_2046	3394	1			T1	2		T3	1		T5	2
auto[0]	len_514_1022	2492	1			T1	1		T18	2		T7	12
auto[0]	len_2_510	1970	1			T18	3		T7	10		T55	20
auto[0]	len_2056	90	1			T18	1		T7	2		T45	1
auto[0]	len_2048	273	1			T13	2		T7	4		T55	3
auto[0]	len_2040	115	1			T18	2		T7	2		T80	2
auto[0]	len_1032	63	1			T18	2		T7	5		T45	1
auto[0]	len_1024	227	1			T1	1		T3	1		T5	1
auto[0]	len_1016	84	1			T19	2		T18	2		T7	4
auto[0]	len_520	93	1			T7	9		T80	5		T8	1
auto[0]	len_512	180	1			T1	1		T2	1		T13	1
auto[0]	len_504	100	1			T6	1		T7	4		T45	3
auto[0]	len_8	39	1			T7	1		T8	12		T116	2
auto[0]	len_0	3872	1			T3	4		T6	1		T13	1
auto[1]	len_2050_plus	41099	1			T1	156		T2	3		T3	10
auto[1]	len_1026_2046	4238	1			T1	52		T13	2		T18	3
auto[1]	len_514_1022	1409	1			T1	3		T18	7		T32	1
auto[1]	len_2_510	1058	1			T1	4		T18	4		T32	2
auto[1]	len_2056	68	1			T18	2		T45	1		T131	1
auto[1]	len_2048	147	1			T7	1		T66	1		T132	2
auto[1]	len_2040	79	1			T18	3		T7	1		T80	2
auto[1]	len_1032	61	1			T7	1		T45	2		T20	2
auto[1]	len_1024	1541	1			T5	2		T13	1		T30	117
auto[1]	len_1016	67	1			T19	1		T18	1		T7	1
auto[1]	len_520	237	1			T15	5		T7	3		T80	4
auto[1]	len_512	131	1			T1	1		T18	3		T7	2
auto[1]	len_504	42	1			T7	1		T131	2		T80	4
auto[1]	len_8	938	1			T4	5		T14	6		T15	12
auto[1]	len_0	5368	1			T3	1		T13	1		T14	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

58

1

T2

1

T7

1

T55

1

auto[1]

len_upper

58

1

T13

2

T56

1

T16

2