Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4420698

1

T1

1511

T2

3

T3

5484

auto[1]

2625233

1

T1

711

T2

11

T3

4892

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2637539

1

T1

500

T2

8

T3

6121

auto[1]

4408392

1

T1

1722

T2

6

T3

4255

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3275670

1

T1

1362

T2

11

T3

5565

auto[1]

3770261

1

T1

860

T2

3

T3

4811

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4462522

1

T1

610

T2

7

T3

3900

auto[1]

2583409

1

T1

1612

T2

7

T3

6476

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6381432	1			T1	2127		T2	11		T3	10218
fifo_depth[1]	117645	1			T1	14		T2	1		T3	131
fifo_depth[2]	91528	1			T1	18		T2	2		T3	23
fifo_depth[3]	71682	1			T1	16		T3	3		T4	79
fifo_depth[4]	63703	1			T1	24		T3	1		T4	85
fifo_depth[5]	49665	1			T1	6		T4	72		T5	2
fifo_depth[6]	40130	1			T1	10		T4	70		T5	1
fifo_depth[7]	26201	1			T1	2		T4	38		T5	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664499

1

T1

95

T2

3

T3

158

auto[1]

6381432

1

T1

2127

T2

11

T3

10218

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7035177

1

T1

2222

T2

14

T3

10376

auto[1]

10754

1

T20

56

T16

693

T80

86

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28863

1

T3

31

T5

1

T13

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33320

1

T5

1

T18

359

T7

24

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

25677

1

T1

8

T3

8

T13

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29986

1

T1

1

T2

1

T3

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

168242

1

T5

2

T13

1

T18

446

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28866

1

T5

4

T13

3

T18

267

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30544

1

T3

6

T18

152

T7

17

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25872

1

T2

1

T3

11

T5

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

31854

1

T1

3

T3

13

T18

99

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

34886

1

T3

39

T4

552

T5

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39855

1

T2

1

T3

5

T5

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

33258

1

T3

14

T15

6

T18

206

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45491

1

T30

100

T18

423

T7

41

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35312

1

T1

59

T3

18

T5

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41981

1

T1

24

T13

1

T18

519

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

30492

1

T3

11

T18

1116

T7

153

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

164905

1

T3

1179

T5

3

T13

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

168785

1

T1

80

T2

2

T3

846

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

169371

1

T1

114

T2

2

T3

633

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

175085

1

T1

129

T2

1

T3

604

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1719488

1

T2

1

T3

46

T12

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

167135

1

T1

1030

T5

2

T13

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

164356

1

T2

2

T3

745

T13

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

175175

1

T2

1

T3

1454

T6

11

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

427118

1

T1

26

T3

539

T5

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

415924

1

T3

1657

T4

6249

T5

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

455806

1

T1

139

T3

228

T4

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

402846

1

T2

1

T3

323

T4

4161

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

510788

1

T3

467

T5

1

T14

1323

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

439721

1

T1

313

T3

649

T4

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

438183

1

T1

296

T2

1

T5

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

386746

1

T3

848

T4

1565

T5

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

193111

1

T3

1210

T5

4

T13

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

201517

1

T1

80

T2

2

T3

846

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

193965

1

T1

122

T2

2

T3

641

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

203461

1

T1

130

T2

2

T3

606

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1886456

1

T2

1

T3

46

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

195342

1

T1

1030

T5

6

T13

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

194390

1

T2

2

T3

751

T13

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

200211

1

T2

2

T3

1465

T6

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

458709

1

T1

29

T3

552

T5

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

450450

1

T3

1696

T4

6801

T5

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

494651

1

T1

139

T2

1

T3

233

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

435791

1

T2

1

T3

337

T4

4161

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

555890

1

T3

467

T5

1

T14

1323

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

474656

1

T1

372

T3

667

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

479433

1

T1

320

T2

1

T5

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

417144

1

T3

859

T4

1565

T5

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

657

1

T16

10

T80

1

T8

21

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

588

1

T8

55

T25

3

T135

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1083

1

T8

8

T136

6

T119

146

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1610

1

T16

55

T8

12

T116

426

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1274

1

T80

76

T8

1

T137

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

659

1

T16

30

T80

7

T8

13

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

510

1

T20

56

T8

2

T119

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

836

1

T16

308

T80

1

T42

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

263

1

T42

20

T138

10

T85

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

360

1

T8

8

T85

38

T139

108

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1010

1

T8

838

T140

26

T141

86

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

313

1

T8

14

T25

8

T142

28

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

389

1

T16

189

T8

16

T42

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

377

1

T16

33

T137

47

T42

100

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

731

1

T8

1

T116

1

T85

480

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

94

1

T16

68

T80

1

T42

8

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

164905

1

T3

1179

T5

3

T13

2

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

168785

1

T1

80

T2

2

T3

846

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

169371

1

T1

114

T2

2

T3

633

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

175085

1

T1

129

T2

1

T3

604

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1719488

1

T2

1

T3

46

T12

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

167135

1

T1

1030

T5

2

T13

3

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

164356

1

T2

2

T3

745

T13

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

175175

1

T2

1

T3

1454

T6

11

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

427118

1

T1

26

T3

539

T5

2

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

415924

1

T3

1657

T4

6249

T5

3

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

455806

1

T1

139

T3

228

T4

3

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

402846

1

T2

1

T3

323

T4

4161

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

510788

1

T3

467

T5

1

T14

1323

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

439721

1

T1

313

T3

649

T4

1

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

438183

1

T1

296

T2

1

T5

2

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

386746

1

T3

848

T4

1565

T5

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3798

1

T3

24

T18

17

T7

12

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3785

1

T18

94

T7

14

T55

10

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3328

1

T1

1

T3

8

T18

42

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3482

1

T1

1

T3

2

T13

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

44367

1

T13

1

T18

71

T7

23

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3379

1

T5

1

T18

43

T7

5

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3408

1

T3

6

T18

53

T7

15

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3787

1

T2

1

T3

9

T18

23

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5007

1

T3

13

T18

12

T7

19

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6256

1

T3

28

T4

87

T15

68

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6555

1

T3

4

T18

9

T7

84

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5769

1

T3

12

T15

1

T18

23

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7893

1

T30

87

T18

86

T7

22

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5536

1

T1

12

T3

16

T15

109

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5898

1

T18

87

T53

92

T7

39

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5397

1

T3

9

T18

146

T7

49

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

3038

1

T3

7

T18

26

T7

10

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[1]

3084

1

T18

81

T7

4

T66

7

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[0]

2493

1

T18

35

T7

20

T54

23

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[1]

2780

1

T2

1

T19

1

T18

47

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[0]

31650

1

T18

67

T7

10

T54

13

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[1]

2757

1

T18

43

T7

5

T23

5

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[0]

2779

1

T18

41

T7

2

T54

3

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[1]

3029

1

T3

2

T18

30

T7

19

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[0]

4267

1

T18

15

T7

6

T65

99

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[1]

5144

1

T3

8

T4

75

T15

74

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[0]

5464

1

T2

1

T3

1

T18

6

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[1]

4855

1

T3

2

T18

29

T7

1

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[0]

6107

1

T30

13

T18

68

T7

6

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[1]

4444

1

T1

10

T3

1

T15

99

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

4972

1

T1

8

T18

83

T53

97

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[1]

4665

1

T3

2

T18

179

T7

33

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[0]

2333

1

T18

21

T7

1

T54

12

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[1]

2465

1

T18

72

T7

2

T66

3

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[0]

1687

1

T1

1

T18

38

T7

2

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[1]

1941

1

T18

50

T7

14

T48

8

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[0]

23896

1

T5

1

T18

70

T7

1

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[1]

1996

1

T5

1

T18

32

T7

1

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[0]

2171

1

T18

24

T54

3

T66

2

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[1]

2184

1

T18

29

T7

12

T23

14

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

3568

1

T18

14

T7

4

T65

87

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

4475

1

T3

2

T4

79

T15

72

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[0]

4559

1

T5

1

T18

6

T7

10

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

4122

1

T18

36

T7

2

T23

21

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

4870

1

T18

78

T7

2

T55

1

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

3632

1

T1

15

T3

1

T15

108

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

3985

1

T18

73

T53

95

T7

2

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

3798

1

T18

153

T7

16

T23

33

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

2088

1

T18

15

T54

16

T134

4

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

2472

1

T18

40

T7

1

T134

17

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

1770

1

T1

4

T18

29

T7

3

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2002

1

T18

55

T7

11

T55

5

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

17811

1

T18

85

T54

16

T55

3

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

1903

1

T5

1

T18

37

T23

8

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[0]

2279

1

T18

13

T54

3

T55

3

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

2308

1

T5

1

T13

1

T18

28

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

3348

1

T1

2

T18

10

T7

1

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

4203

1

T3

1

T4

85

T15

69

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

4216

1

T18

4

T7

4

T65

83

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

3906

1

T18

35

T23

11

T55

1

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

4313

1

T18

72

T7

3

T55

4

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

3421

1

T1

12

T15

104

T18

2

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4000

1

T1

6

T18

70

T53

69

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

3663

1

T18

174

T7

15

T23

35

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1675

1

T5

1

T18

17

T54

17

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1841

1

T18

37

T66

1

T134

2

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1327

1

T18

38

T54

17

T55

1

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1555

1

T18

45

T7

5

T48

6

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

12851

1

T5

1

T18

66

T54

16

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[1]

1442

1

T18

45

T23

8

T134

2

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[0]

1649

1

T18

8

T54

1

T20

5

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[1]

1482

1

T18

16

T7

3

T23

5

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[0]

2815

1

T18

18

T65

78

T43

2

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[1]

3557

1

T4

72

T15

66

T18

243

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[0]

3570

1

T18

4

T65

70

T134

4

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[1]

3219

1

T15

1

T18

25

T23

13

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3528

1

T18

47

T132

1

T131

2

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

2892

1

T1

5

T15

95

T53

84

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[0]

3283

1

T1

1

T18

71

T53

68

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[1]

2979

1

T18

151

T7

14

T23

24

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1225

1

T18

9

T54

14

T134

3

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

1729

1

T18

14

T134

2

T20

3

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1192

1

T13

1

T18

38

T7

1

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1526

1

T18

36

T7

7

T55

5

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

9094

1

T18

37

T54

17

T132

3

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1194

1

T5

1

T18

39

T23

3

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[0]

1544

1

T18

4

T54

1

T55

2

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[1]

1523

1

T18

6

T7

1

T23

1

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

2246

1

T18

10

T65

46

T76

8

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2863

1

T4

70

T15

70

T18

199

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2870

1

T18

2

T7

1

T65

65

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

2718

1

T15

1

T18

25

T23

9

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

2798

1

T18

30

T7

3

T132

1

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

2363

1

T1

3

T15

73

T18

1

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

2740

1

T1

7

T18

57

T53

47

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

2505

1

T18

122

T7

9

T23

15

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

742

1

T13

1

T18

7

T54

9

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

1132

1

T5

1

T18

12

T20

1

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

795

1

T18

25

T54

9

T132

1

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

1241

1

T18

33

T7

8

T48

9

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

5587

1

T18

25

T54

10

T134

1

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

836

1

T18

16

T23

4

T134

2

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

1015

1

T18

5

T44

1

T77

23

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

802

1

T18

4

T7

1

T23

1

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

1475

1

T18

9

T65

19

T20

1

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1846

1

T4

38

T15

48

T18

148

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1974

1

T18

1

T65

46

T134

2

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

1808

1

T15

2

T18

11

T23

7

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

1844

1

T18

24

T132

3

T131

2

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

1724

1

T1

2

T15

62

T18

1

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

1764

1

T18

41

T53

25

T134

1

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1616

1

T18

95

T7

7

T23

5