Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17483738	1			T1	1259		T2	3829		T3	20838
all_pins[1]	17483738	1			T1	1259		T2	3829		T3	20838
all_pins[2]	17483738	1			T1	1259		T2	3829		T3	20838

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44767104	1			T1	2956		T2	8856		T3	55868
values[0x1]	7684110	1			T1	821		T2	2631		T3	6646
transitions[0x0=>0x1]	7683952	1			T1	821		T2	2631		T3	6646
transitions[0x1=>0x0]	7683969	1			T1	821		T2	2631		T3	6646

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17463817	1			T1	1251		T2	3817		T3	20816
all_pins[0]	values[0x1]	19921	1			T1	8		T2	12		T3	22
all_pins[0]	transitions[0x0=>0x1]	19848	1			T1	8		T2	12		T3	22
all_pins[0]	transitions[0x1=>0x0]	7663766	1			T1	813		T2	2619		T3	6624
all_pins[1]	values[0x0]	17483371	1			T1	1259		T2	3829		T3	20838
all_pins[1]	values[0x1]	367	1			T5	1		T7	10		T43	2
all_pins[1]	transitions[0x0=>0x1]	325	1			T5	1		T7	10		T43	2
all_pins[1]	transitions[0x1=>0x0]	19879	1			T1	8		T2	12		T3	22
all_pins[2]	values[0x0]	9819916	1			T1	446		T2	1210		T3	14214
all_pins[2]	values[0x1]	7663822	1			T1	813		T2	2619		T3	6624
all_pins[2]	transitions[0x0=>0x1]	7663779	1			T1	813		T2	2619		T3	6624
all_pins[2]	transitions[0x1=>0x0]	324	1			T5	1		T7	8		T43	2