Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1016 1 T7 30 T43 7 T20 10
all_values[1] 1016 1 T7 30 T43 7 T20 10
all_values[2] 1016 1 T7 30 T43 7 T20 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1583 1 T7 36 T43 11 T20 16
auto[1] 1465 1 T7 54 T43 10 T20 14


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1105 1 T7 33 T43 6 T20 13
auto[1] 1943 1 T7 57 T43 15 T20 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1734 1 T7 51 T43 12 T20 18
auto[1] 1314 1 T7 39 T43 9 T20 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 215 1 T7 3 T20 3 T44 9
all_values[0] auto[0] auto[0] auto[1] 89 1 T7 2 T43 2 T20 2
all_values[0] auto[0] auto[1] auto[0] 185 1 T7 9 T43 2 T44 5
all_values[0] auto[0] auto[1] auto[1] 85 1 T7 2 T44 1 T80 2
all_values[0] auto[1] auto[0] auto[1] 213 1 T7 5 T43 1 T20 3
all_values[0] auto[1] auto[1] auto[1] 229 1 T7 9 T43 2 T20 2
all_values[1] auto[0] auto[0] auto[0] 162 1 T7 5 T43 2 T44 7
all_values[1] auto[0] auto[0] auto[1] 131 1 T7 2 T20 1 T44 3
all_values[1] auto[0] auto[1] auto[0] 152 1 T7 3 T43 1 T20 5
all_values[1] auto[0] auto[1] auto[1] 123 1 T7 6 T43 1 T20 1
all_values[1] auto[1] auto[0] auto[1] 231 1 T7 2 T43 1 T20 1
all_values[1] auto[1] auto[1] auto[1] 217 1 T7 12 T43 2 T20 2
all_values[2] auto[0] auto[0] auto[0] 210 1 T7 8 T43 1 T20 3
all_values[2] auto[0] auto[0] auto[1] 114 1 T7 6 T43 2 T20 1
all_values[2] auto[0] auto[1] auto[0] 181 1 T7 5 T20 2 T44 6
all_values[2] auto[0] auto[1] auto[1] 87 1 T43 1 T44 4 T80 2
all_values[2] auto[1] auto[0] auto[1] 218 1 T7 3 T43 2 T20 2
all_values[2] auto[1] auto[1] auto[1] 206 1 T7 8 T43 1 T20 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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