Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4162	1			T1	3		T2	2		T3	3
sha2_none	4089	1			T1	2		T2	4		T3	7
sha2_512	7388	1			T1	1		T2	2		T3	5
sha2_384	7208	1			T1	3		T2	4		T3	5
sha2_256	6111	1			T1	2		T2	2		T3	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18480

1

T1

5

T2

3

T3

11

auto[1]

10864

1

T1

6

T2

12

T3

18

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10856

1

T1

7

T2

8

T3

16

auto[1]

18488

1

T1

4

T2

7

T3

13

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15055

1

T1

5

T2

3

T3

11

disabled

14289

1

T1

6

T2

12

T3

18

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4493	1			T1	2		T2	2		T3	3
key_none	7685	1			T3	7		T4	2		T5	8
key_1024	4257	1			T2	2		T3	2		T4	2
key_512	3757	1			T1	2		T2	2		T3	6
key_384	3333	1			T1	3		T2	6		T3	5
key_256	2908	1			T1	1		T2	2		T3	4
key_128	2848	1			T1	3		T2	1		T3	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18486

1

T1

6

T2

7

T3

11

auto[1]

10858

1

T1

5

T2

8

T3

18

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29162

1

T1

11

T2

15

T3

29

disabled

182

1

T18

2

T7

4

T20

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1522

1

T1

1

T3

2

T5

2

enabled

auto[0]

auto[0]

auto[1]

1558

1

T3

1

T4

3

T5

4

enabled

auto[0]

auto[1]

auto[0]

1551

1

T1

1

T2

1

T3

1

enabled

auto[0]

auto[1]

auto[1]

1549

1

T2

1

T3

1

T4

4

enabled

auto[1]

auto[0]

auto[0]

4245

1

T3

1

T5

1

T14

1

enabled

auto[1]

auto[0]

auto[1]

1511

1

T1

1

T3

2

T4

1

enabled

auto[1]

auto[1]

auto[0]

1629

1

T1

2

T2

1

T5

2

enabled

auto[1]

auto[1]

auto[1]

1490

1

T3

3

T4

3

T5

1

disabled

auto[0]

auto[0]

auto[0]

1170

1

T3

1

T5

4

T13

3

disabled

auto[0]

auto[0]

auto[1]

1224

1

T1

2

T2

2

T3

3

disabled

auto[0]

auto[1]

auto[0]

1140

1

T1

2

T2

2

T3

3

disabled

auto[0]

auto[1]

auto[1]

1142

1

T1

1

T2

2

T3

4

disabled

auto[1]

auto[0]

auto[0]

6039

1

T2

1

T3

1

T12

1

disabled

auto[1]

auto[0]

auto[1]

1211

1

T1

1

T5

8

T13

7

disabled

auto[1]

auto[1]

auto[0]

1190

1

T2

2

T3

2

T13

1

disabled

auto[1]

auto[1]

auto[1]

1173

1

T2

3

T3

4

T6

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14990

1

T1

5

T2

3

T3

11

enabled

disabled

65

1

T18

1

T7

1

T20

3

disabled

disabled

117

1

T18

1

T7

3

T20

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14172

1

T1

6

T2

12

T3

18

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1070	1			T1	1		T2	1		T3	1
key_invalid	sha2_none	794	1			T2	1		T3	1		T5	4
key_invalid	sha2_512	794	1			T3	1		T4	1		T5	4
key_invalid	sha2_384	852	1			T1	1		T13	2		T14	1
key_invalid	sha2_256	879	1			T4	1		T5	2		T13	3
key_none	sha2_invalid	504	1			T3	1		T4	1		T13	1
key_none	sha2_none	541	1			T3	2		T5	1		T15	2
key_none	sha2_512	2540	1			T3	3		T5	3		T14	2
key_none	sha2_384	2524	1			T5	1		T13	1		T15	1
key_none	sha2_256	1532	1			T3	1		T4	1		T5	3
key_1024	sha2_invalid	513	1			T5	1		T13	1		T15	1
key_1024	sha2_none	574	1			T5	1		T13	1		T15	1
key_1024	sha2_512	1709	1			T4	2		T5	1		T13	1
key_1024	sha2_384	852	1			T2	2		T3	2		T5	1
key_512	sha2_invalid	533	1			T2	1		T4	1		T5	3
key_512	sha2_none	525	1			T2	1		T5	1		T13	4
key_512	sha2_512	632	1			T1	1		T13	1		T18	7
key_512	sha2_384	1181	1			T1	1		T3	2		T4	1
key_512	sha2_256	834	1			T3	2		T5	1		T13	1
key_384	sha2_invalid	528	1			T1	1		T5	3		T13	1
key_384	sha2_none	578	1			T2	1		T3	2		T5	2
key_384	sha2_512	560	1			T2	1		T3	1		T15	1
key_384	sha2_384	591	1			T2	1		T5	2		T13	1
key_384	sha2_256	1033	1			T1	2		T2	2		T3	2
key_256	sha2_invalid	496	1			T3	1		T6	1		T5	1
key_256	sha2_none	556	1			T1	1		T3	1		T4	1
key_256	sha2_512	565	1			T2	1		T5	2		T13	1
key_256	sha2_384	576	1			T2	1		T6	1		T13	2
key_256	sha2_256	669	1			T3	2		T13	1		T15	2
key_128	sha2_invalid	503	1			T1	1		T5	4		T19	2
key_128	sha2_none	510	1			T1	1		T2	1		T3	1
key_128	sha2_512	578	1			T5	4		T13	2		T15	2
key_128	sha2_384	622	1			T1	1		T3	1		T5	1
key_128	sha2_256	585	1			T4	1		T5	5		T13	7

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

565

1

T5

1

T15

1

T19

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1070	1			T1	1		T2	1		T3	1
key_invalid	sha2_none	794	1			T2	1		T3	1		T5	4
key_invalid	sha2_512	794	1			T3	1		T4	1		T5	4
key_invalid	sha2_384	852	1			T1	1		T13	2		T14	1
key_invalid	sha2_256	879	1			T4	1		T5	2		T13	3
key_none	sha2_invalid	504	1			T3	1		T4	1		T13	1
key_none	sha2_none	541	1			T3	2		T5	1		T15	2
key_none	sha2_512	2540	1			T3	3		T5	3		T14	2
key_none	sha2_384	2524	1			T5	1		T13	1		T15	1
key_none	sha2_256	1532	1			T3	1		T4	1		T5	3
key_1024	sha2_invalid	513	1			T5	1		T13	1		T15	1
key_1024	sha2_none	574	1			T5	1		T13	1		T15	1
key_1024	sha2_512	1709	1			T4	2		T5	1		T13	1
key_1024	sha2_384	852	1			T2	2		T3	2		T5	1
key_1024	sha2_256	565	1			T5	1		T15	1		T19	1
key_512	sha2_invalid	533	1			T2	1		T4	1		T5	3
key_512	sha2_none	525	1			T2	1		T5	1		T13	4
key_512	sha2_512	632	1			T1	1		T13	1		T18	7
key_512	sha2_384	1181	1			T1	1		T3	2		T4	1
key_512	sha2_256	834	1			T3	2		T5	1		T13	1
key_384	sha2_invalid	528	1			T1	1		T5	3		T13	1
key_384	sha2_none	578	1			T2	1		T3	2		T5	2
key_384	sha2_512	560	1			T2	1		T3	1		T15	1
key_384	sha2_384	591	1			T2	1		T5	2		T13	1
key_384	sha2_256	1033	1			T1	2		T2	2		T3	2
key_256	sha2_invalid	496	1			T3	1		T6	1		T5	1
key_256	sha2_none	556	1			T1	1		T3	1		T4	1
key_256	sha2_512	565	1			T2	1		T5	2		T13	1
key_256	sha2_384	576	1			T2	1		T6	1		T13	2
key_256	sha2_256	669	1			T3	2		T13	1		T15	2
key_128	sha2_invalid	503	1			T1	1		T5	4		T19	2
key_128	sha2_none	510	1			T1	1		T2	1		T3	1
key_128	sha2_512	578	1			T5	4		T13	2		T15	2
key_128	sha2_384	622	1			T1	1		T3	1		T5	1
key_128	sha2_256	585	1			T4	1		T5	5		T13	7