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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85


Total test records in report: 658
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T57 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3521906023 Aug 08 04:26:03 PM PDT 24 Aug 08 04:26:07 PM PDT 24 151491706 ps
T533 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1569126180 Aug 08 04:22:16 PM PDT 24 Aug 08 04:22:21 PM PDT 24 1658744885 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4174894280 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:32 PM PDT 24 23075149 ps
T58 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1110846488 Aug 08 04:22:18 PM PDT 24 Aug 08 04:22:22 PM PDT 24 230175060 ps
T534 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2916625205 Aug 08 04:21:45 PM PDT 24 Aug 08 04:21:48 PM PDT 24 137952022 ps
T111 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1887244442 Aug 08 04:21:29 PM PDT 24 Aug 08 04:21:32 PM PDT 24 285137194 ps
T59 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.752879519 Aug 08 04:23:57 PM PDT 24 Aug 08 04:23:59 PM PDT 24 83729074 ps
T535 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1818701083 Aug 08 04:24:04 PM PDT 24 Aug 08 04:24:05 PM PDT 24 149817438 ps
T536 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.927984885 Aug 08 04:22:26 PM PDT 24 Aug 08 04:22:28 PM PDT 24 280216789 ps
T99 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.529829377 Aug 08 04:26:17 PM PDT 24 Aug 08 04:26:18 PM PDT 24 21950561 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1720564678 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:37 PM PDT 24 1410550524 ps
T537 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1161266334 Aug 08 04:21:27 PM PDT 24 Aug 08 04:21:28 PM PDT 24 299074259 ps
T538 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1509041662 Aug 08 04:22:33 PM PDT 24 Aug 08 04:22:35 PM PDT 24 214062772 ps
T539 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3153148683 Aug 08 04:24:03 PM PDT 24 Aug 08 04:24:04 PM PDT 24 24212477 ps
T540 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.558937015 Aug 08 04:26:50 PM PDT 24 Aug 08 04:26:52 PM PDT 24 104047477 ps
T541 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1486470183 Aug 08 04:21:29 PM PDT 24 Aug 08 04:21:33 PM PDT 24 176397535 ps
T120 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1888666969 Aug 08 04:22:08 PM PDT 24 Aug 08 04:22:09 PM PDT 24 984456684 ps
T542 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2109299573 Aug 08 04:28:10 PM PDT 24 Aug 08 04:28:12 PM PDT 24 106832319 ps
T543 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2420842185 Aug 08 04:24:07 PM PDT 24 Aug 08 04:24:07 PM PDT 24 12101984 ps
T112 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4013546863 Aug 08 04:22:18 PM PDT 24 Aug 08 04:22:19 PM PDT 24 52322050 ps
T544 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3005991319 Aug 08 04:23:49 PM PDT 24 Aug 08 04:23:49 PM PDT 24 14152992 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.257958311 Aug 08 04:21:38 PM PDT 24 Aug 08 04:21:39 PM PDT 24 229552570 ps
T545 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2055037879 Aug 08 04:26:45 PM PDT 24 Aug 08 04:26:46 PM PDT 24 15083331 ps
T546 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.297592245 Aug 08 04:21:24 PM PDT 24 Aug 08 04:21:25 PM PDT 24 21561634 ps
T547 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2475454951 Aug 08 04:22:32 PM PDT 24 Aug 08 04:22:33 PM PDT 24 44092098 ps
T548 /workspace/coverage/cover_reg_top/12.hmac_intr_test.10798815 Aug 08 04:23:03 PM PDT 24 Aug 08 04:23:04 PM PDT 24 25406782 ps
T549 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3167403159 Aug 08 04:24:23 PM PDT 24 Aug 08 04:24:24 PM PDT 24 16693097 ps
T550 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3485188076 Aug 08 04:21:37 PM PDT 24 Aug 08 04:21:40 PM PDT 24 188247420 ps
T551 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3740890511 Aug 08 04:21:40 PM PDT 24 Aug 08 04:21:41 PM PDT 24 44847323 ps
T552 /workspace/coverage/cover_reg_top/11.hmac_intr_test.272714462 Aug 08 04:22:42 PM PDT 24 Aug 08 04:22:43 PM PDT 24 45588796 ps
T553 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2616346375 Aug 08 04:24:54 PM PDT 24 Aug 08 04:24:56 PM PDT 24 25126690 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3396776971 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:32 PM PDT 24 128487159 ps
T113 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.726834186 Aug 08 04:22:50 PM PDT 24 Aug 08 04:22:52 PM PDT 24 79283576 ps
T114 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1892006978 Aug 08 04:21:38 PM PDT 24 Aug 08 04:21:40 PM PDT 24 477350681 ps
T103 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.135618456 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:50 PM PDT 24 35628715 ps
T121 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2831929557 Aug 08 04:22:38 PM PDT 24 Aug 08 04:22:42 PM PDT 24 126023981 ps
T554 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2734068950 Aug 08 04:24:05 PM PDT 24 Aug 08 04:24:06 PM PDT 24 31166886 ps
T555 /workspace/coverage/cover_reg_top/40.hmac_intr_test.455791007 Aug 08 04:27:05 PM PDT 24 Aug 08 04:27:06 PM PDT 24 13129708 ps
T128 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1484523663 Aug 08 04:22:38 PM PDT 24 Aug 08 04:22:40 PM PDT 24 324713253 ps
T122 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3019369389 Aug 08 04:24:29 PM PDT 24 Aug 08 04:24:31 PM PDT 24 161386234 ps
T556 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4282922828 Aug 08 04:21:22 PM PDT 24 Aug 08 04:21:25 PM PDT 24 134128497 ps
T557 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1273788550 Aug 08 04:21:50 PM PDT 24 Aug 08 04:21:50 PM PDT 24 13345601 ps
T104 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.841991765 Aug 08 04:24:17 PM PDT 24 Aug 08 04:24:18 PM PDT 24 40315900 ps
T105 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2178967571 Aug 08 04:24:08 PM PDT 24 Aug 08 04:24:09 PM PDT 24 303368190 ps
T558 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2669860411 Aug 08 04:23:18 PM PDT 24 Aug 08 04:23:20 PM PDT 24 125154520 ps
T106 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2927858504 Aug 08 04:22:34 PM PDT 24 Aug 08 04:22:35 PM PDT 24 29783707 ps
T559 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2003474724 Aug 08 04:27:20 PM PDT 24 Aug 08 04:27:21 PM PDT 24 13168444 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3403647009 Aug 08 04:22:48 PM PDT 24 Aug 08 04:22:49 PM PDT 24 30302096 ps
T561 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3893655324 Aug 08 04:24:33 PM PDT 24 Aug 08 04:24:35 PM PDT 24 110861131 ps
T562 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2234841303 Aug 08 04:24:39 PM PDT 24 Aug 08 04:24:40 PM PDT 24 25272036 ps
T563 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.381417837 Aug 08 04:27:31 PM PDT 24 Aug 08 04:27:33 PM PDT 24 354197002 ps
T564 /workspace/coverage/cover_reg_top/13.hmac_intr_test.395079323 Aug 08 04:26:04 PM PDT 24 Aug 08 04:26:05 PM PDT 24 36284537 ps
T107 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1778921205 Aug 08 04:26:09 PM PDT 24 Aug 08 04:26:09 PM PDT 24 30317529 ps
T565 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1301521013 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:27 PM PDT 24 11666215 ps
T115 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3338349389 Aug 08 04:26:08 PM PDT 24 Aug 08 04:26:10 PM PDT 24 356126765 ps
T129 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2813755392 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:35 PM PDT 24 203903376 ps
T566 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.101823373 Aug 08 04:22:36 PM PDT 24 Aug 08 04:22:38 PM PDT 24 33887460 ps
T567 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1053978242 Aug 08 04:26:53 PM PDT 24 Aug 08 04:26:55 PM PDT 24 111993591 ps
T108 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.910969456 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:47 PM PDT 24 1610991109 ps
T568 /workspace/coverage/cover_reg_top/30.hmac_intr_test.705382669 Aug 08 04:26:19 PM PDT 24 Aug 08 04:26:20 PM PDT 24 12917749 ps
T569 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2906113677 Aug 08 04:21:37 PM PDT 24 Aug 08 04:21:38 PM PDT 24 92123616 ps
T570 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1182709274 Aug 08 04:26:43 PM PDT 24 Aug 08 04:26:44 PM PDT 24 23894979 ps
T571 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1259164628 Aug 08 04:22:35 PM PDT 24 Aug 08 04:22:36 PM PDT 24 12746301 ps
T572 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1029086068 Aug 08 04:21:44 PM PDT 24 Aug 08 04:21:45 PM PDT 24 30130943 ps
T573 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2639856134 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:30 PM PDT 24 564629914 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.49795125 Aug 08 04:22:37 PM PDT 24 Aug 08 04:22:38 PM PDT 24 91726245 ps
T574 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.429644352 Aug 08 04:22:38 PM PDT 24 Aug 08 04:22:41 PM PDT 24 299555298 ps
T575 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.258110687 Aug 08 04:23:36 PM PDT 24 Aug 08 04:23:38 PM PDT 24 367604260 ps
T576 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1190397191 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:32 PM PDT 24 156086713 ps
T577 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3829102517 Aug 08 04:21:25 PM PDT 24 Aug 08 04:21:26 PM PDT 24 29093532 ps
T578 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1053024572 Aug 08 04:22:55 PM PDT 24 Aug 08 04:22:55 PM PDT 24 12717743 ps
T579 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3201808433 Aug 08 04:23:08 PM PDT 24 Aug 08 04:42:30 PM PDT 24 469721752364 ps
T580 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.452771295 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:51 PM PDT 24 116507106 ps
T581 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2012590223 Aug 08 04:21:39 PM PDT 24 Aug 08 04:21:40 PM PDT 24 42142531 ps
T124 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4211203752 Aug 08 04:26:53 PM PDT 24 Aug 08 04:26:55 PM PDT 24 1862637542 ps
T582 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.225543756 Aug 08 04:23:52 PM PDT 24 Aug 08 04:23:54 PM PDT 24 116070994 ps
T583 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.681121608 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:28 PM PDT 24 219478344 ps
T584 /workspace/coverage/cover_reg_top/36.hmac_intr_test.952473721 Aug 08 04:21:53 PM PDT 24 Aug 08 04:21:53 PM PDT 24 16941060 ps
T585 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1540377651 Aug 08 04:26:56 PM PDT 24 Aug 08 04:26:59 PM PDT 24 543007611 ps
T586 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1816341939 Aug 08 04:23:58 PM PDT 24 Aug 08 04:23:59 PM PDT 24 45574295 ps
T587 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.765595191 Aug 08 04:24:35 PM PDT 24 Aug 08 04:24:36 PM PDT 24 239638219 ps
T588 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3477839475 Aug 08 04:21:44 PM PDT 24 Aug 08 04:21:45 PM PDT 24 32015781 ps
T589 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1985428167 Aug 08 04:21:43 PM PDT 24 Aug 08 04:21:43 PM PDT 24 12924376 ps
T590 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1949024515 Aug 08 04:23:08 PM PDT 24 Aug 08 04:23:09 PM PDT 24 144969631 ps
T127 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.842702640 Aug 08 04:23:21 PM PDT 24 Aug 08 04:23:24 PM PDT 24 755261712 ps
T591 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2411746563 Aug 08 04:27:43 PM PDT 24 Aug 08 04:27:48 PM PDT 24 157615176 ps
T592 /workspace/coverage/cover_reg_top/16.hmac_intr_test.109817925 Aug 08 04:26:04 PM PDT 24 Aug 08 04:26:05 PM PDT 24 41573172 ps
T593 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2234485361 Aug 08 04:27:45 PM PDT 24 Aug 08 04:27:46 PM PDT 24 57081085 ps
T594 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2190539489 Aug 08 04:23:37 PM PDT 24 Aug 08 04:23:38 PM PDT 24 24355792 ps
T595 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.554705272 Aug 08 04:22:12 PM PDT 24 Aug 08 04:22:13 PM PDT 24 17354299 ps
T596 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1770511895 Aug 08 04:22:55 PM PDT 24 Aug 08 04:22:57 PM PDT 24 67254613 ps
T597 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4236910975 Aug 08 04:21:33 PM PDT 24 Aug 08 04:21:45 PM PDT 24 2027539187 ps
T598 /workspace/coverage/cover_reg_top/33.hmac_intr_test.233210644 Aug 08 04:25:11 PM PDT 24 Aug 08 04:25:12 PM PDT 24 39105876 ps
T599 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3053884666 Aug 08 04:24:43 PM PDT 24 Aug 08 04:24:45 PM PDT 24 81959610 ps
T600 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3381364311 Aug 08 04:21:38 PM PDT 24 Aug 08 04:21:47 PM PDT 24 461558730 ps
T601 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1555499671 Aug 08 04:23:54 PM PDT 24 Aug 08 04:23:54 PM PDT 24 47718998 ps
T602 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3360765849 Aug 08 04:25:21 PM PDT 24 Aug 08 04:25:23 PM PDT 24 141685350 ps
T603 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2596980586 Aug 08 04:27:09 PM PDT 24 Aug 08 04:27:09 PM PDT 24 17994670 ps
T604 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1853171456 Aug 08 04:25:23 PM PDT 24 Aug 08 04:25:24 PM PDT 24 13765218 ps
T605 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1017166343 Aug 08 04:27:45 PM PDT 24 Aug 08 04:27:46 PM PDT 24 44970014 ps
T606 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.345945116 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:54 PM PDT 24 1105728053 ps
T607 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2336162804 Aug 08 04:22:32 PM PDT 24 Aug 08 04:22:32 PM PDT 24 41903513 ps
T608 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3697614294 Aug 08 04:22:33 PM PDT 24 Aug 08 04:22:36 PM PDT 24 160845849 ps
T609 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3280809703 Aug 08 04:26:19 PM PDT 24 Aug 08 04:26:19 PM PDT 24 48286064 ps
T125 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2584036184 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:51 PM PDT 24 200958768 ps
T610 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.934979677 Aug 08 04:22:30 PM PDT 24 Aug 08 04:22:31 PM PDT 24 46305518 ps
T611 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3659998778 Aug 08 04:22:35 PM PDT 24 Aug 08 04:22:37 PM PDT 24 560857465 ps
T612 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4104661634 Aug 08 04:22:48 PM PDT 24 Aug 08 04:22:51 PM PDT 24 212210258 ps
T613 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1142177184 Aug 08 04:23:23 PM PDT 24 Aug 08 04:23:24 PM PDT 24 20501667 ps
T126 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1780160987 Aug 08 04:21:37 PM PDT 24 Aug 08 04:21:39 PM PDT 24 86876405 ps
T614 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3842118074 Aug 08 04:23:22 PM PDT 24 Aug 08 04:23:23 PM PDT 24 27287551 ps
T615 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2586467305 Aug 08 04:24:54 PM PDT 24 Aug 08 04:24:56 PM PDT 24 47030160 ps
T616 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3982977510 Aug 08 04:22:50 PM PDT 24 Aug 08 04:23:00 PM PDT 24 214438154 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4093606997 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:50 PM PDT 24 20887192 ps
T618 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1630051040 Aug 08 04:25:04 PM PDT 24 Aug 08 04:25:06 PM PDT 24 49861106 ps
T619 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.235078293 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:59 PM PDT 24 710061504 ps
T123 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.855639765 Aug 08 04:23:23 PM PDT 24 Aug 08 04:23:27 PM PDT 24 1875836899 ps
T620 /workspace/coverage/cover_reg_top/43.hmac_intr_test.577806187 Aug 08 04:22:18 PM PDT 24 Aug 08 04:22:19 PM PDT 24 17279695 ps
T621 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4184226982 Aug 08 04:22:18 PM PDT 24 Aug 08 04:22:19 PM PDT 24 17043863 ps
T622 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1962558291 Aug 08 04:23:22 PM PDT 24 Aug 08 04:23:24 PM PDT 24 93953211 ps
T623 /workspace/coverage/cover_reg_top/18.hmac_intr_test.101712174 Aug 08 04:23:37 PM PDT 24 Aug 08 04:23:38 PM PDT 24 31937071 ps
T624 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1856367030 Aug 08 04:21:32 PM PDT 24 Aug 08 04:21:33 PM PDT 24 97577454 ps
T625 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2926647744 Aug 08 04:21:40 PM PDT 24 Aug 08 04:21:42 PM PDT 24 548736236 ps
T626 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2157141544 Aug 08 04:21:42 PM PDT 24 Aug 08 04:21:43 PM PDT 24 91309187 ps
T627 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4220604319 Aug 08 04:26:54 PM PDT 24 Aug 08 04:26:55 PM PDT 24 25093425 ps
T628 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1564183403 Aug 08 04:26:54 PM PDT 24 Aug 08 04:26:55 PM PDT 24 13243488 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2402089950 Aug 08 04:22:37 PM PDT 24 Aug 08 04:22:38 PM PDT 24 32671864 ps
T630 /workspace/coverage/cover_reg_top/3.hmac_intr_test.669406052 Aug 08 04:21:33 PM PDT 24 Aug 08 04:21:34 PM PDT 24 16269251 ps
T631 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1930834021 Aug 08 04:25:22 PM PDT 24 Aug 08 04:25:23 PM PDT 24 32518038 ps
T632 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3148252407 Aug 08 04:23:40 PM PDT 24 Aug 08 04:23:42 PM PDT 24 318520265 ps
T633 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4133894222 Aug 08 04:22:03 PM PDT 24 Aug 08 04:22:05 PM PDT 24 353070193 ps
T634 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2696511127 Aug 08 04:26:28 PM PDT 24 Aug 08 04:26:30 PM PDT 24 199529576 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1583463231 Aug 08 04:22:16 PM PDT 24 Aug 08 04:22:18 PM PDT 24 214334139 ps
T636 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2561265693 Aug 08 04:26:55 PM PDT 24 Aug 08 04:26:56 PM PDT 24 16011695 ps
T637 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3743626054 Aug 08 04:22:42 PM PDT 24 Aug 08 04:22:44 PM PDT 24 343524861 ps
T638 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2330294044 Aug 08 04:24:48 PM PDT 24 Aug 08 04:24:50 PM PDT 24 185611120 ps
T639 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4069315546 Aug 08 04:23:10 PM PDT 24 Aug 08 04:23:11 PM PDT 24 28049823 ps
T640 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4078454395 Aug 08 04:27:12 PM PDT 24 Aug 08 04:27:14 PM PDT 24 319930687 ps
T641 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2074440906 Aug 08 04:22:36 PM PDT 24 Aug 08 04:22:40 PM PDT 24 1183456325 ps
T642 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1670696490 Aug 08 04:21:23 PM PDT 24 Aug 08 04:21:28 PM PDT 24 909985167 ps
T643 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3820437857 Aug 08 04:22:56 PM PDT 24 Aug 08 04:22:58 PM PDT 24 524654755 ps
T644 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.219102099 Aug 08 04:23:37 PM PDT 24 Aug 08 04:23:39 PM PDT 24 44916149 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4002202712 Aug 08 04:21:26 PM PDT 24 Aug 08 04:21:27 PM PDT 24 158239050 ps
T646 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2605517235 Aug 08 04:22:16 PM PDT 24 Aug 08 04:22:17 PM PDT 24 22880489 ps
T647 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.464908342 Aug 08 04:21:59 PM PDT 24 Aug 08 04:22:00 PM PDT 24 16964801 ps
T648 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.192523119 Aug 08 04:21:27 PM PDT 24 Aug 08 04:21:35 PM PDT 24 295848307 ps
T649 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1151357869 Aug 08 04:22:16 PM PDT 24 Aug 08 04:22:18 PM PDT 24 138762685 ps
T650 /workspace/coverage/cover_reg_top/46.hmac_intr_test.936238696 Aug 08 04:23:50 PM PDT 24 Aug 08 04:23:50 PM PDT 24 13564371 ps
T651 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.48016769 Aug 08 04:21:23 PM PDT 24 Aug 08 04:21:25 PM PDT 24 201432198 ps
T652 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1706962522 Aug 08 04:23:23 PM PDT 24 Aug 08 04:23:24 PM PDT 24 79376226 ps
T130 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.314779362 Aug 08 04:24:45 PM PDT 24 Aug 08 04:24:47 PM PDT 24 330143497 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3272276031 Aug 08 04:21:33 PM PDT 24 Aug 08 04:21:36 PM PDT 24 224242326 ps
T654 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4111993169 Aug 08 04:26:38 PM PDT 24 Aug 08 04:26:40 PM PDT 24 877729290 ps
T655 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3465182543 Aug 08 04:23:38 PM PDT 24 Aug 08 04:23:39 PM PDT 24 93614736 ps
T656 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2790211660 Aug 08 04:23:35 PM PDT 24 Aug 08 04:23:36 PM PDT 24 21571636 ps
T60 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3446759525 Aug 08 04:22:18 PM PDT 24 Aug 08 04:22:21 PM PDT 24 309036257 ps
T657 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.115504161 Aug 08 04:22:49 PM PDT 24 Aug 08 04:22:51 PM PDT 24 32842535 ps
T658 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.476429197 Aug 08 04:21:31 PM PDT 24 Aug 08 04:21:33 PM PDT 24 251585909 ps

Test location /workspace/coverage/default/35.hmac_back_pressure.2812978102
Short name T5
Test name
Test status
Simulation time 1659418101 ps
CPU time 87.9 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 04:29:48 PM PDT 24
Peak memory 199668 kb
Host smart-d9ecfde5-4bba-49cf-8347-d955ba4f5d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812978102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2812978102
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.77034190
Short name T7
Test name
Test status
Simulation time 257255714668 ps
CPU time 1956.41 seconds
Started Aug 08 04:27:20 PM PDT 24
Finished Aug 08 04:59:57 PM PDT 24
Peak memory 768172 kb
Host smart-0583ade2-8591-4f87-9f4f-418dd3f3486c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77034190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.77034190
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2387447209
Short name T8
Test name
Test status
Simulation time 836749882582 ps
CPU time 3933.08 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 05:33:54 PM PDT 24
Peak memory 705780 kb
Host smart-957bcc58-4db1-4586-80f0-d7bd8392c381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387447209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2387447209
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.952378980
Short name T17
Test name
Test status
Simulation time 166217179754 ps
CPU time 3403.04 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 05:25:01 PM PDT 24
Peak memory 801496 kb
Host smart-11dfcad0-aa14-4de4-bb3e-18e2bdb3ce71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952378980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.952378980
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1110846488
Short name T58
Test name
Test status
Simulation time 230175060 ps
CPU time 4.45 seconds
Started Aug 08 04:22:18 PM PDT 24
Finished Aug 08 04:22:22 PM PDT 24
Peak memory 199952 kb
Host smart-8fe5dd86-9c6b-4c4f-85b8-f6d5d96e8d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110846488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1110846488
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.785919783
Short name T31
Test name
Test status
Simulation time 310413604 ps
CPU time 0.95 seconds
Started Aug 08 04:27:17 PM PDT 24
Finished Aug 08 04:27:18 PM PDT 24
Peak memory 219092 kb
Host smart-b3668323-f4c7-409e-8763-6016fa6af093
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785919783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.785919783
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3461053263
Short name T18
Test name
Test status
Simulation time 18430474224 ps
CPU time 1863.36 seconds
Started Aug 08 04:28:34 PM PDT 24
Finished Aug 08 04:59:37 PM PDT 24
Peak memory 783668 kb
Host smart-d01aa756-c958-4db5-ae35-dee71d268de8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461053263 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3461053263
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.360194313
Short name T10
Test name
Test status
Simulation time 22040844035 ps
CPU time 73.13 seconds
Started Aug 08 04:27:32 PM PDT 24
Finished Aug 08 04:28:45 PM PDT 24
Peak memory 199672 kb
Host smart-a9a95644-494e-4f13-ba6a-090d6f4477b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360194313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.360194313
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1950892726
Short name T16
Test name
Test status
Simulation time 4599034570 ps
CPU time 64.06 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:30:03 PM PDT 24
Peak memory 215872 kb
Host smart-bb894a45-8ead-4a72-99cb-806e6ce81d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950892726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1950892726
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_alert_test.977499233
Short name T47
Test name
Test status
Simulation time 23073824 ps
CPU time 0.55 seconds
Started Aug 08 04:27:13 PM PDT 24
Finished Aug 08 04:27:13 PM PDT 24
Peak memory 195440 kb
Host smart-7f2be820-9d4a-402a-ad2b-efa28fb134ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977499233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.977499233
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2927858504
Short name T106
Test name
Test status
Simulation time 29783707 ps
CPU time 0.87 seconds
Started Aug 08 04:22:34 PM PDT 24
Finished Aug 08 04:22:35 PM PDT 24
Peak memory 199104 kb
Host smart-108b3984-c338-41ae-a7bb-3a606aec7bfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927858504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2927858504
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.855639765
Short name T123
Test name
Test status
Simulation time 1875836899 ps
CPU time 4.06 seconds
Started Aug 08 04:23:23 PM PDT 24
Finished Aug 08 04:23:27 PM PDT 24
Peak memory 200068 kb
Host smart-642346a6-0133-49ee-b4b6-93e6bde85b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855639765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.855639765
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.24911093
Short name T9
Test name
Test status
Simulation time 262025271516 ps
CPU time 387.96 seconds
Started Aug 08 04:27:17 PM PDT 24
Finished Aug 08 04:33:45 PM PDT 24
Peak memory 583108 kb
Host smart-be747ae6-175d-4f17-a778-2d650203ef5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24911093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.24911093
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4211203752
Short name T124
Test name
Test status
Simulation time 1862637542 ps
CPU time 1.83 seconds
Started Aug 08 04:26:53 PM PDT 24
Finished Aug 08 04:26:55 PM PDT 24
Peak memory 198584 kb
Host smart-8fb76dac-e193-4717-9d5b-c36c69d2d106
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211203752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4211203752
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3906703458
Short name T30
Test name
Test status
Simulation time 170886152490 ps
CPU time 131.3 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 199616 kb
Host smart-bf6ede96-12ce-4d72-b937-fd4d24d185aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3906703458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3906703458
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.61180799
Short name T133
Test name
Test status
Simulation time 78177515858 ps
CPU time 56.73 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:29:02 PM PDT 24
Peak memory 199960 kb
Host smart-d61bcad1-1243-4237-af14-ea444f18c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61180799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.61180799
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3446759525
Short name T60
Test name
Test status
Simulation time 309036257 ps
CPU time 2.86 seconds
Started Aug 08 04:22:18 PM PDT 24
Finished Aug 08 04:22:21 PM PDT 24
Peak memory 199956 kb
Host smart-e3d5500b-481a-4334-820e-b1550b931f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446759525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3446759525
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3381364311
Short name T600
Test name
Test status
Simulation time 461558730 ps
CPU time 9.1 seconds
Started Aug 08 04:21:38 PM PDT 24
Finished Aug 08 04:21:47 PM PDT 24
Peak memory 200060 kb
Host smart-3814b006-e5fd-45e9-8a86-f6c4f6c792e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381364311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3381364311
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3982977510
Short name T616
Test name
Test status
Simulation time 214438154 ps
CPU time 9.77 seconds
Started Aug 08 04:22:50 PM PDT 24
Finished Aug 08 04:23:00 PM PDT 24
Peak memory 199960 kb
Host smart-97afc707-e209-454a-8e3c-7a52723d2095
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982977510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3982977510
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1161266334
Short name T537
Test name
Test status
Simulation time 299074259 ps
CPU time 0.88 seconds
Started Aug 08 04:21:27 PM PDT 24
Finished Aug 08 04:21:28 PM PDT 24
Peak memory 198824 kb
Host smart-ea77f118-a752-4776-9bdd-b0439f778182
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161266334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1161266334
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.48016769
Short name T651
Test name
Test status
Simulation time 201432198 ps
CPU time 1.17 seconds
Started Aug 08 04:21:23 PM PDT 24
Finished Aug 08 04:21:25 PM PDT 24
Peak memory 198036 kb
Host smart-ea02c942-819d-43d0-a134-8de9bf31e27d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48016769 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.48016769
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.257958311
Short name T101
Test name
Test status
Simulation time 229552570 ps
CPU time 0.85 seconds
Started Aug 08 04:21:38 PM PDT 24
Finished Aug 08 04:21:39 PM PDT 24
Peak memory 200216 kb
Host smart-2fadb1c6-f3bf-484c-b127-635a45aa7b04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257958311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.257958311
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3829102517
Short name T577
Test name
Test status
Simulation time 29093532 ps
CPU time 0.61 seconds
Started Aug 08 04:21:25 PM PDT 24
Finished Aug 08 04:21:26 PM PDT 24
Peak memory 193744 kb
Host smart-50c55a2e-e31c-409c-83e4-3df4d72ae58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829102517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3829102517
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.726834186
Short name T113
Test name
Test status
Simulation time 79283576 ps
CPU time 1.1 seconds
Started Aug 08 04:22:50 PM PDT 24
Finished Aug 08 04:22:52 PM PDT 24
Peak memory 199812 kb
Host smart-846c2bc5-b9b0-4f09-936e-468a72d2281a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726834186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.726834186
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2074440906
Short name T641
Test name
Test status
Simulation time 1183456325 ps
CPU time 3.27 seconds
Started Aug 08 04:22:36 PM PDT 24
Finished Aug 08 04:22:40 PM PDT 24
Peak memory 199020 kb
Host smart-9c748305-9e37-4a59-acb4-955405493940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074440906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2074440906
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.345945116
Short name T606
Test name
Test status
Simulation time 1105728053 ps
CPU time 4.57 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:54 PM PDT 24
Peak memory 199948 kb
Host smart-9f1ebbe8-fdac-4c8c-ae6c-f789dd3bb254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345945116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.345945116
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2639856134
Short name T573
Test name
Test status
Simulation time 564629914 ps
CPU time 3.26 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:30 PM PDT 24
Peak memory 199032 kb
Host smart-17e0fca3-b463-4d63-a90a-d14f17189441
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639856134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2639856134
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.235078293
Short name T619
Test name
Test status
Simulation time 710061504 ps
CPU time 10.37 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:59 PM PDT 24
Peak memory 199984 kb
Host smart-756e3547-9cdf-452c-8b84-ee20513d32f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235078293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.235078293
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4174894280
Short name T98
Test name
Test status
Simulation time 23075149 ps
CPU time 1.05 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:32 PM PDT 24
Peak memory 197280 kb
Host smart-fd5ef8b1-775a-4e57-83f8-6c8c02305e16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174894280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4174894280
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3868071849
Short name T63
Test name
Test status
Simulation time 153933646 ps
CPU time 1.21 seconds
Started Aug 08 04:21:39 PM PDT 24
Finished Aug 08 04:21:41 PM PDT 24
Peak memory 200044 kb
Host smart-8d9248f5-ea60-4440-abee-eb1fdf8a55b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868071849 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3868071849
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1716050303
Short name T110
Test name
Test status
Simulation time 96105140 ps
CPU time 0.86 seconds
Started Aug 08 04:21:38 PM PDT 24
Finished Aug 08 04:21:39 PM PDT 24
Peak memory 199588 kb
Host smart-ad72a4ca-85d3-4844-a2aa-4423f39976c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716050303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1716050303
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3403647009
Short name T560
Test name
Test status
Simulation time 30302096 ps
CPU time 0.66 seconds
Started Aug 08 04:22:48 PM PDT 24
Finished Aug 08 04:22:49 PM PDT 24
Peak memory 194856 kb
Host smart-43529c57-4b15-4833-9943-c739b55811e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403647009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3403647009
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4002202712
Short name T645
Test name
Test status
Simulation time 158239050 ps
CPU time 1.2 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:27 PM PDT 24
Peak memory 199032 kb
Host smart-7643d268-57a5-4220-b9ee-c7bf6e4c500a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002202712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4002202712
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.476429197
Short name T658
Test name
Test status
Simulation time 251585909 ps
CPU time 2.49 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:33 PM PDT 24
Peak memory 197984 kb
Host smart-8e61e860-644f-479b-bfb7-663dcfb4c727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476429197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.476429197
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1780160987
Short name T126
Test name
Test status
Simulation time 86876405 ps
CPU time 1.75 seconds
Started Aug 08 04:21:37 PM PDT 24
Finished Aug 08 04:21:39 PM PDT 24
Peak memory 200356 kb
Host smart-62688f56-57ea-4e31-8054-83079aa6d7db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780160987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1780160987
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3360765849
Short name T602
Test name
Test status
Simulation time 141685350 ps
CPU time 1.83 seconds
Started Aug 08 04:25:21 PM PDT 24
Finished Aug 08 04:25:23 PM PDT 24
Peak memory 200036 kb
Host smart-c1d28f34-c330-4080-9de4-76f26e233441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360765849 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3360765849
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1930834021
Short name T631
Test name
Test status
Simulation time 32518038 ps
CPU time 0.91 seconds
Started Aug 08 04:25:22 PM PDT 24
Finished Aug 08 04:25:23 PM PDT 24
Peak memory 199528 kb
Host smart-832cd418-ecc9-4c7c-894e-3c652a979b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930834021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1930834021
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1853171456
Short name T604
Test name
Test status
Simulation time 13765218 ps
CPU time 0.65 seconds
Started Aug 08 04:25:23 PM PDT 24
Finished Aug 08 04:25:24 PM PDT 24
Peak memory 194784 kb
Host smart-bbd58f6b-81d7-4173-8346-02081f8ee7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853171456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1853171456
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1151357869
Short name T649
Test name
Test status
Simulation time 138762685 ps
CPU time 1.68 seconds
Started Aug 08 04:22:16 PM PDT 24
Finished Aug 08 04:22:18 PM PDT 24
Peak memory 200056 kb
Host smart-c6d7e00a-e282-41ce-9a6a-bb981d59fc9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151357869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1151357869
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1583463231
Short name T635
Test name
Test status
Simulation time 214334139 ps
CPU time 1.47 seconds
Started Aug 08 04:22:16 PM PDT 24
Finished Aug 08 04:22:18 PM PDT 24
Peak memory 199928 kb
Host smart-821c7acc-92c8-435a-805d-9561de981926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583463231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1583463231
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2696511127
Short name T634
Test name
Test status
Simulation time 199529576 ps
CPU time 1.69 seconds
Started Aug 08 04:26:28 PM PDT 24
Finished Aug 08 04:26:30 PM PDT 24
Peak memory 199584 kb
Host smart-855bec6b-bd28-4fe2-815a-518902760da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696511127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2696511127
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.381417837
Short name T563
Test name
Test status
Simulation time 354197002 ps
CPU time 2.2 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:27:33 PM PDT 24
Peak memory 200040 kb
Host smart-855a3d74-e9b3-4291-bb97-8792db03845e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381417837 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.381417837
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2234485361
Short name T593
Test name
Test status
Simulation time 57081085 ps
CPU time 0.89 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:46 PM PDT 24
Peak memory 199568 kb
Host smart-577b8100-ef2c-4aba-a3a1-f48b43dd320f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234485361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2234485361
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.272714462
Short name T552
Test name
Test status
Simulation time 45588796 ps
CPU time 0.65 seconds
Started Aug 08 04:22:42 PM PDT 24
Finished Aug 08 04:22:43 PM PDT 24
Peak memory 194852 kb
Host smart-bf072ce5-8f54-4d98-8578-c942d9b49738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272714462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.272714462
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2586467305
Short name T615
Test name
Test status
Simulation time 47030160 ps
CPU time 2 seconds
Started Aug 08 04:24:54 PM PDT 24
Finished Aug 08 04:24:56 PM PDT 24
Peak memory 200052 kb
Host smart-54b9f4d7-50ae-46ea-b420-39780cf28fdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586467305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2586467305
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3659998778
Short name T611
Test name
Test status
Simulation time 560857465 ps
CPU time 2.47 seconds
Started Aug 08 04:22:35 PM PDT 24
Finished Aug 08 04:22:37 PM PDT 24
Peak memory 200048 kb
Host smart-fc6d231b-bf20-4455-8f66-20ea41ab7f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659998778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3659998778
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4111993169
Short name T654
Test name
Test status
Simulation time 877729290 ps
CPU time 1.82 seconds
Started Aug 08 04:26:38 PM PDT 24
Finished Aug 08 04:26:40 PM PDT 24
Peak memory 199492 kb
Host smart-a8c70326-fccd-4f88-accd-893960804f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111993169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4111993169
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2616346375
Short name T553
Test name
Test status
Simulation time 25126690 ps
CPU time 1.51 seconds
Started Aug 08 04:24:54 PM PDT 24
Finished Aug 08 04:24:56 PM PDT 24
Peak memory 199980 kb
Host smart-7996cf1c-acbb-4d57-b821-65e6b9092757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616346375 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2616346375
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4013546863
Short name T112
Test name
Test status
Simulation time 52322050 ps
CPU time 0.77 seconds
Started Aug 08 04:22:18 PM PDT 24
Finished Aug 08 04:22:19 PM PDT 24
Peak memory 197836 kb
Host smart-8c17fed8-a09d-4c79-ae7e-ce3cc3aec9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013546863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4013546863
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.10798815
Short name T548
Test name
Test status
Simulation time 25406782 ps
CPU time 0.64 seconds
Started Aug 08 04:23:03 PM PDT 24
Finished Aug 08 04:23:04 PM PDT 24
Peak memory 194916 kb
Host smart-b6b14c5e-e288-4e5d-b316-3bb3bd5dec05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10798815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.10798815
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.258110687
Short name T575
Test name
Test status
Simulation time 367604260 ps
CPU time 1.9 seconds
Started Aug 08 04:23:36 PM PDT 24
Finished Aug 08 04:23:38 PM PDT 24
Peak memory 199996 kb
Host smart-c7dd13ea-de7d-4977-a505-5d74237e00b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258110687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.258110687
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1630051040
Short name T618
Test name
Test status
Simulation time 49861106 ps
CPU time 2.01 seconds
Started Aug 08 04:25:04 PM PDT 24
Finished Aug 08 04:25:06 PM PDT 24
Peak memory 200004 kb
Host smart-c48f375e-6782-4d77-b4e7-f146fcfa1ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630051040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1630051040
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3521906023
Short name T57
Test name
Test status
Simulation time 151491706 ps
CPU time 2.97 seconds
Started Aug 08 04:26:03 PM PDT 24
Finished Aug 08 04:26:07 PM PDT 24
Peak memory 199004 kb
Host smart-dc56d191-52be-4618-9934-c8217e5c68c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521906023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3521906023
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3053884666
Short name T599
Test name
Test status
Simulation time 81959610 ps
CPU time 1.88 seconds
Started Aug 08 04:24:43 PM PDT 24
Finished Aug 08 04:24:45 PM PDT 24
Peak memory 200000 kb
Host smart-f90308ae-2850-4302-af6e-5230ae463efa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053884666 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3053884666
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2336162804
Short name T607
Test name
Test status
Simulation time 41903513 ps
CPU time 0.74 seconds
Started Aug 08 04:22:32 PM PDT 24
Finished Aug 08 04:22:32 PM PDT 24
Peak memory 197936 kb
Host smart-595c4f4d-b342-4f66-b784-d2fd020561cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336162804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2336162804
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.395079323
Short name T564
Test name
Test status
Simulation time 36284537 ps
CPU time 0.62 seconds
Started Aug 08 04:26:04 PM PDT 24
Finished Aug 08 04:26:05 PM PDT 24
Peak memory 193804 kb
Host smart-27cd2496-ba36-4052-8a1e-6edc23b694c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395079323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.395079323
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1706962522
Short name T652
Test name
Test status
Simulation time 79376226 ps
CPU time 1.1 seconds
Started Aug 08 04:23:23 PM PDT 24
Finished Aug 08 04:23:24 PM PDT 24
Peak memory 199944 kb
Host smart-3cfe517b-f21a-4b3b-8c49-779c0e9be3ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706962522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1706962522
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2411746563
Short name T591
Test name
Test status
Simulation time 157615176 ps
CPU time 3.94 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:27:48 PM PDT 24
Peak memory 199600 kb
Host smart-73087bf0-6080-48f1-b1ac-4ceaddc3ca48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411746563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2411746563
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.314779362
Short name T130
Test name
Test status
Simulation time 330143497 ps
CPU time 1.94 seconds
Started Aug 08 04:24:45 PM PDT 24
Finished Aug 08 04:24:47 PM PDT 24
Peak memory 199952 kb
Host smart-7016df45-2edd-4c7e-a853-116cfa6bf4a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314779362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.314779362
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1770511895
Short name T596
Test name
Test status
Simulation time 67254613 ps
CPU time 2.5 seconds
Started Aug 08 04:22:55 PM PDT 24
Finished Aug 08 04:22:57 PM PDT 24
Peak memory 208248 kb
Host smart-92450ce2-7495-497e-9acd-139171cb35a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770511895 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1770511895
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3465182543
Short name T655
Test name
Test status
Simulation time 93614736 ps
CPU time 0.86 seconds
Started Aug 08 04:23:38 PM PDT 24
Finished Aug 08 04:23:39 PM PDT 24
Peak memory 199160 kb
Host smart-74050bb5-72c2-48ac-9a9e-f06a38fa96fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465182543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3465182543
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1524566062
Short name T531
Test name
Test status
Simulation time 13851737 ps
CPU time 0.6 seconds
Started Aug 08 04:22:28 PM PDT 24
Finished Aug 08 04:22:29 PM PDT 24
Peak memory 194852 kb
Host smart-2394f63d-0c6f-4086-877d-ecaf09384e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524566062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1524566062
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4133894222
Short name T633
Test name
Test status
Simulation time 353070193 ps
CPU time 1.6 seconds
Started Aug 08 04:22:03 PM PDT 24
Finished Aug 08 04:22:05 PM PDT 24
Peak memory 199976 kb
Host smart-f019d6e9-bae9-416a-b68d-b3ae90b7e500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133894222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4133894222
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3893655324
Short name T561
Test name
Test status
Simulation time 110861131 ps
CPU time 2.47 seconds
Started Aug 08 04:24:33 PM PDT 24
Finished Aug 08 04:24:35 PM PDT 24
Peak memory 200056 kb
Host smart-e484b29f-bc13-4de7-bea9-3e15e768c060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893655324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3893655324
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1888666969
Short name T120
Test name
Test status
Simulation time 984456684 ps
CPU time 1.69 seconds
Started Aug 08 04:22:08 PM PDT 24
Finished Aug 08 04:22:09 PM PDT 24
Peak memory 200000 kb
Host smart-039005b3-c743-4423-97a3-8c6031cd26d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888666969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1888666969
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1962558291
Short name T622
Test name
Test status
Simulation time 93953211 ps
CPU time 1.84 seconds
Started Aug 08 04:23:22 PM PDT 24
Finished Aug 08 04:23:24 PM PDT 24
Peak memory 199984 kb
Host smart-efd18d3d-ad41-4a99-bc37-314a6222a933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962558291 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1962558291
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3814060177
Short name T529
Test name
Test status
Simulation time 28752447 ps
CPU time 0.66 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:45 PM PDT 24
Peak memory 197296 kb
Host smart-aa31e8a2-dedd-4a97-9bed-6124f929f131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814060177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3814060177
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1555499671
Short name T601
Test name
Test status
Simulation time 47718998 ps
CPU time 0.64 seconds
Started Aug 08 04:23:54 PM PDT 24
Finished Aug 08 04:23:54 PM PDT 24
Peak memory 195288 kb
Host smart-def30263-cfe4-4b80-8b87-6071a414eaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555499671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1555499671
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1142177184
Short name T613
Test name
Test status
Simulation time 20501667 ps
CPU time 1.1 seconds
Started Aug 08 04:23:23 PM PDT 24
Finished Aug 08 04:23:24 PM PDT 24
Peak memory 198652 kb
Host smart-943706ec-9a6c-433f-8775-fc3a0e7af55c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142177184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1142177184
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.219102099
Short name T644
Test name
Test status
Simulation time 44916149 ps
CPU time 1.86 seconds
Started Aug 08 04:23:37 PM PDT 24
Finished Aug 08 04:23:39 PM PDT 24
Peak memory 200044 kb
Host smart-465ecb5c-2af1-46ee-91e3-347ae3050f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219102099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.219102099
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.752879519
Short name T59
Test name
Test status
Simulation time 83729074 ps
CPU time 1.84 seconds
Started Aug 08 04:23:57 PM PDT 24
Finished Aug 08 04:23:59 PM PDT 24
Peak memory 200028 kb
Host smart-cd4ea1e6-a266-40da-bb39-61c3d143779c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752879519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.752879519
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3201808433
Short name T579
Test name
Test status
Simulation time 469721752364 ps
CPU time 1161.93 seconds
Started Aug 08 04:23:08 PM PDT 24
Finished Aug 08 04:42:30 PM PDT 24
Peak memory 224704 kb
Host smart-7fd2bcb2-7a21-4cd7-80cc-856a4b272383
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201808433 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3201808433
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.529829377
Short name T99
Test name
Test status
Simulation time 21950561 ps
CPU time 0.71 seconds
Started Aug 08 04:26:17 PM PDT 24
Finished Aug 08 04:26:18 PM PDT 24
Peak memory 198024 kb
Host smart-ebe02169-c102-411f-9197-decb4780212c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529829377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.529829377
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.109817925
Short name T592
Test name
Test status
Simulation time 41573172 ps
CPU time 0.59 seconds
Started Aug 08 04:26:04 PM PDT 24
Finished Aug 08 04:26:05 PM PDT 24
Peak memory 193716 kb
Host smart-1bdf83f4-d8bf-4ca2-8e9f-9412402476b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109817925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.109817925
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.765595191
Short name T587
Test name
Test status
Simulation time 239638219 ps
CPU time 1.2 seconds
Started Aug 08 04:24:35 PM PDT 24
Finished Aug 08 04:24:36 PM PDT 24
Peak memory 200028 kb
Host smart-7286c8db-2082-4ecf-a5d5-a64ecde7b45e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765595191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.765595191
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2109299573
Short name T542
Test name
Test status
Simulation time 106832319 ps
CPU time 1.57 seconds
Started Aug 08 04:28:10 PM PDT 24
Finished Aug 08 04:28:12 PM PDT 24
Peak memory 200068 kb
Host smart-4ed4a447-550c-430a-9f71-7ff2562c94ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109299573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2109299573
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3019369389
Short name T122
Test name
Test status
Simulation time 161386234 ps
CPU time 2.01 seconds
Started Aug 08 04:24:29 PM PDT 24
Finished Aug 08 04:24:31 PM PDT 24
Peak memory 199976 kb
Host smart-5552b337-df97-4624-a39e-c065b5ac548f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019369389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3019369389
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2790211660
Short name T656
Test name
Test status
Simulation time 21571636 ps
CPU time 1.29 seconds
Started Aug 08 04:23:35 PM PDT 24
Finished Aug 08 04:23:36 PM PDT 24
Peak memory 199944 kb
Host smart-ece84dda-1d1c-4347-a315-63da0e50f5db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790211660 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2790211660
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1949024515
Short name T590
Test name
Test status
Simulation time 144969631 ps
CPU time 0.82 seconds
Started Aug 08 04:23:08 PM PDT 24
Finished Aug 08 04:23:09 PM PDT 24
Peak memory 199340 kb
Host smart-e9fbc6d8-dafc-44bd-9fc5-cb3a4edd7e17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949024515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1949024515
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3167403159
Short name T549
Test name
Test status
Simulation time 16693097 ps
CPU time 0.67 seconds
Started Aug 08 04:24:23 PM PDT 24
Finished Aug 08 04:24:24 PM PDT 24
Peak memory 194972 kb
Host smart-fca7ff4f-f622-4df5-aaf3-197a54aca0bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167403159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3167403159
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4220604319
Short name T627
Test name
Test status
Simulation time 25093425 ps
CPU time 1.07 seconds
Started Aug 08 04:26:54 PM PDT 24
Finished Aug 08 04:26:55 PM PDT 24
Peak memory 199728 kb
Host smart-580a7d72-5157-4584-a6f1-a6f3de4aeb36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220604319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4220604319
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.927984885
Short name T536
Test name
Test status
Simulation time 280216789 ps
CPU time 1.75 seconds
Started Aug 08 04:22:26 PM PDT 24
Finished Aug 08 04:22:28 PM PDT 24
Peak memory 200032 kb
Host smart-02d7ea61-c6ba-4bb6-89fc-3c809814e2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927984885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.927984885
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.842702640
Short name T127
Test name
Test status
Simulation time 755261712 ps
CPU time 2.89 seconds
Started Aug 08 04:23:21 PM PDT 24
Finished Aug 08 04:23:24 PM PDT 24
Peak memory 199984 kb
Host smart-09d475ea-6f05-4693-93c8-5714c77f8c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842702640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.842702640
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3052973783
Short name T532
Test name
Test status
Simulation time 770479291 ps
CPU time 2.57 seconds
Started Aug 08 04:23:22 PM PDT 24
Finished Aug 08 04:23:24 PM PDT 24
Peak memory 200024 kb
Host smart-08f76ba8-2bf1-4b7f-ae74-8acc26b1fd77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052973783 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3052973783
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.934979677
Short name T610
Test name
Test status
Simulation time 46305518 ps
CPU time 0.69 seconds
Started Aug 08 04:22:30 PM PDT 24
Finished Aug 08 04:22:31 PM PDT 24
Peak memory 198352 kb
Host smart-7bf39bc4-a593-481d-8e87-85b237c1f703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934979677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.934979677
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.101712174
Short name T623
Test name
Test status
Simulation time 31937071 ps
CPU time 0.6 seconds
Started Aug 08 04:23:37 PM PDT 24
Finished Aug 08 04:23:38 PM PDT 24
Peak memory 194868 kb
Host smart-4e10d3b0-c444-4179-98eb-cb7049559350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101712174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.101712174
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1053978242
Short name T567
Test name
Test status
Simulation time 111993591 ps
CPU time 1.25 seconds
Started Aug 08 04:26:53 PM PDT 24
Finished Aug 08 04:26:55 PM PDT 24
Peak memory 198532 kb
Host smart-2649abbe-d84c-4523-bbe0-94e1775fff6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053978242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1053978242
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1540377651
Short name T585
Test name
Test status
Simulation time 543007611 ps
CPU time 2.56 seconds
Started Aug 08 04:26:56 PM PDT 24
Finished Aug 08 04:26:59 PM PDT 24
Peak memory 199072 kb
Host smart-4b8f9203-7cba-427f-a467-bbb6dac5ada2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540377651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1540377651
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2330294044
Short name T638
Test name
Test status
Simulation time 185611120 ps
CPU time 1.1 seconds
Started Aug 08 04:24:48 PM PDT 24
Finished Aug 08 04:24:50 PM PDT 24
Peak memory 199880 kb
Host smart-18f5ac6e-34e9-4a88-ad31-d764d1e53d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330294044 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2330294044
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.558937015
Short name T540
Test name
Test status
Simulation time 104047477 ps
CPU time 0.93 seconds
Started Aug 08 04:26:50 PM PDT 24
Finished Aug 08 04:26:52 PM PDT 24
Peak memory 198520 kb
Host smart-5215abe6-9ad2-409b-ba0c-2ab725b57340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558937015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.558937015
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2561265693
Short name T636
Test name
Test status
Simulation time 16011695 ps
CPU time 0.56 seconds
Started Aug 08 04:26:55 PM PDT 24
Finished Aug 08 04:26:56 PM PDT 24
Peak memory 194448 kb
Host smart-02b21034-de46-4880-9d38-c5cd3a2b42f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561265693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2561265693
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.225543756
Short name T582
Test name
Test status
Simulation time 116070994 ps
CPU time 1.5 seconds
Started Aug 08 04:23:52 PM PDT 24
Finished Aug 08 04:23:54 PM PDT 24
Peak memory 199948 kb
Host smart-ea6f9ef6-945a-4187-ae45-c3e38129f9d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225543756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.225543756
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2669860411
Short name T558
Test name
Test status
Simulation time 125154520 ps
CPU time 1.49 seconds
Started Aug 08 04:23:18 PM PDT 24
Finished Aug 08 04:23:20 PM PDT 24
Peak memory 199948 kb
Host smart-cdc9fbf6-2709-4c50-87ff-ce3a7fd2196d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669860411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2669860411
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.192523119
Short name T648
Test name
Test status
Simulation time 295848307 ps
CPU time 8.1 seconds
Started Aug 08 04:21:27 PM PDT 24
Finished Aug 08 04:21:35 PM PDT 24
Peak memory 199548 kb
Host smart-91168029-d399-4d42-bb01-8e2f6243223c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192523119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.192523119
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4236910975
Short name T597
Test name
Test status
Simulation time 2027539187 ps
CPU time 11.51 seconds
Started Aug 08 04:21:33 PM PDT 24
Finished Aug 08 04:21:45 PM PDT 24
Peak memory 199784 kb
Host smart-6da22bba-1be0-4191-9da5-f53436dfc4af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236910975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4236910975
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3396776971
Short name T102
Test name
Test status
Simulation time 128487159 ps
CPU time 1.06 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:32 PM PDT 24
Peak memory 197824 kb
Host smart-b23785a2-922e-4fd1-baa1-46373acc4606
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396776971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3396776971
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.297592245
Short name T546
Test name
Test status
Simulation time 21561634 ps
CPU time 1.15 seconds
Started Aug 08 04:21:24 PM PDT 24
Finished Aug 08 04:21:25 PM PDT 24
Peak memory 199048 kb
Host smart-3f6bc13c-ea2d-4c5c-a400-600925ac16d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297592245 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.297592245
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.464908342
Short name T647
Test name
Test status
Simulation time 16964801 ps
CPU time 0.73 seconds
Started Aug 08 04:21:59 PM PDT 24
Finished Aug 08 04:22:00 PM PDT 24
Peak memory 198044 kb
Host smart-83faede3-7979-4d1b-bed6-6c6e049e4d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464908342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.464908342
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4093606997
Short name T617
Test name
Test status
Simulation time 20887192 ps
CPU time 0.61 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:50 PM PDT 24
Peak memory 194888 kb
Host smart-ba90d317-1c8b-4f6f-b70c-888ace7ca560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093606997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4093606997
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1887244442
Short name T111
Test name
Test status
Simulation time 285137194 ps
CPU time 2.42 seconds
Started Aug 08 04:21:29 PM PDT 24
Finished Aug 08 04:21:32 PM PDT 24
Peak memory 198964 kb
Host smart-d982ccd2-9c65-43f6-93bf-d17957f25aae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887244442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1887244442
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1486470183
Short name T541
Test name
Test status
Simulation time 176397535 ps
CPU time 3.72 seconds
Started Aug 08 04:21:29 PM PDT 24
Finished Aug 08 04:21:33 PM PDT 24
Peak memory 198904 kb
Host smart-4555fc7a-a462-47cc-b717-3b7f95232af4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486470183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1486470183
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2831929557
Short name T121
Test name
Test status
Simulation time 126023981 ps
CPU time 3.71 seconds
Started Aug 08 04:22:38 PM PDT 24
Finished Aug 08 04:22:42 PM PDT 24
Peak memory 199780 kb
Host smart-87285ead-6744-402c-8f88-df11dcbef651
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831929557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2831929557
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1818701083
Short name T535
Test name
Test status
Simulation time 149817438 ps
CPU time 0.68 seconds
Started Aug 08 04:24:04 PM PDT 24
Finished Aug 08 04:24:05 PM PDT 24
Peak memory 194880 kb
Host smart-26a434a4-a6a3-485f-92c6-c9442b485cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818701083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1818701083
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4069315546
Short name T639
Test name
Test status
Simulation time 28049823 ps
CPU time 0.62 seconds
Started Aug 08 04:23:10 PM PDT 24
Finished Aug 08 04:23:11 PM PDT 24
Peak memory 195236 kb
Host smart-6179c75f-af38-42d6-b764-6a9eb45ca491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069315546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4069315546
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1273788550
Short name T557
Test name
Test status
Simulation time 13345601 ps
CPU time 0.6 seconds
Started Aug 08 04:21:50 PM PDT 24
Finished Aug 08 04:21:50 PM PDT 24
Peak memory 194836 kb
Host smart-a4cb8f88-03e0-4bd7-9485-48c7d7fae04c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273788550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1273788550
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2420842185
Short name T543
Test name
Test status
Simulation time 12101984 ps
CPU time 0.58 seconds
Started Aug 08 04:24:07 PM PDT 24
Finished Aug 08 04:24:07 PM PDT 24
Peak memory 194880 kb
Host smart-e5fd4711-9cf1-4a28-b36d-4b925e560486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420842185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2420842185
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3153148683
Short name T539
Test name
Test status
Simulation time 24212477 ps
CPU time 0.68 seconds
Started Aug 08 04:24:03 PM PDT 24
Finished Aug 08 04:24:04 PM PDT 24
Peak memory 195036 kb
Host smart-0e5684ec-cc33-4720-a728-b9f539d24340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153148683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3153148683
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3005991319
Short name T544
Test name
Test status
Simulation time 14152992 ps
CPU time 0.58 seconds
Started Aug 08 04:23:49 PM PDT 24
Finished Aug 08 04:23:49 PM PDT 24
Peak memory 194972 kb
Host smart-627c52a0-ffd0-420e-b79c-661ad0570b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005991319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3005991319
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1985428167
Short name T589
Test name
Test status
Simulation time 12924376 ps
CPU time 0.62 seconds
Started Aug 08 04:21:43 PM PDT 24
Finished Aug 08 04:21:43 PM PDT 24
Peak memory 195024 kb
Host smart-ceed6a55-c96e-4ff6-9961-af5817026530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985428167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1985428167
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1564183403
Short name T628
Test name
Test status
Simulation time 13243488 ps
CPU time 0.62 seconds
Started Aug 08 04:26:54 PM PDT 24
Finished Aug 08 04:26:55 PM PDT 24
Peak memory 193828 kb
Host smart-181dee0d-9957-4c87-83d6-5e0902aae5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564183403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1564183403
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2596980586
Short name T603
Test name
Test status
Simulation time 17994670 ps
CPU time 0.61 seconds
Started Aug 08 04:27:09 PM PDT 24
Finished Aug 08 04:27:09 PM PDT 24
Peak memory 194856 kb
Host smart-60fcd8f0-7c85-4744-9d8f-80060263c9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596980586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2596980586
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2055037879
Short name T545
Test name
Test status
Simulation time 15083331 ps
CPU time 0.57 seconds
Started Aug 08 04:26:45 PM PDT 24
Finished Aug 08 04:26:46 PM PDT 24
Peak memory 194776 kb
Host smart-b47c2a80-5c96-448c-b05a-5bcb8828ed07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055037879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2055037879
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3272276031
Short name T653
Test name
Test status
Simulation time 224242326 ps
CPU time 2.97 seconds
Started Aug 08 04:21:33 PM PDT 24
Finished Aug 08 04:21:36 PM PDT 24
Peak memory 199700 kb
Host smart-61486820-e92e-425f-9155-1e11ca0ad070
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272276031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3272276031
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.910969456
Short name T108
Test name
Test status
Simulation time 1610991109 ps
CPU time 16.67 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:47 PM PDT 24
Peak memory 196912 kb
Host smart-352fdac8-4650-4334-a78f-891b4dfdc8bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910969456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.910969456
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.49795125
Short name T109
Test name
Test status
Simulation time 91726245 ps
CPU time 0.91 seconds
Started Aug 08 04:22:37 PM PDT 24
Finished Aug 08 04:22:38 PM PDT 24
Peak memory 198672 kb
Host smart-e6147c2b-cba5-413e-ad02-83de63e998e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49795125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.49795125
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.681121608
Short name T583
Test name
Test status
Simulation time 219478344 ps
CPU time 1.8 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:28 PM PDT 24
Peak memory 198984 kb
Host smart-4b60b75c-8b18-4956-b49c-2da5c73998f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681121608 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.681121608
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1190397191
Short name T576
Test name
Test status
Simulation time 156086713 ps
CPU time 0.94 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:32 PM PDT 24
Peak memory 197612 kb
Host smart-f968184f-cd07-428e-933c-af790378b875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190397191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1190397191
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.669406052
Short name T630
Test name
Test status
Simulation time 16269251 ps
CPU time 0.62 seconds
Started Aug 08 04:21:33 PM PDT 24
Finished Aug 08 04:21:34 PM PDT 24
Peak memory 194724 kb
Host smart-6a905804-ad7c-4e5a-8348-feccfe9acca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669406052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.669406052
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.452771295
Short name T580
Test name
Test status
Simulation time 116507106 ps
CPU time 1.9 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:51 PM PDT 24
Peak memory 200048 kb
Host smart-3ca73a41-6321-45c2-952d-f8d9d18d206a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452771295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.452771295
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1509041662
Short name T538
Test name
Test status
Simulation time 214062772 ps
CPU time 1.61 seconds
Started Aug 08 04:22:33 PM PDT 24
Finished Aug 08 04:22:35 PM PDT 24
Peak memory 198372 kb
Host smart-50b714e6-df20-4849-9a44-ee80d717e3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509041662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1509041662
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1484523663
Short name T128
Test name
Test status
Simulation time 324713253 ps
CPU time 1.9 seconds
Started Aug 08 04:22:38 PM PDT 24
Finished Aug 08 04:22:40 PM PDT 24
Peak memory 199780 kb
Host smart-d9d50d9c-a39c-4868-b617-b4c7333b1150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484523663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1484523663
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.705382669
Short name T568
Test name
Test status
Simulation time 12917749 ps
CPU time 0.61 seconds
Started Aug 08 04:26:19 PM PDT 24
Finished Aug 08 04:26:20 PM PDT 24
Peak memory 194656 kb
Host smart-6c39b362-d8b2-4590-bc71-6926d68799a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705382669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.705382669
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1182709274
Short name T570
Test name
Test status
Simulation time 23894979 ps
CPU time 0.57 seconds
Started Aug 08 04:26:43 PM PDT 24
Finished Aug 08 04:26:44 PM PDT 24
Peak memory 194776 kb
Host smart-77dd15aa-62f1-4d7c-b8c9-f863e1710fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182709274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1182709274
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1816341939
Short name T586
Test name
Test status
Simulation time 45574295 ps
CPU time 0.65 seconds
Started Aug 08 04:23:58 PM PDT 24
Finished Aug 08 04:23:59 PM PDT 24
Peak memory 194928 kb
Host smart-715e2fe6-9c30-4c46-ae89-8dba790f23f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816341939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1816341939
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.233210644
Short name T598
Test name
Test status
Simulation time 39105876 ps
CPU time 0.61 seconds
Started Aug 08 04:25:11 PM PDT 24
Finished Aug 08 04:25:12 PM PDT 24
Peak memory 194932 kb
Host smart-5b081bc5-94a6-4579-94cd-5eb22043e6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233210644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.233210644
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2234841303
Short name T562
Test name
Test status
Simulation time 25272036 ps
CPU time 0.62 seconds
Started Aug 08 04:24:39 PM PDT 24
Finished Aug 08 04:24:40 PM PDT 24
Peak memory 194964 kb
Host smart-3dde370e-5794-44de-b4ec-5e75db01c634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234841303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2234841303
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3280809703
Short name T609
Test name
Test status
Simulation time 48286064 ps
CPU time 0.58 seconds
Started Aug 08 04:26:19 PM PDT 24
Finished Aug 08 04:26:19 PM PDT 24
Peak memory 194520 kb
Host smart-28001deb-2eff-4b15-b84e-e94247729bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280809703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3280809703
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.952473721
Short name T584
Test name
Test status
Simulation time 16941060 ps
CPU time 0.67 seconds
Started Aug 08 04:21:53 PM PDT 24
Finished Aug 08 04:21:53 PM PDT 24
Peak memory 194900 kb
Host smart-43a1a25a-6a38-45eb-81a5-0eec95b2aea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952473721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.952473721
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1029086068
Short name T572
Test name
Test status
Simulation time 30130943 ps
CPU time 0.61 seconds
Started Aug 08 04:21:44 PM PDT 24
Finished Aug 08 04:21:45 PM PDT 24
Peak memory 194860 kb
Host smart-5243cb96-0fb9-4bb5-be92-67731f597ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029086068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1029086068
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2734068950
Short name T554
Test name
Test status
Simulation time 31166886 ps
CPU time 0.64 seconds
Started Aug 08 04:24:05 PM PDT 24
Finished Aug 08 04:24:06 PM PDT 24
Peak memory 194960 kb
Host smart-55ced2f5-efa9-4976-b6c4-ab15af620c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734068950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2734068950
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1053024572
Short name T578
Test name
Test status
Simulation time 12717743 ps
CPU time 0.64 seconds
Started Aug 08 04:22:55 PM PDT 24
Finished Aug 08 04:22:55 PM PDT 24
Peak memory 194852 kb
Host smart-87cab180-d768-428f-ab53-e3e03378271c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053024572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1053024572
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4104661634
Short name T612
Test name
Test status
Simulation time 212210258 ps
CPU time 3.4 seconds
Started Aug 08 04:22:48 PM PDT 24
Finished Aug 08 04:22:51 PM PDT 24
Peak memory 199852 kb
Host smart-485e1340-2db0-475b-a660-d34947315e08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104661634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4104661634
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1720564678
Short name T100
Test name
Test status
Simulation time 1410550524 ps
CPU time 10.48 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:37 PM PDT 24
Peak memory 198156 kb
Host smart-d4d3cce3-f824-43dd-9fac-e8de372bd5bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720564678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1720564678
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2402089950
Short name T629
Test name
Test status
Simulation time 32671864 ps
CPU time 0.85 seconds
Started Aug 08 04:22:37 PM PDT 24
Finished Aug 08 04:22:38 PM PDT 24
Peak memory 199444 kb
Host smart-03a9bc32-f582-4d73-9a4c-c7c1fe0bdf14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402089950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2402089950
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2916625205
Short name T534
Test name
Test status
Simulation time 137952022 ps
CPU time 2.57 seconds
Started Aug 08 04:21:45 PM PDT 24
Finished Aug 08 04:21:48 PM PDT 24
Peak memory 200404 kb
Host smart-3c4d1529-4f78-48a8-8885-2ddb6daf9e9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916625205 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2916625205
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2475454951
Short name T547
Test name
Test status
Simulation time 44092098 ps
CPU time 0.64 seconds
Started Aug 08 04:22:32 PM PDT 24
Finished Aug 08 04:22:33 PM PDT 24
Peak memory 194192 kb
Host smart-d4c0cc4c-4746-4f7f-833b-f30fe9aafcd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475454951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2475454951
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1856367030
Short name T624
Test name
Test status
Simulation time 97577454 ps
CPU time 1.21 seconds
Started Aug 08 04:21:32 PM PDT 24
Finished Aug 08 04:21:33 PM PDT 24
Peak memory 198264 kb
Host smart-f1a3d5ae-8e84-4aa1-99ac-be81f52adc90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856367030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1856367030
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.101823373
Short name T566
Test name
Test status
Simulation time 33887460 ps
CPU time 1.62 seconds
Started Aug 08 04:22:36 PM PDT 24
Finished Aug 08 04:22:38 PM PDT 24
Peak memory 199392 kb
Host smart-3cdbd2cd-702c-42c3-831b-5bcb55f4d553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101823373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.101823373
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1670696490
Short name T642
Test name
Test status
Simulation time 909985167 ps
CPU time 4.48 seconds
Started Aug 08 04:21:23 PM PDT 24
Finished Aug 08 04:21:28 PM PDT 24
Peak memory 198092 kb
Host smart-1a69ca66-853a-4238-b11d-3129688f70da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670696490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1670696490
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.455791007
Short name T555
Test name
Test status
Simulation time 13129708 ps
CPU time 0.55 seconds
Started Aug 08 04:27:05 PM PDT 24
Finished Aug 08 04:27:06 PM PDT 24
Peak memory 194764 kb
Host smart-83d4b0db-91ce-4eae-9f74-1984d01204b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455791007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.455791007
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2323781573
Short name T528
Test name
Test status
Simulation time 90514242 ps
CPU time 0.63 seconds
Started Aug 08 04:27:04 PM PDT 24
Finished Aug 08 04:27:05 PM PDT 24
Peak memory 193944 kb
Host smart-4cf0f9d7-1587-4a28-88a5-151931814cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323781573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2323781573
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3842118074
Short name T614
Test name
Test status
Simulation time 27287551 ps
CPU time 0.61 seconds
Started Aug 08 04:23:22 PM PDT 24
Finished Aug 08 04:23:23 PM PDT 24
Peak memory 194952 kb
Host smart-ab2ff5eb-6ee8-4ae4-a6d1-c1134317111a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842118074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3842118074
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.577806187
Short name T620
Test name
Test status
Simulation time 17279695 ps
CPU time 0.65 seconds
Started Aug 08 04:22:18 PM PDT 24
Finished Aug 08 04:22:19 PM PDT 24
Peak memory 195008 kb
Host smart-bc571436-0eb3-4029-88f3-6954ce79e2dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577806187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.577806187
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2605517235
Short name T646
Test name
Test status
Simulation time 22880489 ps
CPU time 0.66 seconds
Started Aug 08 04:22:16 PM PDT 24
Finished Aug 08 04:22:17 PM PDT 24
Peak memory 194992 kb
Host smart-36826feb-7588-4535-84b8-35ed9feb9b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605517235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2605517235
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2003474724
Short name T559
Test name
Test status
Simulation time 13168444 ps
CPU time 0.55 seconds
Started Aug 08 04:27:20 PM PDT 24
Finished Aug 08 04:27:21 PM PDT 24
Peak memory 194548 kb
Host smart-10dc365f-f6f0-4ad0-b20f-f9f7b64ae48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003474724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2003474724
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.936238696
Short name T650
Test name
Test status
Simulation time 13564371 ps
CPU time 0.64 seconds
Started Aug 08 04:23:50 PM PDT 24
Finished Aug 08 04:23:50 PM PDT 24
Peak memory 194956 kb
Host smart-e0c9de80-b43e-4e00-b1c8-ffa2bfae7dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936238696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.936238696
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3477839475
Short name T588
Test name
Test status
Simulation time 32015781 ps
CPU time 0.58 seconds
Started Aug 08 04:21:44 PM PDT 24
Finished Aug 08 04:21:45 PM PDT 24
Peak memory 194880 kb
Host smart-1561a908-7cd6-4f5b-bda7-21a1c2f7ac61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477839475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3477839475
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2190539489
Short name T594
Test name
Test status
Simulation time 24355792 ps
CPU time 0.56 seconds
Started Aug 08 04:23:37 PM PDT 24
Finished Aug 08 04:23:38 PM PDT 24
Peak memory 194848 kb
Host smart-c96a1aa6-682c-4392-be35-ac20e1b2e9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190539489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2190539489
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1259164628
Short name T571
Test name
Test status
Simulation time 12746301 ps
CPU time 0.59 seconds
Started Aug 08 04:22:35 PM PDT 24
Finished Aug 08 04:22:36 PM PDT 24
Peak memory 194824 kb
Host smart-b2bd78e7-ce2d-473a-932b-7cc182bb9fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259164628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1259164628
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3697614294
Short name T608
Test name
Test status
Simulation time 160845849 ps
CPU time 2.52 seconds
Started Aug 08 04:22:33 PM PDT 24
Finished Aug 08 04:22:36 PM PDT 24
Peak memory 198408 kb
Host smart-9408d4ab-1b96-45e1-bfb6-f813a4549d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697614294 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3697614294
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.135618456
Short name T103
Test name
Test status
Simulation time 35628715 ps
CPU time 0.93 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:50 PM PDT 24
Peak memory 199444 kb
Host smart-1bfe01e0-e63d-4d38-8be5-7b4e0fce0536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135618456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.135618456
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1301521013
Short name T565
Test name
Test status
Simulation time 11666215 ps
CPU time 0.62 seconds
Started Aug 08 04:21:26 PM PDT 24
Finished Aug 08 04:21:27 PM PDT 24
Peak memory 193920 kb
Host smart-1eeb4176-758c-4b4d-bc98-c806ea390f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301521013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1301521013
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.115504161
Short name T657
Test name
Test status
Simulation time 32842535 ps
CPU time 1.56 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:51 PM PDT 24
Peak memory 199964 kb
Host smart-3eb1f36e-2188-489a-8ef3-3dbeac271c58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115504161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.115504161
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.429644352
Short name T574
Test name
Test status
Simulation time 299555298 ps
CPU time 3.25 seconds
Started Aug 08 04:22:38 PM PDT 24
Finished Aug 08 04:22:41 PM PDT 24
Peak memory 199832 kb
Host smart-5e9da2f8-6acf-4532-b191-024d52e47cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429644352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.429644352
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2584036184
Short name T125
Test name
Test status
Simulation time 200958768 ps
CPU time 1.87 seconds
Started Aug 08 04:22:49 PM PDT 24
Finished Aug 08 04:22:51 PM PDT 24
Peak memory 199940 kb
Host smart-36976cb8-4744-4ece-9edb-6ce7140b0c43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584036184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2584036184
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2906113677
Short name T569
Test name
Test status
Simulation time 92123616 ps
CPU time 1.34 seconds
Started Aug 08 04:21:37 PM PDT 24
Finished Aug 08 04:21:38 PM PDT 24
Peak memory 199832 kb
Host smart-7e015032-ce00-4012-b357-4af7c9fa0fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906113677 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2906113677
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.841991765
Short name T104
Test name
Test status
Simulation time 40315900 ps
CPU time 0.94 seconds
Started Aug 08 04:24:17 PM PDT 24
Finished Aug 08 04:24:18 PM PDT 24
Peak memory 199456 kb
Host smart-4ac6f476-b582-42c2-8f79-b33845d71278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841991765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.841991765
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2012590223
Short name T581
Test name
Test status
Simulation time 42142531 ps
CPU time 0.61 seconds
Started Aug 08 04:21:39 PM PDT 24
Finished Aug 08 04:21:40 PM PDT 24
Peak memory 195028 kb
Host smart-f28db2d2-09e6-4259-8d31-b371f58a620b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012590223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2012590223
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1892006978
Short name T114
Test name
Test status
Simulation time 477350681 ps
CPU time 1.78 seconds
Started Aug 08 04:21:38 PM PDT 24
Finished Aug 08 04:21:40 PM PDT 24
Peak memory 199972 kb
Host smart-2fb00b11-0041-4e96-ab83-c1c261b5a210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892006978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1892006978
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4282922828
Short name T556
Test name
Test status
Simulation time 134128497 ps
CPU time 2.04 seconds
Started Aug 08 04:21:22 PM PDT 24
Finished Aug 08 04:21:25 PM PDT 24
Peak memory 199184 kb
Host smart-60ac91c0-4ae8-45d1-9f6d-98c1182f29ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282922828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4282922828
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2813755392
Short name T129
Test name
Test status
Simulation time 203903376 ps
CPU time 3.24 seconds
Started Aug 08 04:21:31 PM PDT 24
Finished Aug 08 04:21:35 PM PDT 24
Peak memory 199612 kb
Host smart-135decef-359d-4f81-8d3a-acf9d1dae971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813755392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2813755392
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3743626054
Short name T637
Test name
Test status
Simulation time 343524861 ps
CPU time 2.34 seconds
Started Aug 08 04:22:42 PM PDT 24
Finished Aug 08 04:22:44 PM PDT 24
Peak memory 200032 kb
Host smart-e22f5122-0aa3-4a94-ab56-f784d01f0b15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743626054 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3743626054
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.554705272
Short name T595
Test name
Test status
Simulation time 17354299 ps
CPU time 0.92 seconds
Started Aug 08 04:22:12 PM PDT 24
Finished Aug 08 04:22:13 PM PDT 24
Peak memory 198736 kb
Host smart-9a850156-d30e-4dcc-a78d-64c063950c15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554705272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.554705272
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4184226982
Short name T621
Test name
Test status
Simulation time 17043863 ps
CPU time 0.62 seconds
Started Aug 08 04:22:18 PM PDT 24
Finished Aug 08 04:22:19 PM PDT 24
Peak memory 194904 kb
Host smart-5e8cf255-e152-4a29-931e-58f9e1c7ccda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184226982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4184226982
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2926647744
Short name T625
Test name
Test status
Simulation time 548736236 ps
CPU time 2.37 seconds
Started Aug 08 04:21:40 PM PDT 24
Finished Aug 08 04:21:42 PM PDT 24
Peak memory 199964 kb
Host smart-cdd81287-0d6d-46af-887b-ff46cc7ccdcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926647744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2926647744
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1569126180
Short name T533
Test name
Test status
Simulation time 1658744885 ps
CPU time 4.44 seconds
Started Aug 08 04:22:16 PM PDT 24
Finished Aug 08 04:22:21 PM PDT 24
Peak memory 200016 kb
Host smart-75e8d5f8-0483-422b-938d-7bef665c0030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569126180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1569126180
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3148252407
Short name T632
Test name
Test status
Simulation time 318520265 ps
CPU time 1.8 seconds
Started Aug 08 04:23:40 PM PDT 24
Finished Aug 08 04:23:42 PM PDT 24
Peak memory 199976 kb
Host smart-d91f0e34-af78-4a59-ac99-2a6c835cb6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148252407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3148252407
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4078454395
Short name T640
Test name
Test status
Simulation time 319930687 ps
CPU time 2.13 seconds
Started Aug 08 04:27:12 PM PDT 24
Finished Aug 08 04:27:14 PM PDT 24
Peak memory 199940 kb
Host smart-45b7586e-a66d-4828-8569-a2853884aa71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078454395 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4078454395
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2178967571
Short name T105
Test name
Test status
Simulation time 303368190 ps
CPU time 0.98 seconds
Started Aug 08 04:24:08 PM PDT 24
Finished Aug 08 04:24:09 PM PDT 24
Peak memory 198736 kb
Host smart-f9079f79-f683-42a4-baa0-ed9565b1a52a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178967571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2178967571
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3740890511
Short name T551
Test name
Test status
Simulation time 44847323 ps
CPU time 0.59 seconds
Started Aug 08 04:21:40 PM PDT 24
Finished Aug 08 04:21:41 PM PDT 24
Peak memory 194832 kb
Host smart-edaafdab-084e-432a-a16c-e6eb83445086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740890511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3740890511
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3338349389
Short name T115
Test name
Test status
Simulation time 356126765 ps
CPU time 1.71 seconds
Started Aug 08 04:26:08 PM PDT 24
Finished Aug 08 04:26:10 PM PDT 24
Peak memory 199976 kb
Host smart-3e424973-0ee0-43f4-a47d-b734eb8fee54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338349389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3338349389
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.401019194
Short name T530
Test name
Test status
Simulation time 1446625633 ps
CPU time 4.05 seconds
Started Aug 08 04:23:52 PM PDT 24
Finished Aug 08 04:23:56 PM PDT 24
Peak memory 199976 kb
Host smart-4bd86f45-4119-4017-bce0-399b2be744a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401019194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.401019194
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3485188076
Short name T550
Test name
Test status
Simulation time 188247420 ps
CPU time 2.56 seconds
Started Aug 08 04:21:37 PM PDT 24
Finished Aug 08 04:21:40 PM PDT 24
Peak memory 200124 kb
Host smart-4e2e8fb9-8f9a-4d93-8ab7-34c1afb60d6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485188076 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3485188076
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1778921205
Short name T107
Test name
Test status
Simulation time 30317529 ps
CPU time 0.81 seconds
Started Aug 08 04:26:09 PM PDT 24
Finished Aug 08 04:26:09 PM PDT 24
Peak memory 198996 kb
Host smart-dc4c9c21-904f-4f05-b59c-d137207f3e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778921205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1778921205
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1017166343
Short name T605
Test name
Test status
Simulation time 44970014 ps
CPU time 0.55 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:46 PM PDT 24
Peak memory 194760 kb
Host smart-5de5e234-1f12-4528-89d9-76b02dde27b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017166343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1017166343
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2157141544
Short name T626
Test name
Test status
Simulation time 91309187 ps
CPU time 1.8 seconds
Started Aug 08 04:21:42 PM PDT 24
Finished Aug 08 04:21:43 PM PDT 24
Peak memory 200072 kb
Host smart-d09b1858-f903-4e39-9ff8-33f91c967898
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157141544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2157141544
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3820437857
Short name T643
Test name
Test status
Simulation time 524654755 ps
CPU time 2.68 seconds
Started Aug 08 04:22:56 PM PDT 24
Finished Aug 08 04:22:58 PM PDT 24
Peak memory 200052 kb
Host smart-8721ddc4-d01f-4bf8-b334-49a0eb54b5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820437857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3820437857
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4261198251
Short name T385
Test name
Test status
Simulation time 26547351 ps
CPU time 0.62 seconds
Started Aug 08 04:27:04 PM PDT 24
Finished Aug 08 04:27:05 PM PDT 24
Peak memory 195508 kb
Host smart-5cda8a64-8926-4606-a510-1b086d908677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261198251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4261198251
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3573074014
Short name T504
Test name
Test status
Simulation time 9740470440 ps
CPU time 104.6 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:30:03 PM PDT 24
Peak memory 206080 kb
Host smart-9c8adc32-fe83-4884-a05c-23fb70704239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573074014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3573074014
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1129442341
Short name T92
Test name
Test status
Simulation time 1974798200 ps
CPU time 17.19 seconds
Started Aug 08 04:27:07 PM PDT 24
Finished Aug 08 04:27:24 PM PDT 24
Peak memory 200004 kb
Host smart-c4a4f4d7-18fd-4b4f-8a82-9b415e357684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129442341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1129442341
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1715024997
Short name T367
Test name
Test status
Simulation time 1906677166 ps
CPU time 128.32 seconds
Started Aug 08 04:27:02 PM PDT 24
Finished Aug 08 04:29:11 PM PDT 24
Peak memory 362200 kb
Host smart-92642ea0-df93-4d19-9e33-307a44c57476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715024997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1715024997
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.119466434
Short name T337
Test name
Test status
Simulation time 6107364865 ps
CPU time 72.65 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:29:40 PM PDT 24
Peak memory 199456 kb
Host smart-940822a1-83de-410c-8b99-a2a9ac3817fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119466434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.119466434
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3856538214
Short name T519
Test name
Test status
Simulation time 332898556 ps
CPU time 2.79 seconds
Started Aug 08 04:27:00 PM PDT 24
Finished Aug 08 04:27:03 PM PDT 24
Peak memory 199548 kb
Host smart-7e00566e-41d0-4619-a9a6-0f03832bdb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856538214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3856538214
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1930266075
Short name T51
Test name
Test status
Simulation time 73229168 ps
CPU time 0.83 seconds
Started Aug 08 04:27:02 PM PDT 24
Finished Aug 08 04:27:03 PM PDT 24
Peak memory 218048 kb
Host smart-808a4892-b020-4da4-8f13-42d85e9b2ac2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930266075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1930266075
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.4037887044
Short name T355
Test name
Test status
Simulation time 72962249 ps
CPU time 3.35 seconds
Started Aug 08 04:27:03 PM PDT 24
Finished Aug 08 04:27:06 PM PDT 24
Peak memory 199688 kb
Host smart-d79aae81-862f-42ef-be0c-d86aed5f33f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037887044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4037887044
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4055956633
Short name T20
Test name
Test status
Simulation time 32625827305 ps
CPU time 477.92 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:36:16 PM PDT 24
Peak memory 197852 kb
Host smart-5b1eec46-9076-46e5-844e-e46366eb36c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055956633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4055956633
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3496375186
Short name T177
Test name
Test status
Simulation time 2393171643 ps
CPU time 43.95 seconds
Started Aug 08 04:27:03 PM PDT 24
Finished Aug 08 04:27:47 PM PDT 24
Peak memory 199700 kb
Host smart-39be19b7-4b7b-4cc5-bae6-4be76ecdb80c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3496375186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3496375186
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2918607492
Short name T516
Test name
Test status
Simulation time 13862754999 ps
CPU time 56.83 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:29:15 PM PDT 24
Peak memory 199344 kb
Host smart-b430993b-77bb-49d7-a2b4-d9fb3fc9aba5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2918607492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2918607492
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1456286981
Short name T209
Test name
Test status
Simulation time 22074567007 ps
CPU time 128.93 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:30:36 PM PDT 24
Peak memory 199408 kb
Host smart-e2d4fb22-16bd-483e-8d17-c0d0fa3d1793
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1456286981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1456286981
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2395920831
Short name T430
Test name
Test status
Simulation time 196925382325 ps
CPU time 595.29 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:38:13 PM PDT 24
Peak memory 197788 kb
Host smart-8f3e7f3c-ca5f-4892-974f-bc98015491e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2395920831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2395920831
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.650113789
Short name T93
Test name
Test status
Simulation time 226414408869 ps
CPU time 2407.06 seconds
Started Aug 08 04:27:03 PM PDT 24
Finished Aug 08 05:07:10 PM PDT 24
Peak memory 214996 kb
Host smart-2a7121f0-5a13-4b81-a3e7-ef39be589c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=650113789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.650113789
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.4082267779
Short name T235
Test name
Test status
Simulation time 76291095671 ps
CPU time 2166.77 seconds
Started Aug 08 04:27:02 PM PDT 24
Finished Aug 08 05:03:09 PM PDT 24
Peak memory 215720 kb
Host smart-db5149a5-f7f4-4482-b64a-98e5d92bc9fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4082267779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.4082267779
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3349063529
Short name T515
Test name
Test status
Simulation time 9641991349 ps
CPU time 44.74 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 199308 kb
Host smart-f823736b-ebbb-4f91-8dee-ce73d65b5027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349063529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3349063529
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4037032723
Short name T253
Test name
Test status
Simulation time 1464061378 ps
CPU time 79.23 seconds
Started Aug 08 04:27:04 PM PDT 24
Finished Aug 08 04:28:24 PM PDT 24
Peak memory 199220 kb
Host smart-e7986372-56ea-458f-9e46-8d4743861ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037032723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4037032723
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3111447710
Short name T409
Test name
Test status
Simulation time 70676179257 ps
CPU time 60.36 seconds
Started Aug 08 04:27:04 PM PDT 24
Finished Aug 08 04:28:05 PM PDT 24
Peak memory 199620 kb
Host smart-428dfb98-0006-4e37-912e-d40e418c609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111447710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3111447710
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4222301716
Short name T53
Test name
Test status
Simulation time 2889873548 ps
CPU time 198.24 seconds
Started Aug 08 04:27:04 PM PDT 24
Finished Aug 08 04:30:23 PM PDT 24
Peak memory 457148 kb
Host smart-75ce50bd-dc23-48ed-8b4b-ea0c258dbd69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222301716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4222301716
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2877979452
Short name T41
Test name
Test status
Simulation time 5682208824 ps
CPU time 64.15 seconds
Started Aug 08 04:27:02 PM PDT 24
Finished Aug 08 04:28:07 PM PDT 24
Peak memory 199524 kb
Host smart-a695e059-6652-417c-8d68-b2469b9fbbd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877979452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2877979452
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2868371075
Short name T226
Test name
Test status
Simulation time 43722773696 ps
CPU time 187.75 seconds
Started Aug 08 04:27:06 PM PDT 24
Finished Aug 08 04:30:14 PM PDT 24
Peak memory 199792 kb
Host smart-8f94d349-aea7-4f69-98a1-b74e1ca2eb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868371075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2868371075
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1872992204
Short name T50
Test name
Test status
Simulation time 62109606 ps
CPU time 0.97 seconds
Started Aug 08 04:27:18 PM PDT 24
Finished Aug 08 04:27:19 PM PDT 24
Peak memory 218716 kb
Host smart-cd7c1062-2dd2-4771-a4e1-7f98098fff70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872992204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1872992204
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.446578311
Short name T248
Test name
Test status
Simulation time 1301177218 ps
CPU time 7.53 seconds
Started Aug 08 04:27:05 PM PDT 24
Finished Aug 08 04:27:13 PM PDT 24
Peak memory 199512 kb
Host smart-7885d3fb-afaf-4e8f-9329-80988339d230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446578311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.446578311
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1392115347
Short name T371
Test name
Test status
Simulation time 312524090171 ps
CPU time 1962.22 seconds
Started Aug 08 04:27:15 PM PDT 24
Finished Aug 08 04:59:57 PM PDT 24
Peak memory 759620 kb
Host smart-6c7a25d3-9a6c-4b36-8656-f13a8e2b5ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392115347 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1392115347
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.475064834
Short name T457
Test name
Test status
Simulation time 5160767986 ps
CPU time 41.62 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 199408 kb
Host smart-4874b913-f785-4f12-9808-ab4398c0d7a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=475064834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.475064834
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1554119999
Short name T239
Test name
Test status
Simulation time 2434923257 ps
CPU time 88.72 seconds
Started Aug 08 04:27:05 PM PDT 24
Finished Aug 08 04:28:34 PM PDT 24
Peak memory 199588 kb
Host smart-bd3c9bca-1f9e-4021-a497-41353e6a41ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1554119999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1554119999
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1471737248
Short name T346
Test name
Test status
Simulation time 10510376455 ps
CPU time 576.35 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:37:54 PM PDT 24
Peak memory 198488 kb
Host smart-0687a876-65f7-4f19-a21a-7cd12fadadc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1471737248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1471737248
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.989741430
Short name T252
Test name
Test status
Simulation time 39772307001 ps
CPU time 2195.96 seconds
Started Aug 08 04:27:06 PM PDT 24
Finished Aug 08 05:03:43 PM PDT 24
Peak memory 216028 kb
Host smart-510f2468-5119-4331-9005-8e6bd2b550f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=989741430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.989741430
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2743136609
Short name T449
Test name
Test status
Simulation time 218520449429 ps
CPU time 2355.75 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 05:07:34 PM PDT 24
Peak memory 214744 kb
Host smart-098c48bc-6c7f-4026-b8a8-3ceb68b10e95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2743136609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2743136609
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1417916241
Short name T444
Test name
Test status
Simulation time 7332628257 ps
CPU time 128.56 seconds
Started Aug 08 04:27:05 PM PDT 24
Finished Aug 08 04:29:14 PM PDT 24
Peak memory 199564 kb
Host smart-38f36790-2957-41b9-a866-29ed1fec801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417916241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1417916241
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2956743300
Short name T374
Test name
Test status
Simulation time 11663393 ps
CPU time 0.58 seconds
Started Aug 08 04:27:42 PM PDT 24
Finished Aug 08 04:27:43 PM PDT 24
Peak memory 195640 kb
Host smart-26664405-1818-48ad-a4bc-ab9fd2b14395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956743300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2956743300
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1179375356
Short name T298
Test name
Test status
Simulation time 5031423218 ps
CPU time 47.03 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:28:31 PM PDT 24
Peak memory 215892 kb
Host smart-2b9a875f-f7a9-444b-bb9c-ce31e8f45398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179375356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1179375356
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2647899468
Short name T134
Test name
Test status
Simulation time 2622299031 ps
CPU time 42.96 seconds
Started Aug 08 04:27:41 PM PDT 24
Finished Aug 08 04:28:24 PM PDT 24
Peak memory 199700 kb
Host smart-3a8d1976-7e4b-4a1b-950e-d271096b75c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647899468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2647899468
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3810267520
Short name T39
Test name
Test status
Simulation time 7607597474 ps
CPU time 1782.8 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:57:26 PM PDT 24
Peak memory 777124 kb
Host smart-5b6c331f-a5a1-4645-856b-73daff12dce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3810267520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3810267520
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1656283952
Short name T498
Test name
Test status
Simulation time 9284326045 ps
CPU time 161.31 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:31:39 PM PDT 24
Peak memory 199496 kb
Host smart-4f2c5d78-5584-4ecd-aead-6a03e4bc4069
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656283952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1656283952
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4165018294
Short name T160
Test name
Test status
Simulation time 6078009068 ps
CPU time 115.03 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:29:40 PM PDT 24
Peak memory 216512 kb
Host smart-64e44adb-4917-40bf-85af-48e80d062135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165018294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4165018294
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.717987721
Short name T460
Test name
Test status
Simulation time 1927877781 ps
CPU time 7.62 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:27:53 PM PDT 24
Peak memory 199576 kb
Host smart-63222306-1090-4308-9264-8db43ab42fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717987721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.717987721
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1920443136
Short name T446
Test name
Test status
Simulation time 17323359614 ps
CPU time 1299.29 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:49:23 PM PDT 24
Peak memory 522676 kb
Host smart-d33244ee-d14d-4054-a137-da1a4b1c008a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920443136 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1920443136
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2105455959
Short name T418
Test name
Test status
Simulation time 22610320700 ps
CPU time 74.45 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 199544 kb
Host smart-fb1c2e1e-0e48-47c0-b9bf-8b81ce1ddc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105455959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2105455959
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4105168544
Short name T475
Test name
Test status
Simulation time 46611729 ps
CPU time 0.59 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:27:48 PM PDT 24
Peak memory 196444 kb
Host smart-c1581ee4-5907-4c65-a954-2597a773ddf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105168544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4105168544
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.118755214
Short name T197
Test name
Test status
Simulation time 1398833320 ps
CPU time 20.5 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:28:07 PM PDT 24
Peak memory 199652 kb
Host smart-8dcb82fc-afbe-4ef9-b8f1-f4392f9f5966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118755214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.118755214
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3870169868
Short name T415
Test name
Test status
Simulation time 890345488 ps
CPU time 4.14 seconds
Started Aug 08 04:27:50 PM PDT 24
Finished Aug 08 04:27:54 PM PDT 24
Peak memory 199504 kb
Host smart-5653ef7f-4da7-459d-a2bc-54db3d6c1f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870169868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3870169868
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2625368384
Short name T411
Test name
Test status
Simulation time 2803629355 ps
CPU time 517.7 seconds
Started Aug 08 04:27:49 PM PDT 24
Finished Aug 08 04:36:27 PM PDT 24
Peak memory 667816 kb
Host smart-bd1bf3a1-711f-464f-9c41-85f678a99664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625368384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2625368384
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3766202556
Short name T90
Test name
Test status
Simulation time 36688483901 ps
CPU time 113.92 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:30:53 PM PDT 24
Peak memory 199384 kb
Host smart-633f97a0-d7cf-4cb2-8778-1381a469b248
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766202556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3766202556
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1493096049
Short name T478
Test name
Test status
Simulation time 20854343490 ps
CPU time 54.48 seconds
Started Aug 08 04:27:48 PM PDT 24
Finished Aug 08 04:28:43 PM PDT 24
Peak memory 199740 kb
Host smart-0a6f1f49-bdd2-462e-87be-7e25042e1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493096049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1493096049
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.704344554
Short name T45
Test name
Test status
Simulation time 814135902 ps
CPU time 6.82 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:27:50 PM PDT 24
Peak memory 199624 kb
Host smart-bff83196-0909-47ed-9da6-b70b4ebc4f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704344554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.704344554
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4106529905
Short name T203
Test name
Test status
Simulation time 9586169251 ps
CPU time 83.74 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 199648 kb
Host smart-f3641774-ba45-4522-be43-e780e14771d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106529905 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4106529905
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2971741848
Short name T348
Test name
Test status
Simulation time 1019960884 ps
CPU time 44.01 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:28:29 PM PDT 24
Peak memory 199376 kb
Host smart-0405fb95-dfef-46b3-a00a-1f931b2c8ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971741848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2971741848
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4225054025
Short name T497
Test name
Test status
Simulation time 12699265 ps
CPU time 0.59 seconds
Started Aug 08 04:27:42 PM PDT 24
Finished Aug 08 04:27:43 PM PDT 24
Peak memory 195268 kb
Host smart-f033afcd-c13b-4a80-bbbd-167cfd7608eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225054025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4225054025
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3965031136
Short name T24
Test name
Test status
Simulation time 614544255 ps
CPU time 33.18 seconds
Started Aug 08 04:27:48 PM PDT 24
Finished Aug 08 04:28:21 PM PDT 24
Peak memory 199640 kb
Host smart-b03c4f29-3822-4e8f-b35e-49ca3e6a1cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965031136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3965031136
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2940595116
Short name T417
Test name
Test status
Simulation time 2568234746 ps
CPU time 14.87 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:27:59 PM PDT 24
Peak memory 199548 kb
Host smart-9ee22e3f-ad22-42b1-838b-f121f548ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940595116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2940595116
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2046023449
Short name T233
Test name
Test status
Simulation time 26420312892 ps
CPU time 1328.43 seconds
Started Aug 08 04:27:50 PM PDT 24
Finished Aug 08 04:49:58 PM PDT 24
Peak memory 748692 kb
Host smart-4d646811-b312-4547-b1b6-1ce6e8ba65c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046023449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2046023449
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.529236374
Short name T459
Test name
Test status
Simulation time 16756003707 ps
CPU time 56.07 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:28:39 PM PDT 24
Peak memory 199540 kb
Host smart-96998f9e-d6de-48c6-a647-dca3ce682166
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529236374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.529236374
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2159911018
Short name T377
Test name
Test status
Simulation time 14778439363 ps
CPU time 48.55 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:28:35 PM PDT 24
Peak memory 215772 kb
Host smart-e1b2d871-eda5-454c-9528-e847fb690ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159911018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2159911018
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.4152921299
Short name T40
Test name
Test status
Simulation time 172002022 ps
CPU time 4.41 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:27:51 PM PDT 24
Peak memory 199704 kb
Host smart-6de9c371-2930-4813-b4ff-b65288c9b3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152921299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4152921299
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1705148921
Short name T173
Test name
Test status
Simulation time 52073895010 ps
CPU time 1695.15 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:56:02 PM PDT 24
Peak memory 688852 kb
Host smart-75c9e447-2416-4084-b3c0-1fbe87acbb94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705148921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1705148921
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.773000865
Short name T492
Test name
Test status
Simulation time 39172593827 ps
CPU time 110.93 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:29:34 PM PDT 24
Peak memory 199736 kb
Host smart-8afb69c0-ab02-4d4e-a136-4086e0abcb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773000865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.773000865
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2196112912
Short name T231
Test name
Test status
Simulation time 21973839 ps
CPU time 0.59 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:27:44 PM PDT 24
Peak memory 195692 kb
Host smart-8a20779c-9a7e-4314-8c45-2309bd26fb86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196112912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2196112912
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1471569237
Short name T323
Test name
Test status
Simulation time 1634240693 ps
CPU time 23.63 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:28:11 PM PDT 24
Peak memory 199668 kb
Host smart-f414f704-34e1-457e-821b-d35324736edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471569237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1471569237
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1104988229
Short name T135
Test name
Test status
Simulation time 1295108841 ps
CPU time 17.26 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:28:03 PM PDT 24
Peak memory 198760 kb
Host smart-797a2792-b93e-4221-b408-ddbea76b657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104988229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1104988229
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.461050940
Short name T426
Test name
Test status
Simulation time 25606903 ps
CPU time 0.86 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:27:45 PM PDT 24
Peak memory 207612 kb
Host smart-1aaef468-e239-4c2f-bb2b-afaa2963973d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461050940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.461050940
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.389770588
Short name T388
Test name
Test status
Simulation time 2198524273 ps
CPU time 19.17 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:28:06 PM PDT 24
Peak memory 199440 kb
Host smart-011e99b1-61d1-496a-bd5a-d1d87b946878
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389770588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.389770588
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.582590559
Short name T95
Test name
Test status
Simulation time 7111146717 ps
CPU time 90.64 seconds
Started Aug 08 04:27:49 PM PDT 24
Finished Aug 08 04:29:20 PM PDT 24
Peak memory 199744 kb
Host smart-fbdafe48-cf05-4fba-ab07-7b9bb5ca2f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582590559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.582590559
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2926937973
Short name T319
Test name
Test status
Simulation time 501408662 ps
CPU time 3.11 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:27:47 PM PDT 24
Peak memory 199544 kb
Host smart-ca730a2f-6c3f-4ac9-8a02-b0f0c93b92fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926937973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2926937973
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3964041594
Short name T389
Test name
Test status
Simulation time 5138782500 ps
CPU time 126.96 seconds
Started Aug 08 04:28:48 PM PDT 24
Finished Aug 08 04:30:55 PM PDT 24
Peak memory 198928 kb
Host smart-7df2a653-4b59-4e06-9de4-a41fa521ee02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964041594 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3964041594
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3550884121
Short name T468
Test name
Test status
Simulation time 1295489642 ps
CPU time 11.98 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:27:58 PM PDT 24
Peak memory 199708 kb
Host smart-cbec2b81-aed1-43c1-953e-94354f2c7017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550884121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3550884121
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2590110575
Short name T331
Test name
Test status
Simulation time 11908271 ps
CPU time 0.58 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 196160 kb
Host smart-209980ce-90eb-44b1-b64f-973aa6ee19e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590110575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2590110575
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.789361217
Short name T217
Test name
Test status
Simulation time 1143381118 ps
CPU time 59.39 seconds
Started Aug 08 04:27:50 PM PDT 24
Finished Aug 08 04:28:50 PM PDT 24
Peak memory 199604 kb
Host smart-03f60001-a978-4310-a9c6-3ea48f99bb45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789361217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.789361217
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2386472292
Short name T269
Test name
Test status
Simulation time 1411250150 ps
CPU time 17.32 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:28:03 PM PDT 24
Peak memory 199564 kb
Host smart-3df5d730-a0d5-4dd8-982b-ede67d69c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386472292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2386472292
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.931090155
Short name T228
Test name
Test status
Simulation time 25886792132 ps
CPU time 1488.3 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:52:34 PM PDT 24
Peak memory 762404 kb
Host smart-d7630f0e-a9a6-4ee5-a6a0-d5fd0f867420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931090155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.931090155
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3966624516
Short name T170
Test name
Test status
Simulation time 126140676148 ps
CPU time 213.26 seconds
Started Aug 08 04:27:48 PM PDT 24
Finished Aug 08 04:31:22 PM PDT 24
Peak memory 199604 kb
Host smart-e1e44987-30a2-4e7a-9208-be456f1303ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966624516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3966624516
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2472731972
Short name T193
Test name
Test status
Simulation time 968337728 ps
CPU time 3.58 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:27:48 PM PDT 24
Peak memory 198840 kb
Host smart-58291312-dcf3-49d5-92f5-6dde595407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472731972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2472731972
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.152763348
Short name T208
Test name
Test status
Simulation time 900535650 ps
CPU time 10.85 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:56 PM PDT 24
Peak memory 200024 kb
Host smart-e97210ab-c269-4c09-b2ab-6155d58b47b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152763348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.152763348
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2055479704
Short name T520
Test name
Test status
Simulation time 12298541155 ps
CPU time 127.94 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:29:54 PM PDT 24
Peak memory 620492 kb
Host smart-fb24314b-9630-4709-9274-a76b71b5aca8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055479704 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2055479704
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1960022376
Short name T390
Test name
Test status
Simulation time 3479284779 ps
CPU time 62.69 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:28:46 PM PDT 24
Peak memory 199688 kb
Host smart-7aee4e17-7d0c-4de0-be4f-b5083f64be8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960022376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1960022376
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1270807164
Short name T507
Test name
Test status
Simulation time 12224975 ps
CPU time 0.58 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:27:55 PM PDT 24
Peak memory 195256 kb
Host smart-32c80b0d-15e9-46b6-82d6-b1f487c70124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270807164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1270807164
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1742021392
Short name T250
Test name
Test status
Simulation time 392339674 ps
CPU time 22.72 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:28:06 PM PDT 24
Peak memory 199676 kb
Host smart-ba02a149-9e9d-4da8-9589-db28d4df63dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742021392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1742021392
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3016507549
Short name T328
Test name
Test status
Simulation time 12031888463 ps
CPU time 18.72 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:28:25 PM PDT 24
Peak memory 199684 kb
Host smart-3e3ad48e-f05e-46ad-b325-60d5fac4cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016507549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3016507549
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2082106994
Short name T474
Test name
Test status
Simulation time 3656875182 ps
CPU time 497.9 seconds
Started Aug 08 04:28:01 PM PDT 24
Finished Aug 08 04:36:19 PM PDT 24
Peak memory 622404 kb
Host smart-b56b5a06-5114-4b75-b7d2-7b83097c4363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082106994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2082106994
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3002986109
Short name T190
Test name
Test status
Simulation time 2100170705 ps
CPU time 44.66 seconds
Started Aug 08 04:27:57 PM PDT 24
Finished Aug 08 04:28:42 PM PDT 24
Peak memory 199612 kb
Host smart-7f29bfe0-3057-493b-b3e0-3a404718eb9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002986109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3002986109
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2059400983
Short name T372
Test name
Test status
Simulation time 5934655102 ps
CPU time 9.64 seconds
Started Aug 08 04:27:48 PM PDT 24
Finished Aug 08 04:27:58 PM PDT 24
Peak memory 199636 kb
Host smart-0da1143b-ee98-4143-bd62-1082e4e7321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059400983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2059400983
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.462572543
Short name T276
Test name
Test status
Simulation time 2778353869 ps
CPU time 7.15 seconds
Started Aug 08 04:27:49 PM PDT 24
Finished Aug 08 04:27:56 PM PDT 24
Peak memory 199700 kb
Host smart-a87cfa5f-0221-492e-9dea-68f15a238114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462572543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.462572543
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3522172982
Short name T43
Test name
Test status
Simulation time 32154536931 ps
CPU time 341.86 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:33:46 PM PDT 24
Peak memory 641696 kb
Host smart-e15b48c8-2dea-4cd4-a171-34d93f2b1171
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522172982 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3522172982
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3967807187
Short name T117
Test name
Test status
Simulation time 1782316943 ps
CPU time 83.65 seconds
Started Aug 08 04:28:00 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 199500 kb
Host smart-16eccce1-0bfb-4794-a725-1ea7a179a748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967807187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3967807187
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1549496857
Short name T202
Test name
Test status
Simulation time 17925930 ps
CPU time 0.6 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:27:54 PM PDT 24
Peak memory 194736 kb
Host smart-e228dfd6-8d51-4bde-8443-4d2999c7211a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549496857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1549496857
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.374951467
Short name T395
Test name
Test status
Simulation time 2343965144 ps
CPU time 32.31 seconds
Started Aug 08 04:27:53 PM PDT 24
Finished Aug 08 04:28:25 PM PDT 24
Peak memory 199628 kb
Host smart-d7e02519-f187-4468-bd6c-305c1e11f430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374951467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.374951467
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3867439712
Short name T142
Test name
Test status
Simulation time 3796293316 ps
CPU time 44.9 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:28:39 PM PDT 24
Peak memory 199580 kb
Host smart-2cd50775-6499-4c71-9b83-a163871e6ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867439712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3867439712
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3563197939
Short name T244
Test name
Test status
Simulation time 7995730483 ps
CPU time 662.71 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:39:06 PM PDT 24
Peak memory 634240 kb
Host smart-00a01e1f-9e23-4968-8ea8-bf3963d4e795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563197939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3563197939
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.920775239
Short name T429
Test name
Test status
Simulation time 1251330552 ps
CPU time 22.24 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:27 PM PDT 24
Peak memory 199468 kb
Host smart-5ebfc35b-1b8f-4844-bd1c-dd2f0f9c282c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920775239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.920775239
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3369548965
Short name T176
Test name
Test status
Simulation time 5206309390 ps
CPU time 29.02 seconds
Started Aug 08 04:27:53 PM PDT 24
Finished Aug 08 04:28:22 PM PDT 24
Peak memory 199664 kb
Host smart-4a9ebdbd-2b2e-46f8-bb13-46b0727dab02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369548965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3369548965
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.308627466
Short name T132
Test name
Test status
Simulation time 255491927 ps
CPU time 6.54 seconds
Started Aug 08 04:28:13 PM PDT 24
Finished Aug 08 04:28:19 PM PDT 24
Peak memory 199608 kb
Host smart-73c797e8-1072-400f-93fc-cd468bbdd338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308627466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.308627466
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.158712498
Short name T299
Test name
Test status
Simulation time 754954518703 ps
CPU time 1804.84 seconds
Started Aug 08 04:28:00 PM PDT 24
Finished Aug 08 04:58:05 PM PDT 24
Peak memory 721452 kb
Host smart-06e8c533-250b-4c3c-b36a-4d333d9399ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158712498 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.158712498
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.415298344
Short name T229
Test name
Test status
Simulation time 4537165394 ps
CPU time 82.11 seconds
Started Aug 08 04:28:01 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 199696 kb
Host smart-ba0c01ae-cd42-44f1-8f15-66b43f681505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415298344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.415298344
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2330005216
Short name T210
Test name
Test status
Simulation time 45110868 ps
CPU time 0.64 seconds
Started Aug 08 04:27:52 PM PDT 24
Finished Aug 08 04:27:53 PM PDT 24
Peak memory 195668 kb
Host smart-7f88da10-2a21-4a80-be54-37250fd41d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330005216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2330005216
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2486066551
Short name T12
Test name
Test status
Simulation time 199525969 ps
CPU time 2.83 seconds
Started Aug 08 04:27:53 PM PDT 24
Finished Aug 08 04:27:55 PM PDT 24
Peak memory 199392 kb
Host smart-f6953571-8b3f-4b7a-b963-5be6e364804a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486066551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2486066551
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3937027251
Short name T490
Test name
Test status
Simulation time 1504109200 ps
CPU time 36.6 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:28:43 PM PDT 24
Peak memory 199560 kb
Host smart-9d562b83-8f2f-4f0c-88f4-3fbea807b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937027251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3937027251
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1533387943
Short name T178
Test name
Test status
Simulation time 3487816532 ps
CPU time 590.8 seconds
Started Aug 08 04:28:10 PM PDT 24
Finished Aug 08 04:38:01 PM PDT 24
Peak memory 682812 kb
Host smart-698c81d6-113e-4c38-b43d-f47a3a08485d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1533387943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1533387943
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1928142340
Short name T238
Test name
Test status
Simulation time 8207964322 ps
CPU time 50.95 seconds
Started Aug 08 04:27:55 PM PDT 24
Finished Aug 08 04:28:46 PM PDT 24
Peak memory 199608 kb
Host smart-f723b164-d95c-42cf-92b4-063c82d06c9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928142340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1928142340
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1496846291
Short name T150
Test name
Test status
Simulation time 964642376 ps
CPU time 50.88 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 199632 kb
Host smart-eca9dbac-427f-4c0d-9eec-375b203638ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496846291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1496846291
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2928332979
Short name T402
Test name
Test status
Simulation time 4899893061 ps
CPU time 14.17 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:13 PM PDT 24
Peak memory 199424 kb
Host smart-22c5530c-cb72-4072-a634-ac26673736b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928332979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2928332979
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.449005
Short name T404
Test name
Test status
Simulation time 1427437887 ps
CPU time 75.19 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:29:19 PM PDT 24
Peak memory 197256 kb
Host smart-0f96b1f3-ec36-4425-bcf7-2d48e35b7f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.449005
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.648712359
Short name T215
Test name
Test status
Simulation time 18216757 ps
CPU time 0.62 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:28:04 PM PDT 24
Peak memory 194508 kb
Host smart-b66da758-0935-4360-bcc0-6d89911449ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648712359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.648712359
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1278294534
Short name T207
Test name
Test status
Simulation time 1342006057 ps
CPU time 19.47 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:23 PM PDT 24
Peak memory 199588 kb
Host smart-f508bea7-450e-4e6b-9394-b47687e5009c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1278294534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1278294534
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.916306082
Short name T330
Test name
Test status
Simulation time 13410199226 ps
CPU time 46.62 seconds
Started Aug 08 04:27:52 PM PDT 24
Finished Aug 08 04:28:38 PM PDT 24
Peak memory 207928 kb
Host smart-960b0688-8f37-4a91-b2b5-85d6bbe61a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916306082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.916306082
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3447934199
Short name T172
Test name
Test status
Simulation time 6601385564 ps
CPU time 1213.07 seconds
Started Aug 08 04:28:02 PM PDT 24
Finished Aug 08 04:48:16 PM PDT 24
Peak memory 748940 kb
Host smart-9dde93f6-2495-49c5-804f-9f6ea16efb6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447934199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3447934199
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2295225458
Short name T452
Test name
Test status
Simulation time 3620645894 ps
CPU time 48.72 seconds
Started Aug 08 04:28:02 PM PDT 24
Finished Aug 08 04:28:50 PM PDT 24
Peak memory 199560 kb
Host smart-452a1bf8-2e27-4149-8ed6-5fe32f1dab5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295225458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2295225458
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1068471415
Short name T506
Test name
Test status
Simulation time 5510462898 ps
CPU time 150.75 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:30:35 PM PDT 24
Peak memory 214044 kb
Host smart-3acffb60-d4c1-4103-aa74-04c7d86f5366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068471415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1068471415
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1912871982
Short name T161
Test name
Test status
Simulation time 2454754283 ps
CPU time 15.9 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:20 PM PDT 24
Peak memory 199664 kb
Host smart-3750d351-e7d0-4ccd-88c1-dbee47504cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912871982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1912871982
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3296589249
Short name T69
Test name
Test status
Simulation time 40474207504 ps
CPU time 574.3 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:37:41 PM PDT 24
Peak memory 199740 kb
Host smart-1523e3cd-e1e7-4c39-b048-4ab05a08e4f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296589249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3296589249
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1127189493
Short name T81
Test name
Test status
Simulation time 24627628372 ps
CPU time 90.53 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:29:25 PM PDT 24
Peak memory 199568 kb
Host smart-94a5d989-070b-4306-bfb5-250c24e0ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127189493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1127189493
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1692406949
Short name T360
Test name
Test status
Simulation time 14175011 ps
CPU time 0.57 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:27:54 PM PDT 24
Peak memory 195324 kb
Host smart-8b560509-1d92-4236-acf3-0dbab194fadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692406949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1692406949
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2776558252
Short name T453
Test name
Test status
Simulation time 3239840802 ps
CPU time 32.45 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:38 PM PDT 24
Peak memory 199564 kb
Host smart-a64c798d-44e3-40d5-94f1-424d16fc0897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776558252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2776558252
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2791855192
Short name T313
Test name
Test status
Simulation time 5732832756 ps
CPU time 21.6 seconds
Started Aug 08 04:27:53 PM PDT 24
Finished Aug 08 04:28:15 PM PDT 24
Peak memory 199640 kb
Host smart-5ca36309-1fa2-4607-88fd-299e1fcf64d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791855192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2791855192
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2089237929
Short name T425
Test name
Test status
Simulation time 54081020808 ps
CPU time 1283.98 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:49:30 PM PDT 24
Peak memory 740648 kb
Host smart-a838bcb2-91a1-4fb9-a71d-2c2993fe976b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089237929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2089237929
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4234597331
Short name T191
Test name
Test status
Simulation time 37671073462 ps
CPU time 124.42 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:30:09 PM PDT 24
Peak memory 197484 kb
Host smart-49274516-720a-4632-92ff-df6ee56558eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234597331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4234597331
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2215163361
Short name T314
Test name
Test status
Simulation time 5386138690 ps
CPU time 95.92 seconds
Started Aug 08 04:27:52 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 199764 kb
Host smart-a2c30cac-fb3b-45e8-90fd-4e869b5088d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215163361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2215163361
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2321195805
Short name T471
Test name
Test status
Simulation time 383115333 ps
CPU time 5.14 seconds
Started Aug 08 04:27:53 PM PDT 24
Finished Aug 08 04:27:58 PM PDT 24
Peak memory 199800 kb
Host smart-ed6c4a15-de1a-45fc-81e2-d44ce1a2b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321195805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2321195805
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3464147685
Short name T82
Test name
Test status
Simulation time 11108147092 ps
CPU time 487.94 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:36:35 PM PDT 24
Peak memory 199704 kb
Host smart-99965cdb-b49a-490c-a9c4-36ebcebfae81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464147685 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3464147685
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1469571609
Short name T352
Test name
Test status
Simulation time 7485095905 ps
CPU time 128.44 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:30:14 PM PDT 24
Peak memory 199616 kb
Host smart-f61fbec5-aae9-41cf-9e80-8c59e8b45d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469571609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1469571609
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1574931695
Short name T386
Test name
Test status
Simulation time 48622463 ps
CPU time 0.57 seconds
Started Aug 08 04:27:17 PM PDT 24
Finished Aug 08 04:27:17 PM PDT 24
Peak memory 194600 kb
Host smart-f8390b00-ac95-47cb-afeb-b6dd7a03989b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574931695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1574931695
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.999304251
Short name T320
Test name
Test status
Simulation time 5386283507 ps
CPU time 76.47 seconds
Started Aug 08 04:27:18 PM PDT 24
Finished Aug 08 04:28:35 PM PDT 24
Peak memory 199400 kb
Host smart-f87d2935-5407-46ce-9b99-bb69a201257e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999304251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.999304251
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2273677100
Short name T139
Test name
Test status
Simulation time 10158828880 ps
CPU time 31.1 seconds
Started Aug 08 04:27:21 PM PDT 24
Finished Aug 08 04:27:52 PM PDT 24
Peak memory 199524 kb
Host smart-054ba2f5-ecbc-402f-bf9f-e3f94bdb5f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273677100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2273677100
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.323358353
Short name T79
Test name
Test status
Simulation time 508276121 ps
CPU time 46.98 seconds
Started Aug 08 04:28:26 PM PDT 24
Finished Aug 08 04:29:14 PM PDT 24
Peak memory 253428 kb
Host smart-9240bb41-6ef8-45db-ba65-a64ce6e8cf15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323358353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.323358353
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3690442542
Short name T419
Test name
Test status
Simulation time 3429063031 ps
CPU time 197.73 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:30:34 PM PDT 24
Peak memory 199696 kb
Host smart-df9bad5e-fa8d-462b-a283-830892137544
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690442542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3690442542
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.252017883
Short name T199
Test name
Test status
Simulation time 1668309569 ps
CPU time 46.46 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:28:02 PM PDT 24
Peak memory 199548 kb
Host smart-abafc1fe-96a4-4a3a-9ffe-26cf2c09ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252017883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.252017883
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1661586590
Short name T49
Test name
Test status
Simulation time 137794894 ps
CPU time 0.81 seconds
Started Aug 08 04:27:20 PM PDT 24
Finished Aug 08 04:27:20 PM PDT 24
Peak memory 218052 kb
Host smart-2c385bac-e262-4004-acc6-45daefc88b3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661586590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1661586590
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2604192713
Short name T310
Test name
Test status
Simulation time 71543114 ps
CPU time 3.47 seconds
Started Aug 08 04:27:19 PM PDT 24
Finished Aug 08 04:27:23 PM PDT 24
Peak memory 199572 kb
Host smart-d8fbf30f-bf18-4ab6-b864-0be7512a3f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604192713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2604192713
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.209196480
Short name T73
Test name
Test status
Simulation time 27172577708 ps
CPU time 468.36 seconds
Started Aug 08 04:27:21 PM PDT 24
Finished Aug 08 04:35:10 PM PDT 24
Peak memory 465796 kb
Host smart-49b9bff0-2517-4937-8a97-c9539d7888d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209196480 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.209196480
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.871243432
Short name T403
Test name
Test status
Simulation time 61848879008 ps
CPU time 64.08 seconds
Started Aug 08 04:27:21 PM PDT 24
Finished Aug 08 04:28:25 PM PDT 24
Peak memory 199612 kb
Host smart-2c90a383-21bf-48b6-8828-7d3cf4bcef07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=871243432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.871243432
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3796331539
Short name T185
Test name
Test status
Simulation time 5616050137 ps
CPU time 85.84 seconds
Started Aug 08 04:27:17 PM PDT 24
Finished Aug 08 04:28:43 PM PDT 24
Peak memory 199692 kb
Host smart-8425b0e7-6020-4c5d-9a4f-f2581fcf9f13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3796331539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3796331539
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3458649752
Short name T182
Test name
Test status
Simulation time 9884233985 ps
CPU time 75.71 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:28:32 PM PDT 24
Peak memory 199620 kb
Host smart-209cdb84-7354-44e1-b6cf-cc7fd30ca354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3458649752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3458649752
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2558116175
Short name T361
Test name
Test status
Simulation time 103905400234 ps
CPU time 663.98 seconds
Started Aug 08 04:27:18 PM PDT 24
Finished Aug 08 04:38:22 PM PDT 24
Peak memory 200080 kb
Host smart-347b23c4-f729-497a-a9c2-7f99146b59ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2558116175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2558116175
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1895902988
Short name T387
Test name
Test status
Simulation time 40568882256 ps
CPU time 2159.38 seconds
Started Aug 08 04:27:15 PM PDT 24
Finished Aug 08 05:03:15 PM PDT 24
Peak memory 215696 kb
Host smart-62ec54de-db4c-4d4a-bce4-65028c38c8fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1895902988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1895902988
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2032906875
Short name T335
Test name
Test status
Simulation time 122172416685 ps
CPU time 2319.93 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 05:05:57 PM PDT 24
Peak memory 215168 kb
Host smart-b3316a3c-11c9-4bea-9424-26aeb507ac09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2032906875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2032906875
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2567762025
Short name T373
Test name
Test status
Simulation time 5602776255 ps
CPU time 56.09 seconds
Started Aug 08 04:27:15 PM PDT 24
Finished Aug 08 04:28:11 PM PDT 24
Peak memory 199740 kb
Host smart-9b4fa6b1-f84b-43c3-9496-7415968c6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567762025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2567762025
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3341251962
Short name T187
Test name
Test status
Simulation time 15985707 ps
CPU time 0.62 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:28:04 PM PDT 24
Peak memory 195628 kb
Host smart-7d572143-00f2-4e1d-9117-cfc44f087507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341251962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3341251962
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.32487393
Short name T503
Test name
Test status
Simulation time 202202203 ps
CPU time 11.18 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:16 PM PDT 24
Peak memory 199544 kb
Host smart-e8eed42e-f03d-42dc-b5a3-ada4242a3500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32487393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.32487393
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3129699676
Short name T341
Test name
Test status
Simulation time 12562474194 ps
CPU time 31.4 seconds
Started Aug 08 04:27:59 PM PDT 24
Finished Aug 08 04:28:30 PM PDT 24
Peak memory 199636 kb
Host smart-24d02963-21ef-4778-8a5b-89724e3ea74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129699676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3129699676
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2815195755
Short name T35
Test name
Test status
Simulation time 7252518999 ps
CPU time 329.17 seconds
Started Aug 08 04:27:57 PM PDT 24
Finished Aug 08 04:33:26 PM PDT 24
Peak memory 491372 kb
Host smart-a3fa1c41-4fc4-4094-81a8-f905d5a92572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815195755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2815195755
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1063243662
Short name T75
Test name
Test status
Simulation time 4739679558 ps
CPU time 13.2 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:28:07 PM PDT 24
Peak memory 199720 kb
Host smart-e8da655c-9a88-4989-8458-7acf77368d91
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063243662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1063243662
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2643456025
Short name T301
Test name
Test status
Simulation time 5163407979 ps
CPU time 132.37 seconds
Started Aug 08 04:27:59 PM PDT 24
Finished Aug 08 04:30:11 PM PDT 24
Peak memory 207876 kb
Host smart-00f7b161-a501-43ac-9d0b-d21d24f36e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643456025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2643456025
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1377806857
Short name T131
Test name
Test status
Simulation time 729998483 ps
CPU time 7.31 seconds
Started Aug 08 04:27:52 PM PDT 24
Finished Aug 08 04:27:59 PM PDT 24
Peak memory 199564 kb
Host smart-c69c0c61-fabd-4cd7-a13e-f2b560f2c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377806857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1377806857
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.571519668
Short name T195
Test name
Test status
Simulation time 401067001 ps
CPU time 20.1 seconds
Started Aug 08 04:28:02 PM PDT 24
Finished Aug 08 04:28:22 PM PDT 24
Peak memory 199748 kb
Host smart-58f97a56-3d21-4ac3-bb50-15dbc8492ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571519668 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.571519668
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1134930637
Short name T162
Test name
Test status
Simulation time 284168934 ps
CPU time 11.27 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:15 PM PDT 24
Peak memory 197756 kb
Host smart-a6fd82c5-f327-437d-bb2d-1305c0b1ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134930637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1134930637
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.388913324
Short name T251
Test name
Test status
Simulation time 21743520 ps
CPU time 0.6 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:04 PM PDT 24
Peak memory 194720 kb
Host smart-0e823db4-f8b0-4166-80eb-61b56b8d3786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388913324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.388913324
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1482731840
Short name T379
Test name
Test status
Simulation time 1202578387 ps
CPU time 66.36 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 199560 kb
Host smart-8868e1b8-cfc9-43c1-bf99-26da440a83de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482731840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1482731840
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3672463644
Short name T32
Test name
Test status
Simulation time 391869615 ps
CPU time 6.85 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:28:13 PM PDT 24
Peak memory 199492 kb
Host smart-eee41fa7-9ded-46dc-bd61-5de869611afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672463644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3672463644
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3124250405
Short name T65
Test name
Test status
Simulation time 6311782112 ps
CPU time 524.74 seconds
Started Aug 08 04:27:54 PM PDT 24
Finished Aug 08 04:36:39 PM PDT 24
Peak memory 668992 kb
Host smart-eb914f53-3e8f-4eed-b0b7-e79333ad6257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124250405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3124250405
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2243066829
Short name T219
Test name
Test status
Simulation time 2142976533 ps
CPU time 119.11 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:30:03 PM PDT 24
Peak memory 197772 kb
Host smart-b0d2eee2-9bff-4584-a734-aa7a2eb976bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243066829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2243066829
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4110855567
Short name T258
Test name
Test status
Simulation time 148538030679 ps
CPU time 89.32 seconds
Started Aug 08 04:27:56 PM PDT 24
Finished Aug 08 04:29:25 PM PDT 24
Peak memory 199644 kb
Host smart-de9432c1-72b7-4b98-bf0e-f7716f150125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110855567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4110855567
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3953825518
Short name T261
Test name
Test status
Simulation time 193365513 ps
CPU time 2.53 seconds
Started Aug 08 04:27:55 PM PDT 24
Finished Aug 08 04:27:58 PM PDT 24
Peak memory 199780 kb
Host smart-12977208-6763-4d91-9d5c-dc86875ac6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953825518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3953825518
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1144151005
Short name T451
Test name
Test status
Simulation time 401934494036 ps
CPU time 1101.38 seconds
Started Aug 08 04:27:57 PM PDT 24
Finished Aug 08 04:46:19 PM PDT 24
Peak memory 735332 kb
Host smart-471badb4-e37f-4649-b12d-e7a4d3354ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144151005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1144151005
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4032864568
Short name T392
Test name
Test status
Simulation time 2848706045 ps
CPU time 48.28 seconds
Started Aug 08 04:27:58 PM PDT 24
Finished Aug 08 04:28:46 PM PDT 24
Peak memory 199568 kb
Host smart-01ebfa21-3c4c-4d70-9549-5f1b2b36821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032864568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4032864568
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.857128892
Short name T211
Test name
Test status
Simulation time 13381160 ps
CPU time 0.6 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:05 PM PDT 24
Peak memory 196348 kb
Host smart-1335822c-d6ac-4ae9-824d-0a53a2b2e33e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857128892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.857128892
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.163017871
Short name T322
Test name
Test status
Simulation time 2511747522 ps
CPU time 50.68 seconds
Started Aug 08 04:28:07 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 200088 kb
Host smart-42b42058-2dae-4412-8d41-642d0b0134bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163017871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.163017871
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1640725525
Short name T97
Test name
Test status
Simulation time 1107424023 ps
CPU time 25.75 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:28:29 PM PDT 24
Peak memory 199696 kb
Host smart-98b77017-e0ea-42b6-84c3-466a9ad1a6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640725525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1640725525
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1304649508
Short name T508
Test name
Test status
Simulation time 19613723599 ps
CPU time 280.18 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:33:37 PM PDT 24
Peak memory 658344 kb
Host smart-bb3f16c2-5b22-402d-80fa-9f0b8c317bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304649508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1304649508
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.326590296
Short name T255
Test name
Test status
Simulation time 2797989905 ps
CPU time 142.73 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:30:26 PM PDT 24
Peak memory 199616 kb
Host smart-83ac565a-f7af-44ec-8e69-53fcdae9b87e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326590296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.326590296
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2902189140
Short name T401
Test name
Test status
Simulation time 11952198782 ps
CPU time 71.2 seconds
Started Aug 08 04:28:02 PM PDT 24
Finished Aug 08 04:29:13 PM PDT 24
Peak memory 199584 kb
Host smart-4074a7c0-c5ce-4653-bf55-ed320c177f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902189140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2902189140
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1725782206
Short name T334
Test name
Test status
Simulation time 2072137167 ps
CPU time 10.13 seconds
Started Aug 08 04:28:02 PM PDT 24
Finished Aug 08 04:28:12 PM PDT 24
Peak memory 199692 kb
Host smart-80fe96df-cc40-412e-9251-54fa012081d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725782206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1725782206
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2335163957
Short name T518
Test name
Test status
Simulation time 9719276973 ps
CPU time 1658 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:55:46 PM PDT 24
Peak memory 768152 kb
Host smart-e582e6e8-ed83-4476-9111-a7726787638f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335163957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2335163957
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2091723234
Short name T266
Test name
Test status
Simulation time 1619852914 ps
CPU time 26.55 seconds
Started Aug 08 04:28:09 PM PDT 24
Finished Aug 08 04:28:36 PM PDT 24
Peak memory 199576 kb
Host smart-902fed01-01a0-4656-9b56-f96f1effe69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091723234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2091723234
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2035704385
Short name T397
Test name
Test status
Simulation time 28120370 ps
CPU time 0.59 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:05 PM PDT 24
Peak memory 196492 kb
Host smart-8798a329-4457-4b4f-ae9e-9e68b0d51acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035704385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2035704385
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.668041936
Short name T305
Test name
Test status
Simulation time 1485304819 ps
CPU time 87.68 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:29:36 PM PDT 24
Peak memory 199752 kb
Host smart-58c12aff-6006-4d83-879e-e06bc6389fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668041936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.668041936
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1353264945
Short name T442
Test name
Test status
Simulation time 5175651226 ps
CPU time 17.2 seconds
Started Aug 08 04:28:07 PM PDT 24
Finished Aug 08 04:28:24 PM PDT 24
Peak memory 199612 kb
Host smart-672ae4dc-adbf-408d-9e78-e75494566af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353264945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1353264945
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3656419963
Short name T14
Test name
Test status
Simulation time 2638975705 ps
CPU time 92.91 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:29:38 PM PDT 24
Peak memory 361272 kb
Host smart-424c0104-36c6-45fc-baa0-38aaffed3b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656419963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3656419963
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3234844825
Short name T188
Test name
Test status
Simulation time 12665288409 ps
CPU time 162.29 seconds
Started Aug 08 04:28:12 PM PDT 24
Finished Aug 08 04:30:55 PM PDT 24
Peak memory 199572 kb
Host smart-7aa5d162-718a-43d2-8418-13e9c3d52993
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234844825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3234844825
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1060590569
Short name T431
Test name
Test status
Simulation time 8024591240 ps
CPU time 16.13 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:21 PM PDT 24
Peak memory 199508 kb
Host smart-29f8c9ad-a763-43c0-9ca9-cb0fb82cf870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060590569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1060590569
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1846296231
Short name T349
Test name
Test status
Simulation time 1318493746 ps
CPU time 5.97 seconds
Started Aug 08 04:28:11 PM PDT 24
Finished Aug 08 04:28:17 PM PDT 24
Peak memory 199500 kb
Host smart-149cff12-3b56-4bb8-b176-630af9c1325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846296231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1846296231
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.667531584
Short name T141
Test name
Test status
Simulation time 18599214749 ps
CPU time 1217.94 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:48:24 PM PDT 24
Peak memory 678064 kb
Host smart-333564c9-a4c6-4b4a-b765-ad1666cea3fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667531584 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.667531584
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1629701194
Short name T345
Test name
Test status
Simulation time 124652818936 ps
CPU time 125.36 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:30:10 PM PDT 24
Peak memory 199648 kb
Host smart-cd487e42-d3c4-4e75-9fd2-37c2d31618cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629701194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1629701194
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2697072507
Short name T382
Test name
Test status
Simulation time 61306534 ps
CPU time 0.57 seconds
Started Aug 08 04:28:07 PM PDT 24
Finished Aug 08 04:28:08 PM PDT 24
Peak memory 194484 kb
Host smart-90261075-6658-4fbf-b56e-04186aecd974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697072507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2697072507
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1172370260
Short name T362
Test name
Test status
Simulation time 689148311 ps
CPU time 34.65 seconds
Started Aug 08 04:28:07 PM PDT 24
Finished Aug 08 04:28:42 PM PDT 24
Peak memory 199440 kb
Host smart-798714f3-256d-48d4-a5d3-12b3385b2e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172370260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1172370260
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2124818253
Short name T140
Test name
Test status
Simulation time 3438820375 ps
CPU time 44.19 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:29:02 PM PDT 24
Peak memory 199708 kb
Host smart-0dcbe2e7-df1f-4607-ac11-ec4a8fe7ec06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124818253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2124818253
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3225463803
Short name T256
Test name
Test status
Simulation time 21980257076 ps
CPU time 1124.44 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:46:52 PM PDT 24
Peak memory 756716 kb
Host smart-c70bc382-fcb0-452e-99ae-711b4ec843a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225463803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3225463803
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.861990826
Short name T436
Test name
Test status
Simulation time 4030479166 ps
CPU time 68.46 seconds
Started Aug 08 04:28:14 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 199680 kb
Host smart-8b1a9e7c-7add-42fd-b9e9-7dbc3a3f03b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861990826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.861990826
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.646563083
Short name T179
Test name
Test status
Simulation time 14331898143 ps
CPU time 176.59 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:31:01 PM PDT 24
Peak memory 199660 kb
Host smart-e5d64eff-750a-47d6-8b4a-4fc43e965ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646563083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.646563083
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.455436386
Short name T234
Test name
Test status
Simulation time 997086861 ps
CPU time 16.03 seconds
Started Aug 08 04:28:09 PM PDT 24
Finished Aug 08 04:28:25 PM PDT 24
Peak memory 199564 kb
Host smart-d70f7e9d-b7d5-4b65-b872-310223660e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455436386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.455436386
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3621293777
Short name T480
Test name
Test status
Simulation time 18486947244 ps
CPU time 725.19 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:40:10 PM PDT 24
Peak memory 489608 kb
Host smart-a7dbd152-7cab-4c2f-bfdf-68202e5d52bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621293777 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3621293777
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2128821101
Short name T364
Test name
Test status
Simulation time 15659161 ps
CPU time 0.66 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:06 PM PDT 24
Peak memory 196072 kb
Host smart-28f5a86d-8228-4f2c-8587-df3ecbb2e3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128821101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2128821101
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3782590508
Short name T222
Test name
Test status
Simulation time 50672637 ps
CPU time 0.59 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:17 PM PDT 24
Peak memory 195576 kb
Host smart-d15ee4d2-277e-4a66-8b57-13637ac686dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782590508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3782590508
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1412865270
Short name T242
Test name
Test status
Simulation time 373009088 ps
CPU time 5.86 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:11 PM PDT 24
Peak memory 200032 kb
Host smart-c2daf585-22f0-4e05-8fdf-9ac549bb1aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412865270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1412865270
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3326035929
Short name T484
Test name
Test status
Simulation time 596885638 ps
CPU time 30.69 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:28:39 PM PDT 24
Peak memory 199592 kb
Host smart-c9f6547c-beb8-42b0-908e-e276125a9d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326035929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3326035929
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3453916315
Short name T462
Test name
Test status
Simulation time 19684840581 ps
CPU time 1010.64 seconds
Started Aug 08 04:28:09 PM PDT 24
Finished Aug 08 04:45:00 PM PDT 24
Peak memory 673096 kb
Host smart-e63eef7b-e16e-4f91-b584-27441b0076a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453916315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3453916315
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2374055550
Short name T329
Test name
Test status
Simulation time 9599067160 ps
CPU time 148.61 seconds
Started Aug 08 04:28:07 PM PDT 24
Finished Aug 08 04:30:36 PM PDT 24
Peak memory 199752 kb
Host smart-c7550328-537e-4a8a-84aa-4ac7d0229941
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374055550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2374055550
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1988636513
Short name T366
Test name
Test status
Simulation time 6459985496 ps
CPU time 56.04 seconds
Started Aug 08 04:28:03 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 199612 kb
Host smart-9a082ce8-4512-44bc-a005-ae1bc08d82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988636513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1988636513
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.20413206
Short name T336
Test name
Test status
Simulation time 29916501 ps
CPU time 0.85 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:28:07 PM PDT 24
Peak memory 197580 kb
Host smart-7eda2cdc-73a4-43f2-a92d-50f25654796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20413206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.20413206
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3180180352
Short name T463
Test name
Test status
Simulation time 49712049240 ps
CPU time 1075.64 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:46:01 PM PDT 24
Peak memory 699032 kb
Host smart-55b29f2c-0c67-423d-8777-b92335df4c85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180180352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3180180352
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1258897646
Short name T283
Test name
Test status
Simulation time 6159049026 ps
CPU time 76.36 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:29:21 PM PDT 24
Peak memory 199636 kb
Host smart-8aa9e1fa-4028-45b5-a87c-6da59cd0cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258897646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1258897646
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1550210948
Short name T502
Test name
Test status
Simulation time 18045188 ps
CPU time 0.57 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:28:09 PM PDT 24
Peak memory 195668 kb
Host smart-bd5046bd-9f03-4eac-8658-32cdeb35ea7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550210948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1550210948
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3055239714
Short name T496
Test name
Test status
Simulation time 1606253291 ps
CPU time 97.31 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:29:45 PM PDT 24
Peak memory 199800 kb
Host smart-45fc60af-1350-4508-b781-5608c507e07f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055239714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3055239714
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2078728218
Short name T399
Test name
Test status
Simulation time 7785183534 ps
CPU time 32.89 seconds
Started Aug 08 04:28:09 PM PDT 24
Finished Aug 08 04:28:42 PM PDT 24
Peak memory 199664 kb
Host smart-03b71a9c-e6df-4a31-8f44-27dbbf7e7737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078728218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2078728218
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3739346899
Short name T262
Test name
Test status
Simulation time 16353842305 ps
CPU time 747.3 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:40:34 PM PDT 24
Peak memory 742920 kb
Host smart-12c39154-f532-4312-8906-808a75c05173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739346899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3739346899
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1449167314
Short name T434
Test name
Test status
Simulation time 5436574554 ps
CPU time 93.93 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:29:40 PM PDT 24
Peak memory 199576 kb
Host smart-8afe57d7-77c5-414e-ab84-e8f456888dfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449167314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1449167314
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4159278717
Short name T213
Test name
Test status
Simulation time 5998829118 ps
CPU time 110.58 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:29:57 PM PDT 24
Peak memory 207876 kb
Host smart-bd03a8c0-5af1-4c06-b75a-8f37f0d2aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159278717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4159278717
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1362592201
Short name T494
Test name
Test status
Simulation time 219743012 ps
CPU time 8.81 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:14 PM PDT 24
Peak memory 199708 kb
Host smart-372ba1c2-71b2-405d-b9c4-c3963bfe6383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362592201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1362592201
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.41851387
Short name T91
Test name
Test status
Simulation time 93584343079 ps
CPU time 1290.73 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:49:39 PM PDT 24
Peak memory 715536 kb
Host smart-ef431f78-7106-408a-9a28-b84323c3328d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41851387 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.41851387
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3442746866
Short name T87
Test name
Test status
Simulation time 7062395234 ps
CPU time 127.13 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:30:15 PM PDT 24
Peak memory 199728 kb
Host smart-817de9c5-2bbc-454c-acfa-6099495644e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442746866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3442746866
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3290806961
Short name T340
Test name
Test status
Simulation time 41866167 ps
CPU time 0.6 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:06 PM PDT 24
Peak memory 196308 kb
Host smart-9a81619a-747a-4e06-b072-60331cc6dfd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290806961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3290806961
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1110551347
Short name T354
Test name
Test status
Simulation time 5341941372 ps
CPU time 69.7 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:29:18 PM PDT 24
Peak memory 207836 kb
Host smart-f224e4d1-b2ca-4d48-89a9-1b17e3034651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110551347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1110551347
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2508140998
Short name T158
Test name
Test status
Simulation time 15757460885 ps
CPU time 666.47 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:39:10 PM PDT 24
Peak memory 681148 kb
Host smart-b5b0b040-4de4-4cdb-a7ac-5566c0007cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508140998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2508140998
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2106717016
Short name T147
Test name
Test status
Simulation time 66103429630 ps
CPU time 198.25 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:31:22 PM PDT 24
Peak memory 199616 kb
Host smart-3f27ef7b-8a97-49c3-8ee1-5c2dc08061ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106717016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2106717016
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2924198294
Short name T393
Test name
Test status
Simulation time 7019191210 ps
CPU time 18.03 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:28:26 PM PDT 24
Peak memory 199676 kb
Host smart-9f299223-562a-4403-b40d-02c774143e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924198294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2924198294
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4037876545
Short name T302
Test name
Test status
Simulation time 390695238 ps
CPU time 9.67 seconds
Started Aug 08 04:28:04 PM PDT 24
Finished Aug 08 04:28:14 PM PDT 24
Peak memory 199560 kb
Host smart-68adedce-aeaa-45bd-a7df-8ac6c920b886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037876545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4037876545
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.525131408
Short name T83
Test name
Test status
Simulation time 69085084042 ps
CPU time 2110.27 seconds
Started Aug 08 04:28:10 PM PDT 24
Finished Aug 08 05:03:20 PM PDT 24
Peak memory 752692 kb
Host smart-6bdc0d87-43eb-4913-abf2-44e997b6adf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525131408 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.525131408
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.207449680
Short name T273
Test name
Test status
Simulation time 12691872987 ps
CPU time 45.79 seconds
Started Aug 08 04:28:08 PM PDT 24
Finished Aug 08 04:28:54 PM PDT 24
Peak memory 199824 kb
Host smart-0be4aa41-31a4-4cb1-980a-0e84bb435aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207449680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.207449680
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2844530834
Short name T312
Test name
Test status
Simulation time 21106346 ps
CPU time 0.57 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 04:28:20 PM PDT 24
Peak memory 196332 kb
Host smart-2ff66e0f-941e-4787-804f-a2ef68aa45e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844530834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2844530834
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.19746517
Short name T26
Test name
Test status
Simulation time 2929313724 ps
CPU time 84.64 seconds
Started Aug 08 04:28:14 PM PDT 24
Finished Aug 08 04:29:39 PM PDT 24
Peak memory 199728 kb
Host smart-f84e7c39-3255-4b48-b156-d264938b19ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19746517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.19746517
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2388082109
Short name T236
Test name
Test status
Simulation time 4076119252 ps
CPU time 25.63 seconds
Started Aug 08 04:28:12 PM PDT 24
Finished Aug 08 04:28:38 PM PDT 24
Peak memory 199748 kb
Host smart-281cbd86-c9b2-4ce3-9d54-402b7f32027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388082109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2388082109
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1169183167
Short name T169
Test name
Test status
Simulation time 2276113139 ps
CPU time 385.64 seconds
Started Aug 08 04:28:06 PM PDT 24
Finished Aug 08 04:34:31 PM PDT 24
Peak memory 678376 kb
Host smart-33753178-b50d-4815-85e1-002581f80e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169183167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1169183167
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3416535240
Short name T351
Test name
Test status
Simulation time 2122506796 ps
CPU time 8.29 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:28:27 PM PDT 24
Peak memory 199472 kb
Host smart-2972060e-7b70-4115-b8be-cb02c8e64c1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416535240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3416535240
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1345990931
Short name T511
Test name
Test status
Simulation time 45142937826 ps
CPU time 141.92 seconds
Started Aug 08 04:28:14 PM PDT 24
Finished Aug 08 04:30:36 PM PDT 24
Peak memory 199692 kb
Host smart-54ce34bf-1ed3-4819-9a4b-de3362f8aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345990931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1345990931
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3957491094
Short name T241
Test name
Test status
Simulation time 257610902 ps
CPU time 11.59 seconds
Started Aug 08 04:28:05 PM PDT 24
Finished Aug 08 04:28:17 PM PDT 24
Peak memory 199612 kb
Host smart-e60468b3-ca58-417e-9f5d-b95146029ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957491094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3957491094
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.992807823
Short name T25
Test name
Test status
Simulation time 11395073913 ps
CPU time 1495.68 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:53:13 PM PDT 24
Peak memory 772172 kb
Host smart-756cf094-5f19-473f-b52c-56fbc3850ab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992807823 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.992807823
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2999523008
Short name T513
Test name
Test status
Simulation time 31595209305 ps
CPU time 143.53 seconds
Started Aug 08 04:28:15 PM PDT 24
Finished Aug 08 04:30:38 PM PDT 24
Peak memory 199676 kb
Host smart-00f276ec-a02a-4835-bfd8-eaf7c8eda9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999523008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2999523008
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1785933099
Short name T467
Test name
Test status
Simulation time 42529283 ps
CPU time 0.6 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:28:19 PM PDT 24
Peak memory 195664 kb
Host smart-e461031f-452a-4378-bf9c-eb5cafdf0acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785933099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1785933099
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2388589922
Short name T493
Test name
Test status
Simulation time 11089204296 ps
CPU time 55.66 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:29:15 PM PDT 24
Peak memory 199536 kb
Host smart-6be2297a-04d0-4982-9eaa-d0f6d3ba97fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388589922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2388589922
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.122546316
Short name T1
Test name
Test status
Simulation time 1003163203 ps
CPU time 17.95 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:36 PM PDT 24
Peak memory 199608 kb
Host smart-02f98e58-72e2-4f15-9a79-566c53b893cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122546316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.122546316
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.303665557
Short name T225
Test name
Test status
Simulation time 3931459719 ps
CPU time 674.08 seconds
Started Aug 08 04:28:23 PM PDT 24
Finished Aug 08 04:39:37 PM PDT 24
Peak memory 653276 kb
Host smart-f7802b8b-ab4c-4b08-b062-34891b8b3a49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303665557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.303665557
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2267910448
Short name T145
Test name
Test status
Simulation time 666433819 ps
CPU time 36.22 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 199580 kb
Host smart-a19ee9d8-e66e-44c0-aa47-c546995d3e54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267910448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2267910448
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2092125763
Short name T227
Test name
Test status
Simulation time 36287956845 ps
CPU time 161 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:31:00 PM PDT 24
Peak memory 199588 kb
Host smart-36719c5f-fd21-44a1-a2e9-7abc616d734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092125763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2092125763
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.913467516
Short name T420
Test name
Test status
Simulation time 938359649 ps
CPU time 14.98 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:28:33 PM PDT 24
Peak memory 199612 kb
Host smart-d3cd468a-1b93-4fac-ae2e-be57d50a4cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913467516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.913467516
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.452204524
Short name T116
Test name
Test status
Simulation time 36707262385 ps
CPU time 2201.05 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 05:05:00 PM PDT 24
Peak memory 815412 kb
Host smart-bca7d4b9-fae9-4f83-8b2a-10b4cf9911d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452204524 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.452204524
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1353865485
Short name T407
Test name
Test status
Simulation time 4475306060 ps
CPU time 58 seconds
Started Aug 08 04:28:21 PM PDT 24
Finished Aug 08 04:29:19 PM PDT 24
Peak memory 199668 kb
Host smart-57154aea-781e-470c-961b-8c7aca402377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353865485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1353865485
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1594418782
Short name T308
Test name
Test status
Simulation time 16496791 ps
CPU time 0.58 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:28:59 PM PDT 24
Peak memory 195688 kb
Host smart-064c4e26-e3dd-4563-ab9a-54e8ff40754b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594418782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1594418782
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2353235029
Short name T489
Test name
Test status
Simulation time 579918441 ps
CPU time 30.99 seconds
Started Aug 08 04:27:18 PM PDT 24
Finished Aug 08 04:27:49 PM PDT 24
Peak memory 199460 kb
Host smart-9ed00e4e-44dd-4af7-9f43-bcc57d98211f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353235029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2353235029
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.648713503
Short name T259
Test name
Test status
Simulation time 157030228 ps
CPU time 8.28 seconds
Started Aug 08 04:27:21 PM PDT 24
Finished Aug 08 04:27:29 PM PDT 24
Peak memory 199628 kb
Host smart-aa491681-bae4-4a9b-a42c-f78b40a3cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648713503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.648713503
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.4024511722
Short name T357
Test name
Test status
Simulation time 2634170589 ps
CPU time 548.64 seconds
Started Aug 08 04:27:16 PM PDT 24
Finished Aug 08 04:36:25 PM PDT 24
Peak memory 678776 kb
Host smart-e7b2add9-c761-48c5-a060-8e4f8d5815bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024511722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4024511722
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2213911554
Short name T282
Test name
Test status
Simulation time 5292335187 ps
CPU time 130.55 seconds
Started Aug 08 04:27:17 PM PDT 24
Finished Aug 08 04:29:28 PM PDT 24
Peak memory 199604 kb
Host smart-5bf18c9a-cc6e-45e3-99b7-edf7629f0cf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213911554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2213911554
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3622832365
Short name T318
Test name
Test status
Simulation time 3909667370 ps
CPU time 50.28 seconds
Started Aug 08 04:27:15 PM PDT 24
Finished Aug 08 04:28:06 PM PDT 24
Peak memory 199616 kb
Host smart-95260562-403b-47d6-845c-0c47cf0c723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622832365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3622832365
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.489561355
Short name T19
Test name
Test status
Simulation time 177544020 ps
CPU time 3.19 seconds
Started Aug 08 04:27:17 PM PDT 24
Finished Aug 08 04:27:20 PM PDT 24
Peak memory 199628 kb
Host smart-4df12e0a-a818-403a-b156-0deb37155be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489561355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.489561355
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.435612420
Short name T448
Test name
Test status
Simulation time 66710897996 ps
CPU time 2100.57 seconds
Started Aug 08 04:27:21 PM PDT 24
Finished Aug 08 05:02:22 PM PDT 24
Peak memory 768944 kb
Host smart-5f294ecc-cbec-45f2-b689-00981c984dcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435612420 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.435612420
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.910958707
Short name T270
Test name
Test status
Simulation time 6117474803 ps
CPU time 59.53 seconds
Started Aug 08 04:27:15 PM PDT 24
Finished Aug 08 04:28:14 PM PDT 24
Peak memory 199644 kb
Host smart-4946aeb6-bfae-438d-a1ff-3483ba7ebbb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=910958707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.910958707
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.4080407746
Short name T339
Test name
Test status
Simulation time 13175555380 ps
CPU time 69.47 seconds
Started Aug 08 04:27:13 PM PDT 24
Finished Aug 08 04:28:22 PM PDT 24
Peak memory 199752 kb
Host smart-e06f1f42-4098-40c9-b8ad-d2e5cbdc81f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4080407746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4080407746
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.987634311
Short name T317
Test name
Test status
Simulation time 5539517885 ps
CPU time 89.31 seconds
Started Aug 08 04:27:19 PM PDT 24
Finished Aug 08 04:28:49 PM PDT 24
Peak memory 199676 kb
Host smart-6d5619b4-3e02-4696-9a6e-e5b6a2ea7269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=987634311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.987634311
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.61163860
Short name T421
Test name
Test status
Simulation time 224652916396 ps
CPU time 579.34 seconds
Started Aug 08 04:27:21 PM PDT 24
Finished Aug 08 04:37:01 PM PDT 24
Peak memory 199532 kb
Host smart-934a7141-1e37-49f7-af5a-a59121f0fe72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=61163860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.61163860
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.556443730
Short name T307
Test name
Test status
Simulation time 223649888280 ps
CPU time 2724.63 seconds
Started Aug 08 04:27:20 PM PDT 24
Finished Aug 08 05:12:45 PM PDT 24
Peak memory 215200 kb
Host smart-a2d03bcb-a78f-4a81-9cb4-4fbebd3493c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=556443730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.556443730
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2306175955
Short name T521
Test name
Test status
Simulation time 535617703889 ps
CPU time 2145.7 seconds
Started Aug 08 04:27:15 PM PDT 24
Finished Aug 08 05:03:01 PM PDT 24
Peak memory 215152 kb
Host smart-ed5f44be-d8c6-4306-8e59-d8d99ec5c3b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2306175955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2306175955
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1746962894
Short name T64
Test name
Test status
Simulation time 1742590355 ps
CPU time 5.91 seconds
Started Aug 08 04:27:20 PM PDT 24
Finished Aug 08 04:27:26 PM PDT 24
Peak memory 199772 kb
Host smart-4f3dcc65-db1c-4a7f-a49d-c1236784e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746962894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1746962894
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.228665640
Short name T369
Test name
Test status
Simulation time 44198274 ps
CPU time 0.58 seconds
Started Aug 08 04:28:22 PM PDT 24
Finished Aug 08 04:28:23 PM PDT 24
Peak memory 196388 kb
Host smart-38c157a9-0ce8-48a0-bb9f-616fbc593438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228665640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.228665640
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3515561841
Short name T316
Test name
Test status
Simulation time 3643520670 ps
CPU time 52.7 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:29:12 PM PDT 24
Peak memory 199704 kb
Host smart-bba55241-b2d6-41f3-84c0-f3108e0f5f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515561841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3515561841
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3204875028
Short name T55
Test name
Test status
Simulation time 17090261552 ps
CPU time 52.79 seconds
Started Aug 08 04:28:22 PM PDT 24
Finished Aug 08 04:29:15 PM PDT 24
Peak memory 199672 kb
Host smart-2baa050b-55ed-444e-99a9-3c5852bfd40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204875028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3204875028
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4150905621
Short name T440
Test name
Test status
Simulation time 2111279731 ps
CPU time 155.87 seconds
Started Aug 08 04:28:14 PM PDT 24
Finished Aug 08 04:30:50 PM PDT 24
Peak memory 600860 kb
Host smart-a50084a7-c6e4-4350-b4d6-ed725c7726ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150905621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4150905621
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.437684117
Short name T428
Test name
Test status
Simulation time 3370049541 ps
CPU time 177.88 seconds
Started Aug 08 04:28:23 PM PDT 24
Finished Aug 08 04:31:21 PM PDT 24
Peak memory 199612 kb
Host smart-5d8ec2b9-cfd8-49c2-a79e-bb67801fb3e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437684117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.437684117
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.242036999
Short name T432
Test name
Test status
Simulation time 2654635723 ps
CPU time 35.13 seconds
Started Aug 08 04:28:21 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 199700 kb
Host smart-a3300f5a-b2ce-4829-9085-2a28a3dfeae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242036999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.242036999
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3735631213
Short name T343
Test name
Test status
Simulation time 477931396 ps
CPU time 8.5 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:28:25 PM PDT 24
Peak memory 199620 kb
Host smart-aec2ba88-6dfc-4b21-bbc9-64903fb7b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735631213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3735631213
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3734713551
Short name T85
Test name
Test status
Simulation time 16410763080 ps
CPU time 1632.43 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:55:29 PM PDT 24
Peak memory 746956 kb
Host smart-f0baa838-cf8b-4b61-8a6d-9930e423a811
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734713551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3734713551
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.901378768
Short name T422
Test name
Test status
Simulation time 8193884484 ps
CPU time 94.6 seconds
Started Aug 08 04:28:23 PM PDT 24
Finished Aug 08 04:29:57 PM PDT 24
Peak memory 199572 kb
Host smart-9d4e8e1e-ac69-4e09-acd9-9a4d2783e8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901378768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.901378768
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3254855850
Short name T274
Test name
Test status
Simulation time 13841771 ps
CPU time 0.62 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:28:19 PM PDT 24
Peak memory 195632 kb
Host smart-d3ece24b-a27e-4158-94d7-dfb636c2b51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254855850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3254855850
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1540240622
Short name T280
Test name
Test status
Simulation time 5737468866 ps
CPU time 77.81 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:29:34 PM PDT 24
Peak memory 199824 kb
Host smart-764d3f95-88a5-4426-b628-108b71514b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540240622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1540240622
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1159763129
Short name T295
Test name
Test status
Simulation time 8401202805 ps
CPU time 51.49 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:29:08 PM PDT 24
Peak memory 199636 kb
Host smart-3f314973-7955-4ce8-93b6-b2111ecfed33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159763129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1159763129
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3675794340
Short name T278
Test name
Test status
Simulation time 20088584153 ps
CPU time 986.12 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:44:45 PM PDT 24
Peak memory 725856 kb
Host smart-19fb41f2-753b-425a-81ad-65cec5921be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675794340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3675794340
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2200713255
Short name T363
Test name
Test status
Simulation time 639927935 ps
CPU time 34.42 seconds
Started Aug 08 04:28:15 PM PDT 24
Finished Aug 08 04:28:50 PM PDT 24
Peak memory 199496 kb
Host smart-9ef7e11a-b9c7-4ebd-b249-5e0bd16ff38e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200713255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2200713255
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3435368176
Short name T265
Test name
Test status
Simulation time 2591884235 ps
CPU time 147.43 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:30:46 PM PDT 24
Peak memory 199724 kb
Host smart-f6c8027c-d58f-44be-acd8-166f154cdd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435368176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3435368176
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3502435865
Short name T414
Test name
Test status
Simulation time 526136484 ps
CPU time 3.57 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:28:22 PM PDT 24
Peak memory 199484 kb
Host smart-235881b3-15d7-41c6-99d7-d932700e8942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502435865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3502435865
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3092230921
Short name T80
Test name
Test status
Simulation time 12855547641 ps
CPU time 631.61 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:38:51 PM PDT 24
Peak memory 679360 kb
Host smart-eda11326-8ca4-4658-a4c5-6590b6963172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092230921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3092230921
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1474540220
Short name T523
Test name
Test status
Simulation time 5440456672 ps
CPU time 89.39 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:29:48 PM PDT 24
Peak memory 199672 kb
Host smart-e37f8f9c-08ae-4f30-b23e-2a32f05f8cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474540220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1474540220
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.372981510
Short name T293
Test name
Test status
Simulation time 19830884 ps
CPU time 0.61 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:18 PM PDT 24
Peak memory 195400 kb
Host smart-5ff9e8b5-31b7-4475-b981-7682c921fecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372981510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.372981510
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3813065585
Short name T247
Test name
Test status
Simulation time 1151750234 ps
CPU time 62.97 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:29:21 PM PDT 24
Peak memory 199640 kb
Host smart-926ac4d4-4964-49f0-a2bb-7ddc98ff96e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813065585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3813065585
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3034344594
Short name T136
Test name
Test status
Simulation time 1665768562 ps
CPU time 10.31 seconds
Started Aug 08 04:28:23 PM PDT 24
Finished Aug 08 04:28:33 PM PDT 24
Peak memory 199560 kb
Host smart-4dcc2e58-f8e4-450f-83ea-346d9258a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034344594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3034344594
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2211741838
Short name T240
Test name
Test status
Simulation time 7090604365 ps
CPU time 1287.98 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:49:47 PM PDT 24
Peak memory 754680 kb
Host smart-d7b11bac-26dd-467d-a60a-fd34f0aa4806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211741838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2211741838
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2861848195
Short name T500
Test name
Test status
Simulation time 9132557977 ps
CPU time 129.07 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:30:26 PM PDT 24
Peak memory 199620 kb
Host smart-46eb4353-1b36-4972-aa5a-a4c0110615c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861848195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2861848195
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3928835861
Short name T3
Test name
Test status
Simulation time 32065375743 ps
CPU time 118.13 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:30:16 PM PDT 24
Peak memory 199744 kb
Host smart-f7098fb7-a0ab-4aef-84a0-ca0715d4fca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928835861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3928835861
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1162105201
Short name T6
Test name
Test status
Simulation time 84356430 ps
CPU time 1.02 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:28:20 PM PDT 24
Peak memory 199420 kb
Host smart-25ea637b-4d5b-4e00-925a-882cb4d10852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162105201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1162105201
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2557430416
Short name T479
Test name
Test status
Simulation time 65340125891 ps
CPU time 2217.83 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 05:05:16 PM PDT 24
Peak memory 760016 kb
Host smart-58660cf2-743d-4035-9a44-fa84d28b7ec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557430416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2557430416
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3424982573
Short name T36
Test name
Test status
Simulation time 1908630080 ps
CPU time 18.32 seconds
Started Aug 08 04:28:22 PM PDT 24
Finished Aug 08 04:28:40 PM PDT 24
Peak memory 199596 kb
Host smart-b13af401-00f9-49e6-8447-842947e357ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424982573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3424982573
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4171301444
Short name T46
Test name
Test status
Simulation time 32522778 ps
CPU time 0.6 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:18 PM PDT 24
Peak memory 194820 kb
Host smart-14338c9e-9718-48cb-a412-540c947e5ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171301444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4171301444
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1874599259
Short name T2
Test name
Test status
Simulation time 439676888 ps
CPU time 23.7 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:41 PM PDT 24
Peak memory 199624 kb
Host smart-b6cc95a4-cc24-4bcd-860f-5a732ed35639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874599259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1874599259
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2160478983
Short name T288
Test name
Test status
Simulation time 3536122358 ps
CPU time 51.19 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 199596 kb
Host smart-2c0423ca-8387-4a34-aefd-ce5c3f8dbe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160478983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2160478983
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2302489039
Short name T309
Test name
Test status
Simulation time 18581496755 ps
CPU time 872.31 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:42:50 PM PDT 24
Peak memory 693868 kb
Host smart-a50cb747-bd7f-41cd-9010-2934f8f299a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302489039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2302489039
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2337556493
Short name T303
Test name
Test status
Simulation time 155159908 ps
CPU time 8.04 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:25 PM PDT 24
Peak memory 199564 kb
Host smart-7e511e8d-7f37-436a-8686-f0345d0de37c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337556493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2337556493
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1459423986
Short name T77
Test name
Test status
Simulation time 1984312577 ps
CPU time 104.05 seconds
Started Aug 08 04:28:22 PM PDT 24
Finished Aug 08 04:30:07 PM PDT 24
Peak memory 199536 kb
Host smart-a53e823c-7caf-449b-95b5-a8c530c61a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459423986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1459423986
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.983260155
Short name T230
Test name
Test status
Simulation time 627900008 ps
CPU time 10.41 seconds
Started Aug 08 04:28:21 PM PDT 24
Finished Aug 08 04:28:32 PM PDT 24
Peak memory 199532 kb
Host smart-5fae9ba9-cdfc-43b5-9924-1a56794753f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983260155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.983260155
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.976580890
Short name T44
Test name
Test status
Simulation time 52017886714 ps
CPU time 1371.35 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:51:08 PM PDT 24
Peak memory 722048 kb
Host smart-3a59f3b9-3f57-4b55-9467-fd9243c1570d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976580890 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.976580890
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1534961799
Short name T54
Test name
Test status
Simulation time 2783763628 ps
CPU time 33.48 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:50 PM PDT 24
Peak memory 199692 kb
Host smart-3db30303-a031-45e4-8188-7cd843b09c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534961799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1534961799
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2662269324
Short name T375
Test name
Test status
Simulation time 10737635 ps
CPU time 0.55 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:28:20 PM PDT 24
Peak memory 194488 kb
Host smart-f084b0d7-6be6-4fef-9b00-464ea9111b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662269324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2662269324
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4178394683
Short name T13
Test name
Test status
Simulation time 2393207808 ps
CPU time 66.15 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 199632 kb
Host smart-6e015851-6545-4fd9-b16d-3158e2f6b044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178394683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4178394683
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2837560780
Short name T495
Test name
Test status
Simulation time 8417347863 ps
CPU time 36.17 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:28:52 PM PDT 24
Peak memory 207836 kb
Host smart-d9a97185-23d9-46df-92ac-747a35ca2448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837560780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2837560780
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1652273914
Short name T198
Test name
Test status
Simulation time 5035677516 ps
CPU time 458.45 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:35:56 PM PDT 24
Peak memory 685144 kb
Host smart-d04a0e8b-4a3c-4dca-9f9a-dc9ff6af3c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652273914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1652273914
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2516998244
Short name T470
Test name
Test status
Simulation time 15344791347 ps
CPU time 136.44 seconds
Started Aug 08 04:28:18 PM PDT 24
Finished Aug 08 04:30:35 PM PDT 24
Peak memory 199696 kb
Host smart-3871db2b-5afd-43c6-af4e-cb69a2565e18
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516998244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2516998244
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3428252758
Short name T37
Test name
Test status
Simulation time 14867010708 ps
CPU time 94.88 seconds
Started Aug 08 04:28:23 PM PDT 24
Finished Aug 08 04:29:58 PM PDT 24
Peak memory 207808 kb
Host smart-36de54a9-19a1-4571-bfc6-4090f94274af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428252758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3428252758
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1930118973
Short name T294
Test name
Test status
Simulation time 50197700 ps
CPU time 2.11 seconds
Started Aug 08 04:28:16 PM PDT 24
Finished Aug 08 04:28:18 PM PDT 24
Peak memory 199568 kb
Host smart-3d5c1f93-d67b-41cf-967d-59815a51351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930118973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1930118973
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2873959899
Short name T243
Test name
Test status
Simulation time 2451772195 ps
CPU time 63.03 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:29:20 PM PDT 24
Peak memory 199676 kb
Host smart-2efb806b-001d-4b8d-8c54-1f969d64d50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873959899 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2873959899
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1185220014
Short name T118
Test name
Test status
Simulation time 16675197419 ps
CPU time 81.83 seconds
Started Aug 08 04:28:22 PM PDT 24
Finished Aug 08 04:29:44 PM PDT 24
Peak memory 199676 kb
Host smart-046fc51f-3c87-4b14-9eb7-4d02b781b1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185220014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1185220014
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3572476832
Short name T257
Test name
Test status
Simulation time 32986966 ps
CPU time 0.59 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:18 PM PDT 24
Peak memory 194712 kb
Host smart-a6c96b1b-4a02-4e2c-91d5-86a8089c1183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572476832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3572476832
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1471311559
Short name T224
Test name
Test status
Simulation time 7357815892 ps
CPU time 56.85 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 04:29:17 PM PDT 24
Peak memory 199708 kb
Host smart-a4362645-0d95-49cc-b3e6-7a314c0558d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471311559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1471311559
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3735098873
Short name T206
Test name
Test status
Simulation time 13751187204 ps
CPU time 1423.96 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:52:01 PM PDT 24
Peak memory 765824 kb
Host smart-4d9b09f9-4657-4b0b-ac9e-76f3e1359ac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735098873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3735098873
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3914776517
Short name T510
Test name
Test status
Simulation time 21904221635 ps
CPU time 68.78 seconds
Started Aug 08 04:28:23 PM PDT 24
Finished Aug 08 04:29:32 PM PDT 24
Peak memory 199656 kb
Host smart-35a7fe53-f805-4c94-92bf-407586be29ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914776517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3914776517
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.625977669
Short name T524
Test name
Test status
Simulation time 3723373635 ps
CPU time 106.48 seconds
Started Aug 08 04:28:22 PM PDT 24
Finished Aug 08 04:30:09 PM PDT 24
Peak memory 216064 kb
Host smart-8aa06f93-dd53-4cce-b642-d1215bfadd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625977669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.625977669
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3388355154
Short name T159
Test name
Test status
Simulation time 1259462469 ps
CPU time 11.13 seconds
Started Aug 08 04:28:17 PM PDT 24
Finished Aug 08 04:28:28 PM PDT 24
Peak memory 199636 kb
Host smart-b7483587-1a75-4395-8fe1-758e5db4ace8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388355154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3388355154
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1008503854
Short name T400
Test name
Test status
Simulation time 3182695509 ps
CPU time 166.72 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 04:31:07 PM PDT 24
Peak memory 199728 kb
Host smart-3d182653-54d3-4745-bdf8-6632009fda1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008503854 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1008503854
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1996779029
Short name T156
Test name
Test status
Simulation time 1413259044 ps
CPU time 25.46 seconds
Started Aug 08 04:28:19 PM PDT 24
Finished Aug 08 04:28:44 PM PDT 24
Peak memory 199636 kb
Host smart-95a2bc8a-90e6-4908-9123-99dd6bbc8396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996779029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1996779029
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3144840528
Short name T461
Test name
Test status
Simulation time 12795936 ps
CPU time 0.59 seconds
Started Aug 08 04:28:37 PM PDT 24
Finished Aug 08 04:28:37 PM PDT 24
Peak memory 195644 kb
Host smart-5c82447d-ed63-45b6-9671-fbf76679c20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144840528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3144840528
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.887653557
Short name T155
Test name
Test status
Simulation time 2938121621 ps
CPU time 43.35 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:29:13 PM PDT 24
Peak memory 199692 kb
Host smart-6427d12a-1e21-4e9d-9b91-c5ae2f11b98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887653557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.887653557
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3629344384
Short name T499
Test name
Test status
Simulation time 7951296960 ps
CPU time 53.33 seconds
Started Aug 08 04:28:38 PM PDT 24
Finished Aug 08 04:29:32 PM PDT 24
Peak memory 199680 kb
Host smart-709874ff-f78c-401c-aeb6-6dd4ecc6db8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629344384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3629344384
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2579756755
Short name T522
Test name
Test status
Simulation time 3863099117 ps
CPU time 327.09 seconds
Started Aug 08 04:28:28 PM PDT 24
Finished Aug 08 04:33:55 PM PDT 24
Peak memory 655220 kb
Host smart-5cf2a597-2286-4c5a-b17a-6d86aaecff3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579756755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2579756755
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2313585039
Short name T48
Test name
Test status
Simulation time 2581368400 ps
CPU time 35.29 seconds
Started Aug 08 04:28:34 PM PDT 24
Finished Aug 08 04:29:10 PM PDT 24
Peak memory 199684 kb
Host smart-e01f3236-bce1-439b-a78b-5722556f987e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313585039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2313585039
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3458154448
Short name T481
Test name
Test status
Simulation time 987490499 ps
CPU time 53.87 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:29:26 PM PDT 24
Peak memory 199488 kb
Host smart-00979d68-99a4-41ad-8d5c-195790bdd352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458154448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3458154448
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2188029037
Short name T184
Test name
Test status
Simulation time 1074034068 ps
CPU time 2.75 seconds
Started Aug 08 04:28:30 PM PDT 24
Finished Aug 08 04:28:32 PM PDT 24
Peak memory 199568 kb
Host smart-9891eec7-5c20-40b6-a4d5-19844f2c4c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188029037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2188029037
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.233055467
Short name T194
Test name
Test status
Simulation time 194369429622 ps
CPU time 2108.21 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 05:03:40 PM PDT 24
Peak memory 775104 kb
Host smart-854156e8-4cdf-475f-9684-3348f6ba377b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233055467 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.233055467
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3677927422
Short name T76
Test name
Test status
Simulation time 5964411236 ps
CPU time 45.46 seconds
Started Aug 08 04:28:34 PM PDT 24
Finished Aug 08 04:29:20 PM PDT 24
Peak memory 199680 kb
Host smart-9f7cfcea-2a06-4940-ac38-b1d34e097c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677927422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3677927422
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2962510180
Short name T405
Test name
Test status
Simulation time 45275530 ps
CPU time 0.57 seconds
Started Aug 08 04:28:34 PM PDT 24
Finished Aug 08 04:28:35 PM PDT 24
Peak memory 195712 kb
Host smart-4fc70a2c-46ea-4c89-bd98-715ef7811e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962510180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2962510180
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.979403982
Short name T391
Test name
Test status
Simulation time 698029581 ps
CPU time 39.43 seconds
Started Aug 08 04:28:35 PM PDT 24
Finished Aug 08 04:29:15 PM PDT 24
Peak memory 199572 kb
Host smart-e70edf2a-4ba5-437b-ac7b-9247b5e70daa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979403982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.979403982
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3965328698
Short name T408
Test name
Test status
Simulation time 395139753 ps
CPU time 11.01 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:28:40 PM PDT 24
Peak memory 199540 kb
Host smart-54a67bae-d4b8-4359-9c22-d25726f87534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965328698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3965328698
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3214099395
Short name T180
Test name
Test status
Simulation time 4330797058 ps
CPU time 836.71 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:42:29 PM PDT 24
Peak memory 686412 kb
Host smart-7426595d-966e-4771-b3a8-81b38305a2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214099395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3214099395
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.590413924
Short name T183
Test name
Test status
Simulation time 3716505003 ps
CPU time 31.57 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 199604 kb
Host smart-9943a842-1bd8-4bac-acf6-ab37c1e1afd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590413924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.590413924
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1339163318
Short name T315
Test name
Test status
Simulation time 1439933799 ps
CPU time 18.15 seconds
Started Aug 08 04:28:31 PM PDT 24
Finished Aug 08 04:28:49 PM PDT 24
Peak memory 199564 kb
Host smart-e805b4a1-9c96-4f33-b8bd-c5c4b1efd34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339163318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1339163318
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1244644086
Short name T443
Test name
Test status
Simulation time 448904725 ps
CPU time 1.97 seconds
Started Aug 08 04:28:30 PM PDT 24
Finished Aug 08 04:28:32 PM PDT 24
Peak memory 199552 kb
Host smart-05c90ec2-d03b-4ced-b4c0-7db021af22c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244644086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1244644086
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.776168863
Short name T68
Test name
Test status
Simulation time 23099230 ps
CPU time 0.64 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:28:30 PM PDT 24
Peak memory 195384 kb
Host smart-3a3681ff-7f0e-47fc-92c5-aaabe83a58f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776168863 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.776168863
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3735532669
Short name T89
Test name
Test status
Simulation time 18209507708 ps
CPU time 122.36 seconds
Started Aug 08 04:28:31 PM PDT 24
Finished Aug 08 04:30:33 PM PDT 24
Peak memory 199684 kb
Host smart-2449a973-683f-4df5-9200-072e2231e3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735532669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3735532669
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1164487118
Short name T427
Test name
Test status
Simulation time 27176174 ps
CPU time 0.58 seconds
Started Aug 08 04:28:35 PM PDT 24
Finished Aug 08 04:28:35 PM PDT 24
Peak memory 195304 kb
Host smart-9f08a62e-20b1-457d-97c5-f41772abd608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164487118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1164487118
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4085625919
Short name T466
Test name
Test status
Simulation time 5437893800 ps
CPU time 77.24 seconds
Started Aug 08 04:28:33 PM PDT 24
Finished Aug 08 04:29:50 PM PDT 24
Peak memory 207876 kb
Host smart-49744e5a-37b9-43c7-a7a3-5670503ba7da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085625919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4085625919
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.128372990
Short name T138
Test name
Test status
Simulation time 953946752 ps
CPU time 49.6 seconds
Started Aug 08 04:28:31 PM PDT 24
Finished Aug 08 04:29:21 PM PDT 24
Peak memory 199612 kb
Host smart-70ceb21f-158f-49cd-89ef-3588ebe53110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128372990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.128372990
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3263096268
Short name T454
Test name
Test status
Simulation time 4225150018 ps
CPU time 813.03 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:42:02 PM PDT 24
Peak memory 692352 kb
Host smart-e388c547-9122-4208-91e5-cd771284b049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263096268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3263096268
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.249335879
Short name T376
Test name
Test status
Simulation time 205549365 ps
CPU time 10.99 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:28:43 PM PDT 24
Peak memory 199556 kb
Host smart-a0ecf47b-ddb2-482e-8324-577af4ce316e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249335879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.249335879
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.699127960
Short name T290
Test name
Test status
Simulation time 3153649685 ps
CPU time 52.43 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 199588 kb
Host smart-2c8a76d8-6b7e-4837-8a9d-54c28a7393ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699127960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.699127960
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2234524698
Short name T157
Test name
Test status
Simulation time 66815194 ps
CPU time 0.96 seconds
Started Aug 08 04:28:26 PM PDT 24
Finished Aug 08 04:28:27 PM PDT 24
Peak memory 199460 kb
Host smart-9e38078a-b0d7-44a3-8212-b5f09f4dab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234524698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2234524698
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.695688798
Short name T186
Test name
Test status
Simulation time 69548757489 ps
CPU time 2253.29 seconds
Started Aug 08 04:28:28 PM PDT 24
Finished Aug 08 05:06:01 PM PDT 24
Peak memory 780208 kb
Host smart-7c97eec4-f665-42cb-96cd-a4017dd217d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695688798 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.695688798
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1669230594
Short name T321
Test name
Test status
Simulation time 796010749 ps
CPU time 14.09 seconds
Started Aug 08 04:28:36 PM PDT 24
Finished Aug 08 04:28:51 PM PDT 24
Peak memory 199504 kb
Host smart-bda14835-c5c6-49af-bc1f-e1ca07fc3c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669230594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1669230594
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1438012614
Short name T284
Test name
Test status
Simulation time 13605205 ps
CPU time 0.58 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:28:33 PM PDT 24
Peak memory 194708 kb
Host smart-c1e65d27-4b41-43b5-8018-898fcf0143e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438012614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1438012614
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3393794584
Short name T368
Test name
Test status
Simulation time 26308296370 ps
CPU time 86.09 seconds
Started Aug 08 04:28:34 PM PDT 24
Finished Aug 08 04:30:00 PM PDT 24
Peak memory 199676 kb
Host smart-c1383653-3b43-4b4d-8bfa-a0ebce772811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393794584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3393794584
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2208237373
Short name T306
Test name
Test status
Simulation time 201825153 ps
CPU time 4 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:28:33 PM PDT 24
Peak memory 199504 kb
Host smart-9eddc776-fe59-4711-a8e8-454a7c4e05ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208237373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2208237373
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3054894473
Short name T4
Test name
Test status
Simulation time 8472302682 ps
CPU time 346.71 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:34:14 PM PDT 24
Peak memory 642240 kb
Host smart-f1ed7e7e-d933-440b-90c9-7874b97e9840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054894473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3054894473
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.4170045590
Short name T350
Test name
Test status
Simulation time 2838298144 ps
CPU time 38.37 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 199588 kb
Host smart-c5c2574e-cc18-41a8-8a20-b40376834ab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170045590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.4170045590
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3459364019
Short name T165
Test name
Test status
Simulation time 2851582799 ps
CPU time 37.65 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 199692 kb
Host smart-ddb4f3e1-005d-43aa-82f0-bcb7b1b7228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459364019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3459364019
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.723840871
Short name T525
Test name
Test status
Simulation time 414087513 ps
CPU time 4.78 seconds
Started Aug 08 04:28:31 PM PDT 24
Finished Aug 08 04:28:36 PM PDT 24
Peak memory 199624 kb
Host smart-80c0580c-6a5f-4661-a905-6c6dbfd31848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723840871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.723840871
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2331513661
Short name T67
Test name
Test status
Simulation time 523304055503 ps
CPU time 555.36 seconds
Started Aug 08 04:28:36 PM PDT 24
Finished Aug 08 04:37:52 PM PDT 24
Peak memory 203140 kb
Host smart-5b9b3c21-94a1-4bce-a48e-9a5d0c3d3077
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331513661 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2331513661
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3146925690
Short name T143
Test name
Test status
Simulation time 10179413354 ps
CPU time 46.33 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:29:15 PM PDT 24
Peak memory 199772 kb
Host smart-dfbdafb1-291b-4cf5-86d0-f2f51c0cc143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146925690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3146925690
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1242622305
Short name T29
Test name
Test status
Simulation time 32752723 ps
CPU time 0.58 seconds
Started Aug 08 04:27:34 PM PDT 24
Finished Aug 08 04:27:35 PM PDT 24
Peak memory 196312 kb
Host smart-3b5e0782-6ac1-4c73-bb80-396435a69ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242622305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1242622305
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3032340265
Short name T324
Test name
Test status
Simulation time 750774746 ps
CPU time 4.08 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:27:35 PM PDT 24
Peak memory 199500 kb
Host smart-dc2b8b7e-09fb-4932-8070-372c61b5ba66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032340265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3032340265
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1084632209
Short name T254
Test name
Test status
Simulation time 5114173028 ps
CPU time 67.75 seconds
Started Aug 08 04:27:28 PM PDT 24
Finished Aug 08 04:28:36 PM PDT 24
Peak memory 199484 kb
Host smart-aa3cb151-fa7a-4753-b114-7c299c6f2d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084632209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1084632209
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2930609849
Short name T487
Test name
Test status
Simulation time 3545377069 ps
CPU time 334.88 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:33:06 PM PDT 24
Peak memory 642072 kb
Host smart-90b96a65-f1d7-46be-98a8-6c874e1c2691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930609849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2930609849
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.4138978257
Short name T445
Test name
Test status
Simulation time 2536304903 ps
CPU time 32.21 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:29:15 PM PDT 24
Peak memory 199456 kb
Host smart-87170072-94cf-4d85-bde5-015afaca4808
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138978257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.4138978257
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3008523835
Short name T277
Test name
Test status
Simulation time 4398685552 ps
CPU time 194.57 seconds
Started Aug 08 04:27:36 PM PDT 24
Finished Aug 08 04:30:50 PM PDT 24
Peak memory 199684 kb
Host smart-e7e4088b-0db2-45c5-81f5-4842dc8a9c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008523835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3008523835
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2901410714
Short name T52
Test name
Test status
Simulation time 35297867 ps
CPU time 0.91 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:27:34 PM PDT 24
Peak memory 218108 kb
Host smart-dc451009-057a-4756-a3ec-590e92dc2335
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901410714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2901410714
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3461713775
Short name T486
Test name
Test status
Simulation time 722379699 ps
CPU time 10.08 seconds
Started Aug 08 04:27:28 PM PDT 24
Finished Aug 08 04:27:38 PM PDT 24
Peak memory 199564 kb
Host smart-2673be65-c6a3-49d6-bd0e-5870c7f9f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461713775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3461713775
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1039536153
Short name T332
Test name
Test status
Simulation time 427672165530 ps
CPU time 2382.38 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 05:08:24 PM PDT 24
Peak memory 764736 kb
Host smart-5e6441a7-93a4-4b31-b9af-251e5bdec8fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039536153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1039536153
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.981845673
Short name T21
Test name
Test status
Simulation time 32166778148 ps
CPU time 614.46 seconds
Started Aug 08 04:27:30 PM PDT 24
Finished Aug 08 04:37:45 PM PDT 24
Peak memory 223648 kb
Host smart-ee220b57-bef4-4b07-aeb2-b4c59bf5f0e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981845673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.981845673
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2532131841
Short name T171
Test name
Test status
Simulation time 6731307138 ps
CPU time 41.08 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:28:14 PM PDT 24
Peak memory 199736 kb
Host smart-49f354e6-a42a-4cf6-8aaa-2db15b5016ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2532131841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2532131841
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3057383206
Short name T342
Test name
Test status
Simulation time 6826243556 ps
CPU time 97.7 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:30:37 PM PDT 24
Peak memory 199484 kb
Host smart-76a18ce6-3816-456a-9c17-addcd5cc75c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3057383206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3057383206
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3467349156
Short name T38
Test name
Test status
Simulation time 109741382639 ps
CPU time 139.35 seconds
Started Aug 08 04:27:35 PM PDT 24
Finished Aug 08 04:29:54 PM PDT 24
Peak memory 199624 kb
Host smart-8287fb13-d932-4d41-b17b-ebebd26036ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3467349156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3467349156
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3580576551
Short name T435
Test name
Test status
Simulation time 252532849063 ps
CPU time 594.1 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:37:25 PM PDT 24
Peak memory 199580 kb
Host smart-ed8473b0-e0d1-454d-82e0-97098eedc939
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3580576551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3580576551
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2804999880
Short name T433
Test name
Test status
Simulation time 139047941117 ps
CPU time 2348.55 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 05:06:42 PM PDT 24
Peak memory 216024 kb
Host smart-9b2e4a4b-d31d-4a95-b685-9d4eaf7c23f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2804999880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2804999880
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.488536097
Short name T365
Test name
Test status
Simulation time 129075607391 ps
CPU time 2288.5 seconds
Started Aug 08 04:27:30 PM PDT 24
Finished Aug 08 05:05:39 PM PDT 24
Peak memory 215384 kb
Host smart-df182872-3336-4d5d-8fff-b6c3fc6fdd59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=488536097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.488536097
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1194244270
Short name T296
Test name
Test status
Simulation time 24002009110 ps
CPU time 104 seconds
Started Aug 08 04:27:30 PM PDT 24
Finished Aug 08 04:29:14 PM PDT 24
Peak memory 199560 kb
Host smart-f9d2949c-53e0-4066-9e3b-dae4f27252ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194244270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1194244270
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1426686580
Short name T271
Test name
Test status
Simulation time 34192789 ps
CPU time 0.6 seconds
Started Aug 08 04:28:40 PM PDT 24
Finished Aug 08 04:28:41 PM PDT 24
Peak memory 195404 kb
Host smart-e9687f16-1d3f-46f9-b310-e3a38ac18c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426686580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1426686580
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1398922529
Short name T27
Test name
Test status
Simulation time 1597310018 ps
CPU time 84.82 seconds
Started Aug 08 04:28:28 PM PDT 24
Finished Aug 08 04:29:53 PM PDT 24
Peak memory 199656 kb
Host smart-63790221-c8d7-4f55-b108-197e81273559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398922529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1398922529
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1461833544
Short name T326
Test name
Test status
Simulation time 1673920130 ps
CPU time 18.87 seconds
Started Aug 08 04:28:33 PM PDT 24
Finished Aug 08 04:28:52 PM PDT 24
Peak memory 199592 kb
Host smart-81de37d2-8b53-41d6-a874-6aadd13e3e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461833544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1461833544
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.870646992
Short name T15
Test name
Test status
Simulation time 11516235394 ps
CPU time 745.48 seconds
Started Aug 08 04:28:39 PM PDT 24
Finished Aug 08 04:41:05 PM PDT 24
Peak memory 706364 kb
Host smart-672641a1-0bc5-407c-8bb1-0d63aa69e55f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870646992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.870646992
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.637333815
Short name T154
Test name
Test status
Simulation time 93733523861 ps
CPU time 179.74 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:31:40 PM PDT 24
Peak memory 199756 kb
Host smart-63ae95d8-7180-4b90-878d-ae57c29b0e43
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637333815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.637333815
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1871833941
Short name T325
Test name
Test status
Simulation time 7337002545 ps
CPU time 124.39 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:30:36 PM PDT 24
Peak memory 199632 kb
Host smart-0dc8b827-946a-493b-946d-4db9ee963ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871833941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1871833941
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3384071010
Short name T263
Test name
Test status
Simulation time 764915329 ps
CPU time 8.16 seconds
Started Aug 08 04:28:39 PM PDT 24
Finished Aug 08 04:28:47 PM PDT 24
Peak memory 199652 kb
Host smart-68e937b3-d0b2-4f1c-b25d-c9de8f4773b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384071010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3384071010
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.225781201
Short name T204
Test name
Test status
Simulation time 9694504141 ps
CPU time 38.56 seconds
Started Aug 08 04:28:31 PM PDT 24
Finished Aug 08 04:29:09 PM PDT 24
Peak memory 199680 kb
Host smart-e0cfac98-d9c0-4ae2-b257-8954b87833af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225781201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.225781201
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1131547867
Short name T311
Test name
Test status
Simulation time 44837469 ps
CPU time 0.64 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:28:42 PM PDT 24
Peak memory 196340 kb
Host smart-aec90ecd-3391-4ee0-983a-da74115589ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131547867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1131547867
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4181371332
Short name T450
Test name
Test status
Simulation time 571030438 ps
CPU time 31.85 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:29:04 PM PDT 24
Peak memory 199516 kb
Host smart-3f6b5d04-be74-4aae-bfac-1659ad36991f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181371332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4181371332
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1848613002
Short name T291
Test name
Test status
Simulation time 137747670 ps
CPU time 3.7 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:28:33 PM PDT 24
Peak memory 199576 kb
Host smart-16f91c8d-5338-41ff-8bf0-3658f4c67e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848613002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1848613002
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2054618848
Short name T94
Test name
Test status
Simulation time 2755071367 ps
CPU time 54.69 seconds
Started Aug 08 04:28:46 PM PDT 24
Finished Aug 08 04:29:41 PM PDT 24
Peak memory 396788 kb
Host smart-c037aeb3-2c7a-4a20-ab80-45f6be3abf44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054618848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2054618848
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.926256353
Short name T96
Test name
Test status
Simulation time 16877435 ps
CPU time 0.98 seconds
Started Aug 08 04:28:28 PM PDT 24
Finished Aug 08 04:28:30 PM PDT 24
Peak memory 199380 kb
Host smart-523b783c-e717-4d02-b02b-b70c180c8c48
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926256353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.926256353
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1542438667
Short name T268
Test name
Test status
Simulation time 16451889085 ps
CPU time 216.73 seconds
Started Aug 08 04:28:30 PM PDT 24
Finished Aug 08 04:32:07 PM PDT 24
Peak memory 207928 kb
Host smart-ae27285e-6910-4850-b0d5-01ca54be3d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542438667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1542438667
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1468244421
Short name T482
Test name
Test status
Simulation time 1812046030 ps
CPU time 11.02 seconds
Started Aug 08 04:28:33 PM PDT 24
Finished Aug 08 04:28:44 PM PDT 24
Peak memory 199528 kb
Host smart-f8cf11eb-4fe5-4b62-ae30-af66f80b7e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468244421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1468244421
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.543332102
Short name T473
Test name
Test status
Simulation time 23993944455 ps
CPU time 348.22 seconds
Started Aug 08 04:28:35 PM PDT 24
Finished Aug 08 04:34:24 PM PDT 24
Peak memory 207796 kb
Host smart-8b1da929-54fc-4821-8022-c3979b8dd429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543332102 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.543332102
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.613401403
Short name T164
Test name
Test status
Simulation time 9538518352 ps
CPU time 63 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:29:36 PM PDT 24
Peak memory 199620 kb
Host smart-7a3986d4-bdc2-4220-b796-64ed9d4a9a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613401403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.613401403
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3298927317
Short name T33
Test name
Test status
Simulation time 23897618 ps
CPU time 0.63 seconds
Started Aug 08 04:28:46 PM PDT 24
Finished Aug 08 04:28:47 PM PDT 24
Peak memory 195696 kb
Host smart-7726919c-0636-478b-a448-9dfbdc6138d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298927317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3298927317
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1849635003
Short name T512
Test name
Test status
Simulation time 975835343 ps
CPU time 56.17 seconds
Started Aug 08 04:28:27 PM PDT 24
Finished Aug 08 04:29:23 PM PDT 24
Peak memory 199804 kb
Host smart-f779ed18-cd17-446d-8ef4-a504b249e8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849635003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1849635003
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1605103362
Short name T380
Test name
Test status
Simulation time 701753655 ps
CPU time 10.22 seconds
Started Aug 08 04:28:28 PM PDT 24
Finished Aug 08 04:28:39 PM PDT 24
Peak memory 199800 kb
Host smart-791849c2-3b63-4e13-b3c0-fba05b7bf8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605103362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1605103362
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1391480153
Short name T216
Test name
Test status
Simulation time 122571815 ps
CPU time 1.06 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:28:44 PM PDT 24
Peak memory 199612 kb
Host smart-bfcdc472-404b-4b94-a862-5699342beaaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391480153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1391480153
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.204852602
Short name T514
Test name
Test status
Simulation time 6405374641 ps
CPU time 74.47 seconds
Started Aug 08 04:28:37 PM PDT 24
Finished Aug 08 04:29:52 PM PDT 24
Peak memory 199576 kb
Host smart-d8fb287c-7f32-4405-8e17-0cfca0640b9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204852602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.204852602
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.480681038
Short name T246
Test name
Test status
Simulation time 16322736288 ps
CPU time 134.76 seconds
Started Aug 08 04:28:39 PM PDT 24
Finished Aug 08 04:30:54 PM PDT 24
Peak memory 199720 kb
Host smart-4efd2780-344a-4234-85e9-7e85eca5e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480681038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.480681038
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1169703687
Short name T152
Test name
Test status
Simulation time 5427889255 ps
CPU time 13.72 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:28:55 PM PDT 24
Peak memory 199644 kb
Host smart-b913abe5-12ad-42a9-b62f-6ae8850e1187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169703687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1169703687
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.15352788
Short name T441
Test name
Test status
Simulation time 55943088064 ps
CPU time 902.38 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:43:32 PM PDT 24
Peak memory 651836 kb
Host smart-da1c456f-9338-4098-99dd-c7b50a6313a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15352788 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.15352788
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4205780600
Short name T167
Test name
Test status
Simulation time 600478644 ps
CPU time 8.67 seconds
Started Aug 08 04:28:40 PM PDT 24
Finished Aug 08 04:28:49 PM PDT 24
Peak memory 199520 kb
Host smart-65655148-dee7-4437-b73a-62bffc4ab53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205780600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4205780600
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.418160777
Short name T469
Test name
Test status
Simulation time 53451865 ps
CPU time 0.59 seconds
Started Aug 08 04:28:47 PM PDT 24
Finished Aug 08 04:28:48 PM PDT 24
Peak memory 195680 kb
Host smart-954f6cd6-8266-4bcb-9e66-d7f528ba460d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418160777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.418160777
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3129607504
Short name T28
Test name
Test status
Simulation time 1161858144 ps
CPU time 63.19 seconds
Started Aug 08 04:28:30 PM PDT 24
Finished Aug 08 04:29:33 PM PDT 24
Peak memory 199604 kb
Host smart-3c3c7db3-00c9-4a7f-be1f-ab96079b8ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129607504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3129607504
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1403628703
Short name T338
Test name
Test status
Simulation time 11046553590 ps
CPU time 49.58 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:29:31 PM PDT 24
Peak memory 199940 kb
Host smart-fcaac7f0-5538-4c11-8706-86df2fc35d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403628703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1403628703
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2568972066
Short name T526
Test name
Test status
Simulation time 315586911 ps
CPU time 33.06 seconds
Started Aug 08 04:28:49 PM PDT 24
Finished Aug 08 04:29:22 PM PDT 24
Peak memory 303364 kb
Host smart-d6faecb2-7516-44e1-8c7d-4b5f31cabdcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568972066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2568972066
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1379830136
Short name T424
Test name
Test status
Simulation time 40863362193 ps
CPU time 248.17 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:32:37 PM PDT 24
Peak memory 199660 kb
Host smart-4f5c02a1-104f-4753-ad22-965d9b8500a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379830136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1379830136
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4221572781
Short name T477
Test name
Test status
Simulation time 5592236017 ps
CPU time 25.4 seconds
Started Aug 08 04:28:42 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 199656 kb
Host smart-30eff180-38dd-49d6-99c7-f91d08f41987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221572781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4221572781
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1568998172
Short name T416
Test name
Test status
Simulation time 387811828 ps
CPU time 9.53 seconds
Started Aug 08 04:28:32 PM PDT 24
Finished Aug 08 04:28:41 PM PDT 24
Peak memory 199648 kb
Host smart-29c901f5-1a63-4353-b0f0-2dab5aea0d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568998172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1568998172
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3325980501
Short name T370
Test name
Test status
Simulation time 19212709949 ps
CPU time 151.25 seconds
Started Aug 08 04:28:29 PM PDT 24
Finished Aug 08 04:31:00 PM PDT 24
Peak memory 207928 kb
Host smart-13962ffd-5f52-4e02-a41a-f1d6d3026a71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325980501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3325980501
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3595852858
Short name T86
Test name
Test status
Simulation time 8708310874 ps
CPU time 27.57 seconds
Started Aug 08 04:28:39 PM PDT 24
Finished Aug 08 04:29:06 PM PDT 24
Peak memory 199692 kb
Host smart-d724bd3c-84f1-4d2b-a550-ffde4d514389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595852858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3595852858
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2648921255
Short name T356
Test name
Test status
Simulation time 14189705 ps
CPU time 0.59 seconds
Started Aug 08 04:28:42 PM PDT 24
Finished Aug 08 04:28:42 PM PDT 24
Peak memory 195324 kb
Host smart-37aa8921-5aeb-45fd-a15e-5254c141c0e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648921255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2648921255
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.996286108
Short name T333
Test name
Test status
Simulation time 5738945611 ps
CPU time 77.54 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:30:17 PM PDT 24
Peak memory 215976 kb
Host smart-966fb354-9449-4136-b625-967060eba3d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996286108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.996286108
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2295905175
Short name T220
Test name
Test status
Simulation time 24652210607 ps
CPU time 1293.83 seconds
Started Aug 08 04:28:45 PM PDT 24
Finished Aug 08 04:50:19 PM PDT 24
Peak memory 738284 kb
Host smart-ba6edc4a-e030-406e-befc-620320d5e81e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295905175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2295905175
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1658565442
Short name T458
Test name
Test status
Simulation time 40892452870 ps
CPU time 126.33 seconds
Started Aug 08 04:28:45 PM PDT 24
Finished Aug 08 04:30:51 PM PDT 24
Peak memory 199664 kb
Host smart-06df0a12-5470-44a3-9397-5b9ae5d68726
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658565442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1658565442
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.940869652
Short name T267
Test name
Test status
Simulation time 4403917867 ps
CPU time 114.41 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:30:47 PM PDT 24
Peak memory 207884 kb
Host smart-04a846dc-b45b-4737-9d8b-ceb8a5bda576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940869652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.940869652
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4235129824
Short name T292
Test name
Test status
Simulation time 1580630552 ps
CPU time 5.27 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:28:48 PM PDT 24
Peak memory 199708 kb
Host smart-e1eba73a-d60b-4f70-ad84-9f29c5fd6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235129824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4235129824
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3505810861
Short name T485
Test name
Test status
Simulation time 52177257084 ps
CPU time 615.85 seconds
Started Aug 08 04:28:44 PM PDT 24
Finished Aug 08 04:39:00 PM PDT 24
Peak memory 199688 kb
Host smart-6371ab36-cc48-4340-9c43-55d2b88fd046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505810861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3505810861
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1829922334
Short name T396
Test name
Test status
Simulation time 7486630534 ps
CPU time 72.19 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:30:08 PM PDT 24
Peak memory 199776 kb
Host smart-abb29a04-2027-4123-a9f3-907a3bdc0020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829922334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1829922334
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1600076876
Short name T472
Test name
Test status
Simulation time 14879221 ps
CPU time 0.58 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:28:42 PM PDT 24
Peak memory 195804 kb
Host smart-2071be5d-d64f-45a9-a733-c0e434f4e31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600076876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1600076876
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4244746631
Short name T174
Test name
Test status
Simulation time 1419139639 ps
CPU time 77.09 seconds
Started Aug 08 04:28:45 PM PDT 24
Finished Aug 08 04:30:02 PM PDT 24
Peak memory 199576 kb
Host smart-63cfe22f-d2b7-486c-8996-4c6f868838b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244746631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4244746631
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2885084678
Short name T289
Test name
Test status
Simulation time 6937282732 ps
CPU time 39.64 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:29:33 PM PDT 24
Peak memory 199692 kb
Host smart-9397f5f7-8543-4645-b0c4-dd45f6053f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885084678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2885084678
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2341078014
Short name T465
Test name
Test status
Simulation time 18491734107 ps
CPU time 815.87 seconds
Started Aug 08 04:28:50 PM PDT 24
Finished Aug 08 04:42:26 PM PDT 24
Peak memory 710364 kb
Host smart-df1ba9d2-9500-4dd0-b623-9ba606f76f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341078014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2341078014
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.748337510
Short name T358
Test name
Test status
Simulation time 53707318002 ps
CPU time 174.05 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:31:48 PM PDT 24
Peak memory 199696 kb
Host smart-2e889d89-d9e6-4f0a-b819-085b1a671f13
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748337510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.748337510
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3156849371
Short name T347
Test name
Test status
Simulation time 879718828 ps
CPU time 17.83 seconds
Started Aug 08 04:28:53 PM PDT 24
Finished Aug 08 04:29:11 PM PDT 24
Peak memory 199452 kb
Host smart-cd41fc63-f2e6-412d-9b69-ba001afea29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156849371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3156849371
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2618454970
Short name T286
Test name
Test status
Simulation time 198634527 ps
CPU time 1.96 seconds
Started Aug 08 04:28:44 PM PDT 24
Finished Aug 08 04:28:46 PM PDT 24
Peak memory 199504 kb
Host smart-2c5b8b1e-8e55-4af2-a8a1-7ef4909bf9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618454970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2618454970
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.369707397
Short name T119
Test name
Test status
Simulation time 18223083762 ps
CPU time 1677.19 seconds
Started Aug 08 04:28:40 PM PDT 24
Finished Aug 08 04:56:38 PM PDT 24
Peak memory 661868 kb
Host smart-08e7b286-a14b-4b79-860a-6fe1774670cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369707397 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.369707397
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2602458669
Short name T438
Test name
Test status
Simulation time 11721741171 ps
CPU time 138.49 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:31:14 PM PDT 24
Peak memory 199676 kb
Host smart-4e1f3c54-e5fa-4daa-8297-ec258b72465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602458669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2602458669
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.177012928
Short name T456
Test name
Test status
Simulation time 24139927 ps
CPU time 0.57 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:28:41 PM PDT 24
Peak memory 195652 kb
Host smart-559fccb7-a559-4c45-9432-4d1a3131db82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177012928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.177012928
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2687038085
Short name T56
Test name
Test status
Simulation time 6143837380 ps
CPU time 46.58 seconds
Started Aug 08 04:28:44 PM PDT 24
Finished Aug 08 04:29:30 PM PDT 24
Peak memory 199632 kb
Host smart-6ef47b01-3704-4cff-b040-3f7b717b7aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2687038085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2687038085
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2294947332
Short name T304
Test name
Test status
Simulation time 118674697 ps
CPU time 5.96 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:28:58 PM PDT 24
Peak memory 199544 kb
Host smart-4e184a1b-db36-4852-8db9-c7b0c9855624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294947332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2294947332
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1519746286
Short name T447
Test name
Test status
Simulation time 3092736725 ps
CPU time 493.18 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:37:05 PM PDT 24
Peak memory 695776 kb
Host smart-63f3a733-0f48-42ad-b6b1-cc857af6e9b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519746286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1519746286
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3337626011
Short name T200
Test name
Test status
Simulation time 25741167400 ps
CPU time 150.06 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:31:12 PM PDT 24
Peak memory 199656 kb
Host smart-5405a12c-abe9-4e8f-be8a-23d0c69c7d7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337626011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3337626011
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.288185936
Short name T501
Test name
Test status
Simulation time 1578195419 ps
CPU time 10.33 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 199552 kb
Host smart-e3ab3512-c607-4ab7-a761-705da9375bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288185936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.288185936
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2260972939
Short name T279
Test name
Test status
Simulation time 400269166 ps
CPU time 2.77 seconds
Started Aug 08 04:28:38 PM PDT 24
Finished Aug 08 04:28:41 PM PDT 24
Peak memory 199728 kb
Host smart-a9bd2b60-e301-4a4a-bcc5-5b31a585d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260972939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2260972939
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.10968677
Short name T517
Test name
Test status
Simulation time 340305603332 ps
CPU time 1664.99 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:56:40 PM PDT 24
Peak memory 694396 kb
Host smart-113a8b55-c968-4bfa-9118-9a7ab1c046e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968677 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.10968677
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1278599256
Short name T221
Test name
Test status
Simulation time 7952507044 ps
CPU time 96.47 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:30:34 PM PDT 24
Peak memory 199760 kb
Host smart-8c01febe-98ad-47ae-8700-50b86d0763a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278599256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1278599256
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3994199542
Short name T272
Test name
Test status
Simulation time 24263799 ps
CPU time 0.56 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:56 PM PDT 24
Peak memory 195460 kb
Host smart-e8957918-9874-4d4a-8286-54a555d0a167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994199542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3994199542
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2338075492
Short name T359
Test name
Test status
Simulation time 873978619 ps
CPU time 9.6 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:28:50 PM PDT 24
Peak memory 199608 kb
Host smart-e2969fa7-50d8-42eb-8cbb-c2546d1ebc0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338075492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2338075492
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4096025926
Short name T413
Test name
Test status
Simulation time 919919440 ps
CPU time 23.18 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:29:20 PM PDT 24
Peak memory 199496 kb
Host smart-892316a5-d094-4a64-b3c6-1af2d2300f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096025926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4096025926
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.115185037
Short name T423
Test name
Test status
Simulation time 3062527733 ps
CPU time 456.54 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:36:29 PM PDT 24
Peak memory 639560 kb
Host smart-21b4ef07-83b5-460f-b91a-5c339ac3eb7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115185037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.115185037
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3290225139
Short name T146
Test name
Test status
Simulation time 19768653044 ps
CPU time 179.7 seconds
Started Aug 08 04:28:42 PM PDT 24
Finished Aug 08 04:31:42 PM PDT 24
Peak memory 199560 kb
Host smart-75fd20ef-2a72-4494-b93d-c28cc93eb537
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290225139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3290225139
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1997965984
Short name T166
Test name
Test status
Simulation time 10582848606 ps
CPU time 145.03 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:31:08 PM PDT 24
Peak memory 215872 kb
Host smart-43dbf2f4-9702-4c3f-8e59-6658750a04ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997965984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1997965984
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3075916855
Short name T297
Test name
Test status
Simulation time 888904189 ps
CPU time 13.1 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:29:05 PM PDT 24
Peak memory 199588 kb
Host smart-a309e571-08d5-4354-b7a5-277ad935bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075916855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3075916855
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3473815582
Short name T232
Test name
Test status
Simulation time 16626922438 ps
CPU time 106.45 seconds
Started Aug 08 04:28:51 PM PDT 24
Finished Aug 08 04:30:37 PM PDT 24
Peak memory 207904 kb
Host smart-28e01658-729e-482c-96a5-183df51d535b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473815582 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3473815582
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.948440039
Short name T353
Test name
Test status
Simulation time 2954826112 ps
CPU time 52.2 seconds
Started Aug 08 04:28:48 PM PDT 24
Finished Aug 08 04:29:40 PM PDT 24
Peak memory 199668 kb
Host smart-ed9e764f-f18b-4778-bd5c-b75d2a0b487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948440039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.948440039
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1163230002
Short name T384
Test name
Test status
Simulation time 47753124 ps
CPU time 0.56 seconds
Started Aug 08 04:28:44 PM PDT 24
Finished Aug 08 04:28:44 PM PDT 24
Peak memory 195720 kb
Host smart-c2168026-64e4-4a24-8954-5c3e8e7eb1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163230002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1163230002
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3797927856
Short name T439
Test name
Test status
Simulation time 2593414211 ps
CPU time 75.88 seconds
Started Aug 08 04:28:49 PM PDT 24
Finished Aug 08 04:30:05 PM PDT 24
Peak memory 199704 kb
Host smart-b524f65c-49be-48b7-8da6-4b1c7dc62e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797927856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3797927856
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1216007260
Short name T476
Test name
Test status
Simulation time 4320687267 ps
CPU time 20.21 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:29:03 PM PDT 24
Peak memory 199624 kb
Host smart-88744b1a-d6e0-4db4-8c69-1a3741a8a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216007260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1216007260
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2827232013
Short name T412
Test name
Test status
Simulation time 5533455281 ps
CPU time 1018.87 seconds
Started Aug 08 04:28:51 PM PDT 24
Finished Aug 08 04:45:50 PM PDT 24
Peak memory 696872 kb
Host smart-ccdf58ca-60e5-4964-80d9-d0ddb538807a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827232013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2827232013
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3733138172
Short name T218
Test name
Test status
Simulation time 8390474150 ps
CPU time 136.5 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:30:59 PM PDT 24
Peak memory 199604 kb
Host smart-b1a836b1-25c1-4ec7-9e02-a9757138e4d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733138172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3733138172
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3985879309
Short name T149
Test name
Test status
Simulation time 16456095542 ps
CPU time 137.48 seconds
Started Aug 08 04:28:55 PM PDT 24
Finished Aug 08 04:31:13 PM PDT 24
Peak memory 215872 kb
Host smart-25331d81-bd4b-4184-9ad5-5504bc72e247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985879309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3985879309
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4047658562
Short name T327
Test name
Test status
Simulation time 607966181 ps
CPU time 4.91 seconds
Started Aug 08 04:28:46 PM PDT 24
Finished Aug 08 04:28:51 PM PDT 24
Peak memory 199964 kb
Host smart-f6273b08-2da7-4bff-950b-4d1d65b032c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047658562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4047658562
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2872702847
Short name T70
Test name
Test status
Simulation time 207546885087 ps
CPU time 2092.47 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 05:03:49 PM PDT 24
Peak memory 771700 kb
Host smart-22e630d5-ade9-412f-9f05-4e1307eb03f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872702847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2872702847
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.927551808
Short name T23
Test name
Test status
Simulation time 3893596384 ps
CPU time 41.76 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:29:38 PM PDT 24
Peak memory 199676 kb
Host smart-633198c9-3cd4-4e1e-a71f-f7e96444faf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927551808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.927551808
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2056918244
Short name T34
Test name
Test status
Simulation time 41850393 ps
CPU time 0.56 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 194580 kb
Host smart-4e56aefb-4813-455d-817b-fd76a4fedae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056918244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2056918244
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2854822960
Short name T381
Test name
Test status
Simulation time 584901510 ps
CPU time 30.54 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:29:14 PM PDT 24
Peak memory 199552 kb
Host smart-4120628f-a709-4b37-a0d8-9eee04f6b4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2854822960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2854822960
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.980552616
Short name T42
Test name
Test status
Simulation time 839049058 ps
CPU time 40.78 seconds
Started Aug 08 04:28:49 PM PDT 24
Finished Aug 08 04:29:30 PM PDT 24
Peak memory 199604 kb
Host smart-473388a2-1602-4cf2-abf6-932a7418fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980552616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.980552616
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2238660137
Short name T394
Test name
Test status
Simulation time 32366335396 ps
CPU time 1933.36 seconds
Started Aug 08 04:28:42 PM PDT 24
Finished Aug 08 05:00:56 PM PDT 24
Peak memory 798492 kb
Host smart-802b5a10-d914-48f6-9e5c-3e7afa82b24a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2238660137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2238660137
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2857690036
Short name T189
Test name
Test status
Simulation time 8285496821 ps
CPU time 104.25 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:30:25 PM PDT 24
Peak memory 199876 kb
Host smart-1e13b102-dd55-4439-8913-0972c9a1fcaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857690036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2857690036
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.464648764
Short name T66
Test name
Test status
Simulation time 11097569364 ps
CPU time 183.63 seconds
Started Aug 08 04:28:54 PM PDT 24
Finished Aug 08 04:31:58 PM PDT 24
Peak memory 199584 kb
Host smart-78da5fdf-9584-450e-b271-c9a30dd1c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464648764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.464648764
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2024874022
Short name T245
Test name
Test status
Simulation time 1116145784 ps
CPU time 5.17 seconds
Started Aug 08 04:28:59 PM PDT 24
Finished Aug 08 04:29:04 PM PDT 24
Peak memory 199536 kb
Host smart-379a19c1-0805-4ebe-8770-1c050da9f68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024874022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2024874022
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.216370514
Short name T212
Test name
Test status
Simulation time 68328676266 ps
CPU time 1810.24 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:59:03 PM PDT 24
Peak memory 766104 kb
Host smart-39e7de52-6bb4-4668-9311-ba9695adfa07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216370514 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.216370514
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3990161953
Short name T88
Test name
Test status
Simulation time 2428256007 ps
CPU time 31.49 seconds
Started Aug 08 04:28:52 PM PDT 24
Finished Aug 08 04:29:24 PM PDT 24
Peak memory 199716 kb
Host smart-40c4a907-b9c2-429e-83a5-d6a1e1f92e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990161953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3990161953
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2513759608
Short name T196
Test name
Test status
Simulation time 14519641 ps
CPU time 0.57 seconds
Started Aug 08 04:27:35 PM PDT 24
Finished Aug 08 04:27:35 PM PDT 24
Peak memory 195644 kb
Host smart-81ecca07-103d-4b1d-9ed0-f680cf9cb635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513759608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2513759608
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3337445979
Short name T144
Test name
Test status
Simulation time 3930267099 ps
CPU time 13.53 seconds
Started Aug 08 04:27:29 PM PDT 24
Finished Aug 08 04:27:43 PM PDT 24
Peak memory 199712 kb
Host smart-c99be155-731d-4944-8810-103a8f8e238f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337445979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3337445979
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1621627141
Short name T437
Test name
Test status
Simulation time 2825834477 ps
CPU time 34.94 seconds
Started Aug 08 04:27:29 PM PDT 24
Finished Aug 08 04:28:04 PM PDT 24
Peak memory 199628 kb
Host smart-725fc76b-126f-49ab-8ec2-0a4b5de3ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621627141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1621627141
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3027948029
Short name T410
Test name
Test status
Simulation time 3880601291 ps
CPU time 801.74 seconds
Started Aug 08 04:27:32 PM PDT 24
Finished Aug 08 04:40:54 PM PDT 24
Peak memory 671316 kb
Host smart-f95508eb-c985-4f87-8e32-7aa943face25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027948029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3027948029
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.482024026
Short name T378
Test name
Test status
Simulation time 11388414815 ps
CPU time 17.95 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:27:51 PM PDT 24
Peak memory 199564 kb
Host smart-6d4146e8-605f-43ac-887d-95f60a432824
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482024026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.482024026
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1085095110
Short name T78
Test name
Test status
Simulation time 851923114 ps
CPU time 10.51 seconds
Started Aug 08 04:28:41 PM PDT 24
Finished Aug 08 04:28:52 PM PDT 24
Peak memory 199364 kb
Host smart-df8a49ae-ffb1-4184-a255-a43181465524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085095110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1085095110
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.301441828
Short name T275
Test name
Test status
Simulation time 310585092 ps
CPU time 4.95 seconds
Started Aug 08 04:27:35 PM PDT 24
Finished Aug 08 04:27:40 PM PDT 24
Peak memory 199552 kb
Host smart-fcd77bb4-b576-468f-8a9f-6c1a69d0920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301441828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.301441828
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4293784595
Short name T71
Test name
Test status
Simulation time 257150619639 ps
CPU time 952.08 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:43:25 PM PDT 24
Peak memory 252852 kb
Host smart-cbb72c0a-4dd9-40e6-8bd7-de73bec37877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293784595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4293784595
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.639688080
Short name T22
Test name
Test status
Simulation time 116755714085 ps
CPU time 3261.03 seconds
Started Aug 08 04:27:30 PM PDT 24
Finished Aug 08 05:21:51 PM PDT 24
Peak memory 794176 kb
Host smart-0112786b-df3d-4a83-bd52-caf030683acb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639688080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.639688080
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2555773447
Short name T344
Test name
Test status
Simulation time 150399855 ps
CPU time 8.19 seconds
Started Aug 08 04:28:43 PM PDT 24
Finished Aug 08 04:28:51 PM PDT 24
Peak memory 199252 kb
Host smart-2b940d70-2510-4228-9ed1-eabe52899b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555773447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2555773447
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4133724619
Short name T491
Test name
Test status
Simulation time 15257644 ps
CPU time 0.56 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:27:34 PM PDT 24
Peak memory 195612 kb
Host smart-2dd7e5bc-ff58-46c5-b291-e2d438a21c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133724619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4133724619
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3751882569
Short name T223
Test name
Test status
Simulation time 24141802949 ps
CPU time 78.75 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:28:50 PM PDT 24
Peak memory 199536 kb
Host smart-f6a603b0-06de-4d70-9a61-ab7720f7d566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751882569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3751882569
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.809677673
Short name T285
Test name
Test status
Simulation time 691882009 ps
CPU time 18.38 seconds
Started Aug 08 04:27:30 PM PDT 24
Finished Aug 08 04:27:48 PM PDT 24
Peak memory 199600 kb
Host smart-78791993-db6e-44fc-bcc3-891b0df8c2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809677673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.809677673
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3228077601
Short name T168
Test name
Test status
Simulation time 34654871053 ps
CPU time 1259.57 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:48:31 PM PDT 24
Peak memory 648752 kb
Host smart-20564d84-5e3b-47a1-8bcf-38f8e2f83c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228077601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3228077601
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1216129206
Short name T74
Test name
Test status
Simulation time 108093987 ps
CPU time 0.99 seconds
Started Aug 08 04:27:29 PM PDT 24
Finished Aug 08 04:27:30 PM PDT 24
Peak memory 198904 kb
Host smart-0acfaf39-3108-4ba2-ac6e-5563708738e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216129206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1216129206
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4162912917
Short name T201
Test name
Test status
Simulation time 1447208036 ps
CPU time 78.84 seconds
Started Aug 08 04:27:30 PM PDT 24
Finished Aug 08 04:28:49 PM PDT 24
Peak memory 199552 kb
Host smart-2215fa1c-8e38-434b-9ba9-d9a27b7dafcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162912917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4162912917
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.285005278
Short name T151
Test name
Test status
Simulation time 2117531729 ps
CPU time 8.59 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:27:41 PM PDT 24
Peak memory 199588 kb
Host smart-2a920d3c-20c1-447d-b7df-fd557ee6983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285005278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.285005278
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.753534325
Short name T249
Test name
Test status
Simulation time 52214438186 ps
CPU time 1114.33 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:46:08 PM PDT 24
Peak memory 643392 kb
Host smart-24051dee-2616-4426-bd33-dc343725c6f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753534325 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.753534325
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3359233780
Short name T61
Test name
Test status
Simulation time 49115915118 ps
CPU time 198.33 seconds
Started Aug 08 04:27:32 PM PDT 24
Finished Aug 08 04:30:51 PM PDT 24
Peak memory 208152 kb
Host smart-1db9d1d0-76e9-4b5b-8ba5-c04fafc6148e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359233780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3359233780
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4208918390
Short name T84
Test name
Test status
Simulation time 5797495672 ps
CPU time 69.99 seconds
Started Aug 08 04:27:31 PM PDT 24
Finished Aug 08 04:28:41 PM PDT 24
Peak memory 199584 kb
Host smart-888c1dc3-4a64-4ad5-8ee7-22f944071f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208918390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4208918390
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3081789848
Short name T398
Test name
Test status
Simulation time 16135406 ps
CPU time 0.59 seconds
Started Aug 08 04:27:41 PM PDT 24
Finished Aug 08 04:27:42 PM PDT 24
Peak memory 195708 kb
Host smart-c48a783b-abc6-4201-93cd-5b15b6661bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081789848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3081789848
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2799490277
Short name T148
Test name
Test status
Simulation time 4527203740 ps
CPU time 58.68 seconds
Started Aug 08 04:28:42 PM PDT 24
Finished Aug 08 04:29:41 PM PDT 24
Peak memory 199432 kb
Host smart-df2306f0-f04f-41f0-907f-92d17bc93b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799490277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2799490277
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.868803119
Short name T383
Test name
Test status
Simulation time 5231804919 ps
CPU time 937.62 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:44:36 PM PDT 24
Peak memory 705188 kb
Host smart-a3101e84-b9d6-4282-b2bd-c226188ad3ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868803119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.868803119
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3986555438
Short name T205
Test name
Test status
Simulation time 29945176033 ps
CPU time 122.03 seconds
Started Aug 08 04:29:00 PM PDT 24
Finished Aug 08 04:31:02 PM PDT 24
Peak memory 199680 kb
Host smart-164db4ef-5d5f-4688-8c65-5ad90db56f0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986555438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3986555438
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2416737192
Short name T488
Test name
Test status
Simulation time 9712548809 ps
CPU time 162.31 seconds
Started Aug 08 04:28:39 PM PDT 24
Finished Aug 08 04:31:22 PM PDT 24
Peak memory 215856 kb
Host smart-0de257b4-9274-48e0-9e7c-9d9c13e8b5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416737192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2416737192
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1822158813
Short name T455
Test name
Test status
Simulation time 597726498 ps
CPU time 10.29 seconds
Started Aug 08 04:28:56 PM PDT 24
Finished Aug 08 04:29:07 PM PDT 24
Peak memory 199592 kb
Host smart-299b6a52-10c2-4de5-b47a-4fdb5bd9d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822158813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1822158813
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.815953699
Short name T72
Test name
Test status
Simulation time 70468696783 ps
CPU time 215.63 seconds
Started Aug 08 04:28:42 PM PDT 24
Finished Aug 08 04:32:18 PM PDT 24
Peak memory 207640 kb
Host smart-3a938a1f-bdbd-46e8-96bc-0ef519f477b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815953699 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.815953699
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2450334741
Short name T509
Test name
Test status
Simulation time 1155751745 ps
CPU time 50.53 seconds
Started Aug 08 04:27:33 PM PDT 24
Finished Aug 08 04:28:24 PM PDT 24
Peak memory 199556 kb
Host smart-203c70ef-5dc2-4052-afb5-05920d55a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450334741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2450334741
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3884916686
Short name T260
Test name
Test status
Simulation time 11994475 ps
CPU time 0.61 seconds
Started Aug 08 04:28:20 PM PDT 24
Finished Aug 08 04:28:21 PM PDT 24
Peak memory 194536 kb
Host smart-2b5c3665-21fa-4abb-803c-faf91dde5b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884916686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3884916686
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1057722363
Short name T281
Test name
Test status
Simulation time 5517330756 ps
CPU time 74.58 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:30:12 PM PDT 24
Peak memory 199660 kb
Host smart-bc6fcb52-96a1-42d7-9aed-dd05c1a47314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057722363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1057722363
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2588084540
Short name T505
Test name
Test status
Simulation time 1951373709 ps
CPU time 24.84 seconds
Started Aug 08 04:27:42 PM PDT 24
Finished Aug 08 04:28:07 PM PDT 24
Peak memory 199472 kb
Host smart-ce02e80d-0595-472b-a071-c9d3ec365fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588084540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2588084540
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3357549826
Short name T406
Test name
Test status
Simulation time 4220456252 ps
CPU time 737.16 seconds
Started Aug 08 04:27:41 PM PDT 24
Finished Aug 08 04:39:59 PM PDT 24
Peak memory 687592 kb
Host smart-a8858f67-ad16-472e-9979-86726abfbee1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357549826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3357549826
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.48535267
Short name T264
Test name
Test status
Simulation time 7561230624 ps
CPU time 93.79 seconds
Started Aug 08 04:27:42 PM PDT 24
Finished Aug 08 04:29:16 PM PDT 24
Peak memory 199604 kb
Host smart-865137c3-9673-4a82-9969-f7161ae96657
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48535267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.48535267
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1824001172
Short name T175
Test name
Test status
Simulation time 12048767803 ps
CPU time 146.11 seconds
Started Aug 08 04:27:46 PM PDT 24
Finished Aug 08 04:30:12 PM PDT 24
Peak memory 199760 kb
Host smart-6694e157-8cc7-493a-839a-5836a86661c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824001172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1824001172
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3673599120
Short name T527
Test name
Test status
Simulation time 201961422 ps
CPU time 2.17 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:48 PM PDT 24
Peak memory 199520 kb
Host smart-8275f233-fe79-45cd-a221-13f274077b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673599120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3673599120
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.318142541
Short name T192
Test name
Test status
Simulation time 5391153596 ps
CPU time 76 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:29:00 PM PDT 24
Peak memory 199652 kb
Host smart-81271247-04c1-42de-9a30-a73ba61530d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318142541 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.318142541
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1312064091
Short name T11
Test name
Test status
Simulation time 221822458947 ps
CPU time 1128.81 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:46:32 PM PDT 24
Peak memory 676932 kb
Host smart-36905fbf-493e-47e1-a2fb-6bfb158fe4d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312064091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1312064091
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.728923814
Short name T300
Test name
Test status
Simulation time 779359283 ps
CPU time 37.9 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:28:22 PM PDT 24
Peak memory 199540 kb
Host smart-86a89c5f-fb6b-42f2-aa45-9b8ca9b80c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728923814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.728923814
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1668846384
Short name T153
Test name
Test status
Simulation time 19414216 ps
CPU time 0.58 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:46 PM PDT 24
Peak memory 194580 kb
Host smart-ad754160-361e-4342-b09a-89fff770bcf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668846384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1668846384
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.171197641
Short name T287
Test name
Test status
Simulation time 5619050506 ps
CPU time 73.58 seconds
Started Aug 08 04:27:44 PM PDT 24
Finished Aug 08 04:28:57 PM PDT 24
Peak memory 199632 kb
Host smart-f2580c6a-edab-4eb8-8f85-d98c4514721e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171197641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.171197641
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4093311531
Short name T137
Test name
Test status
Simulation time 3681488613 ps
CPU time 13.71 seconds
Started Aug 08 04:28:58 PM PDT 24
Finished Aug 08 04:29:11 PM PDT 24
Peak memory 199416 kb
Host smart-15a34156-060e-4000-9bab-9fa1a92a1601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093311531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4093311531
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3264725812
Short name T464
Test name
Test status
Simulation time 7665601873 ps
CPU time 657.75 seconds
Started Aug 08 04:28:57 PM PDT 24
Finished Aug 08 04:39:55 PM PDT 24
Peak memory 664032 kb
Host smart-b2a87317-7b06-42e3-9d7b-97f00e935e2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264725812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3264725812
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3519605206
Short name T181
Test name
Test status
Simulation time 350881875 ps
CPU time 4.98 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 04:27:50 PM PDT 24
Peak memory 198672 kb
Host smart-deef040a-6b07-4f12-85c0-cad970438ad6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519605206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3519605206
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3771638169
Short name T237
Test name
Test status
Simulation time 59224777950 ps
CPU time 113.25 seconds
Started Aug 08 04:27:42 PM PDT 24
Finished Aug 08 04:29:36 PM PDT 24
Peak memory 199820 kb
Host smart-b5c80ba4-5686-4ef6-b425-bf7428ef7195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771638169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3771638169
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.682008941
Short name T163
Test name
Test status
Simulation time 2301529001 ps
CPU time 9.6 seconds
Started Aug 08 04:27:47 PM PDT 24
Finished Aug 08 04:27:57 PM PDT 24
Peak memory 199764 kb
Host smart-0d1c6a84-9296-466f-9d88-ac8592c8aa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682008941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.682008941
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2515809533
Short name T483
Test name
Test status
Simulation time 111414090913 ps
CPU time 2051.8 seconds
Started Aug 08 04:27:45 PM PDT 24
Finished Aug 08 05:01:57 PM PDT 24
Peak memory 772388 kb
Host smart-e093ddba-5ba0-4d4c-bf82-d7013323f818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515809533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2515809533
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3005619917
Short name T62
Test name
Test status
Simulation time 10065127737 ps
CPU time 381.01 seconds
Started Aug 08 04:27:50 PM PDT 24
Finished Aug 08 04:34:11 PM PDT 24
Peak memory 454604 kb
Host smart-a3dbbcfd-35d9-4728-a1f3-4ac460d7b03b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005619917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3005619917
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2636195514
Short name T214
Test name
Test status
Simulation time 13865588481 ps
CPU time 81.38 seconds
Started Aug 08 04:27:43 PM PDT 24
Finished Aug 08 04:29:04 PM PDT 24
Peak memory 199620 kb
Host smart-ac62a681-e96a-49c6-8ceb-4f3eabdade57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636195514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2636195514
Directory /workspace/9.hmac_wipe_secret/latest
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