Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20307685	1			T1	21090		T2	4639		T4	54689
all_values[1]	20307685	1			T1	21090		T2	4639		T4	54689
all_values[2]	20307685	1			T1	21090		T2	4639		T4	54689

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250527

1

T4

1929

T8

118

T7

1980

auto[1]

60672528

1

T1

63270

T2

13917

T4

162138

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51723791

1

T1

53628

T2

11596

T4

133343

auto[1]

9199264

1

T1

9642

T2

2321

T4

30724

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	91079	1			T7	990		T25	654		T111	94
all_values[0]	auto[0]	auto[1]	373	1			T111	2		T9	6		T24	2
all_values[0]	auto[1]	auto[0]	20194484	1			T1	21069		T2	4635		T4	54678
all_values[0]	auto[1]	auto[1]	21749	1			T1	21		T2	4		T4	11
all_values[1]	auto[0]	auto[0]	77204	1			T7	990		T5	2		T112	116
all_values[1]	auto[0]	auto[1]	232	1			T9	4		T10	1		T44	4
all_values[1]	auto[1]	auto[0]	20229898	1			T1	21090		T2	4639		T4	54689
all_values[1]	auto[1]	auto[1]	351	1			T6	2		T9	5		T10	3
all_values[2]	auto[0]	auto[0]	45949	1			T4	481		T8	6		T5	2
all_values[2]	auto[0]	auto[1]	35690	1			T4	1448		T8	112		T23	95
all_values[2]	auto[1]	auto[0]	11085177	1			T1	11469		T2	2322		T4	23495
all_values[2]	auto[1]	auto[1]	9140869	1			T1	9621		T2	2317		T4	29265