Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146493

1

T1

36

T8

22

T7

26

auto[1]

136358

1

T1

24

T2

8

T4

58

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	109320	1			T1	22		T2	4		T4	11
len_1026_2046	6672	1			T1	2		T5	48		T6	63
len_514_1022	3979	1			T5	20		T6	15		T23	7
len_2_510	4638	1			T1	1		T5	23		T6	8
len_2056	275	1			T120	4		T9	87		T80	2
len_2048	390	1			T4	1		T5	3		T6	1
len_2040	200	1			T112	1		T9	5		T81	17
len_1032	216	1			T5	2		T6	2		T9	9
len_1024	1889	1			T5	3		T6	90		T23	3
len_1016	375	1			T5	4		T9	5		T80	5
len_520	441	1			T5	4		T19	2		T121	1
len_512	448	1			T5	5		T6	3		T112	1
len_504	175	1			T5	1		T121	1		T9	10
len_8	1753	1			T4	15		T5	12		T6	7
len_0	10655	1			T1	5		T4	2		T8	9

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

103

1

T6

4

T122

2

T24

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	58040	1			T1	13		T8	6		T7	10
auto[0]	len_1026_2046	3183	1			T1	2		T5	39		T6	23
auto[0]	len_514_1022	2610	1			T5	16		T6	9		T23	4
auto[0]	len_2_510	3241	1			T5	19		T6	5		T121	65
auto[0]	len_2056	188	1			T120	1		T9	84		T81	8
auto[0]	len_2048	256	1			T5	3		T6	1		T23	2
auto[0]	len_2040	112	1			T112	1		T9	2		T81	6
auto[0]	len_1032	122	1			T5	2		T9	6		T80	2
auto[0]	len_1024	280	1			T5	3		T6	4		T23	2
auto[0]	len_1016	156	1			T5	1		T9	3		T80	4
auto[0]	len_520	307	1			T5	4		T19	1		T121	1
auto[0]	len_512	253	1			T5	4		T6	3		T112	1
auto[0]	len_504	94	1			T121	1		T9	6		T69	2
auto[0]	len_8	373	1			T121	1		T123	1		T71	338
auto[0]	len_0	4032	1			T1	3		T8	5		T7	3
auto[1]	len_2050_plus	51280	1			T1	9		T2	4		T4	11
auto[1]	len_1026_2046	3489	1			T5	9		T6	40		T23	5
auto[1]	len_514_1022	1369	1			T5	4		T6	6		T23	3
auto[1]	len_2_510	1397	1			T1	1		T5	4		T6	3
auto[1]	len_2056	87	1			T120	3		T9	3		T80	2
auto[1]	len_2048	134	1			T4	1		T9	1		T69	4
auto[1]	len_2040	88	1			T9	3		T81	11		T71	2
auto[1]	len_1032	94	1			T6	2		T9	3		T80	2
auto[1]	len_1024	1609	1			T6	86		T23	1		T9	3
auto[1]	len_1016	219	1			T5	3		T9	2		T80	1
auto[1]	len_520	134	1			T19	1		T9	2		T81	1
auto[1]	len_512	195	1			T5	1		T9	4		T69	2
auto[1]	len_504	81	1			T5	1		T9	4		T69	2
auto[1]	len_8	1380	1			T4	15		T5	12		T6	7
auto[1]	len_0	6623	1			T1	2		T4	2		T8	4

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

67

1

T6

4

T24

1

T70

1

auto[1]

len_upper

36

1

T122

2

T17

2

T124

2