Group : hmac_env_pkg::hmac_env_cov::status_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4952549 1 T1 4651 T2 1800 T4 12001
auto[1] 3421180 1 T1 5858 T2 519 T4 15148


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3372848 1 T1 4228 T2 1779 T4 19605
auto[1] 5000881 1 T1 6281 T2 540 T4 7544


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3685671 1 T1 3762 T2 514 T8 1592
auto[1] 4688058 1 T1 6747 T2 1805 T4 27149


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5015762 1 T1 4972 T2 1185 T4 12630
auto[1] 3357967 1 T1 5537 T2 1134 T4 14519


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7502965 1 T1 9386 T2 2293 T4 25583
fifo_depth[1] 131185 1 T1 178 T2 16 T4 216
fifo_depth[2] 99111 1 T1 172 T2 7 T4 242
fifo_depth[3] 77460 1 T1 184 T2 1 T4 233
fifo_depth[4] 71775 1 T1 174 T4 244 T7 160
fifo_depth[5] 57155 1 T1 165 T2 2 T4 225
fifo_depth[6] 46945 1 T1 101 T4 189 T7 110
fifo_depth[7] 31997 1 T1 78 T4 113 T7 72


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 870764 1 T1 1123 T2 26 T4 1566
auto[1] 7502965 1 T1 9386 T2 2293 T4 25583


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8357749 1 T1 10509 T2 2319 T4 27149
auto[1] 15980 1 T6 625 T9 293 T81 914


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 36942 1 T1 101 T8 8 T5 16
auto[0] auto[0] auto[0] auto[0] auto[1] 42139 1 T1 94 T2 15 T7 71
auto[0] auto[0] auto[0] auto[1] auto[0] 43035 1 T5 14 T6 995 T25 3
auto[0] auto[0] auto[0] auto[1] auto[1] 56330 1 T1 54 T7 174 T5 17
auto[0] auto[0] auto[1] auto[0] auto[0] 147324 1 T1 93 T7 114 T5 68
auto[0] auto[0] auto[1] auto[0] auto[1] 40636 1 T7 151 T5 32 T19 99
auto[0] auto[0] auto[1] auto[1] auto[0] 44827 1 T1 168 T7 69 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] 35107 1 T1 138 T7 147 T6 4
auto[0] auto[1] auto[0] auto[0] auto[0] 55403 1 T1 120 T5 52 T6 1167
auto[0] auto[1] auto[0] auto[0] auto[1] 49736 1 T4 730 T5 25 T6 1071
auto[0] auto[1] auto[0] auto[1] auto[0] 52711 1 T4 45 T7 80 T5 117
auto[0] auto[1] auto[0] auto[1] auto[1] 51842 1 T4 791 T7 214 T6 1359
auto[0] auto[1] auto[1] auto[0] auto[0] 61225 1 T1 76 T5 51 T19 194
auto[0] auto[1] auto[1] auto[0] auto[1] 48381 1 T1 101 T7 91 T5 27
auto[0] auto[1] auto[1] auto[1] auto[0] 65802 1 T2 11 T5 1 T19 117
auto[0] auto[1] auto[1] auto[1] auto[1] 39324 1 T1 178 T5 3 T6 434
auto[1] auto[0] auto[0] auto[0] auto[0] 193562 1 T1 356 T8 348 T5 552
auto[1] auto[0] auto[0] auto[0] auto[1] 198728 1 T1 790 T2 499 T8 283
auto[1] auto[0] auto[0] auto[1] auto[0] 219946 1 T1 290 T8 2 T7 2
auto[1] auto[0] auto[0] auto[1] auto[1] 222976 1 T1 407 T7 483 T5 578
auto[1] auto[0] auto[1] auto[0] auto[0] 1767013 1 T1 535 T8 238 T7 601
auto[1] auto[0] auto[1] auto[0] auto[1] 200640 1 T8 442 T7 761 T5 1877
auto[1] auto[0] auto[1] auto[1] auto[0] 214179 1 T1 440 T7 250 T5 475
auto[1] auto[0] auto[1] auto[1] auto[1] 222287 1 T1 296 T8 271 T7 515
auto[1] auto[1] auto[0] auto[0] auto[0] 498433 1 T1 424 T2 645 T4 4401
auto[1] auto[1] auto[0] auto[0] auto[1] 555648 1 T1 359 T2 348 T4 3716
auto[1] auto[1] auto[0] auto[1] auto[0] 538216 1 T4 3543 T8 264 T7 964
auto[1] auto[1] auto[0] auto[1] auto[1] 557201 1 T1 1233 T2 272 T4 6379
auto[1] auto[1] auto[1] auto[0] auto[0] 548989 1 T1 1447 T2 293 T4 253
auto[1] auto[1] auto[1] auto[0] auto[1] 507750 1 T1 155 T4 2901 T7 487
auto[1] auto[1] auto[1] auto[1] auto[0] 528155 1 T1 922 T2 236 T4 4388
auto[1] auto[1] auto[1] auto[1] auto[1] 529242 1 T1 1732 T4 2 T8 1


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 229951 1 T1 457 T8 356 T5 568
auto[0] auto[0] auto[0] auto[0] auto[1] 239977 1 T1 884 T2 514 T8 283
auto[0] auto[0] auto[0] auto[1] auto[0] 261710 1 T1 290 T8 2 T7 2
auto[0] auto[0] auto[0] auto[1] auto[1] 277641 1 T1 461 T7 657 T5 595
auto[0] auto[0] auto[1] auto[0] auto[0] 1912799 1 T1 628 T8 238 T7 715
auto[0] auto[0] auto[1] auto[0] auto[1] 240623 1 T8 442 T7 912 T5 1909
auto[0] auto[0] auto[1] auto[1] auto[0] 257098 1 T1 608 T7 319 T5 476
auto[0] auto[0] auto[1] auto[1] auto[1] 257119 1 T1 434 T8 271 T7 662
auto[0] auto[1] auto[0] auto[0] auto[0] 553205 1 T1 544 T2 645 T4 4401
auto[0] auto[1] auto[0] auto[0] auto[1] 605027 1 T1 359 T2 348 T4 4446
auto[0] auto[1] auto[0] auto[1] auto[0] 590410 1 T4 3588 T8 264 T7 1044
auto[0] auto[1] auto[0] auto[1] auto[1] 608285 1 T1 1233 T2 272 T4 7170
auto[0] auto[1] auto[1] auto[0] auto[0] 609612 1 T1 1523 T2 293 T4 253
auto[0] auto[1] auto[1] auto[0] auto[1] 553639 1 T1 256 T4 2901 T7 578
auto[0] auto[1] auto[1] auto[1] auto[0] 592144 1 T1 922 T2 247 T4 4388
auto[0] auto[1] auto[1] auto[1] auto[1] 568509 1 T1 1910 T4 2 T8 1
auto[1] auto[0] auto[0] auto[0] auto[0] 553 1 T6 2 T9 8 T125 5
auto[1] auto[0] auto[0] auto[0] auto[1] 890 1 T81 70 T17 2 T20 349
auto[1] auto[0] auto[0] auto[1] auto[0] 1271 1 T6 1 T9 1 T81 526
auto[1] auto[0] auto[0] auto[1] auto[1] 1665 1 T6 18 T9 77 T81 90
auto[1] auto[0] auto[1] auto[0] auto[0] 1538 1 T9 19 T81 5 T125 101
auto[1] auto[0] auto[1] auto[0] auto[1] 653 1 T9 21 T81 46 T20 44
auto[1] auto[0] auto[1] auto[1] auto[0] 1908 1 T6 476 T9 35 T81 2
auto[1] auto[0] auto[1] auto[1] auto[1] 275 1 T9 1 T17 2 T126 17
auto[1] auto[1] auto[0] auto[0] auto[0] 631 1 T6 50 T81 28 T47 2
auto[1] auto[1] auto[0] auto[0] auto[1] 357 1 T6 21 T17 5 T124 4
auto[1] auto[1] auto[0] auto[1] auto[0] 517 1 T6 22 T9 97 T81 46
auto[1] auto[1] auto[0] auto[1] auto[1] 758 1 T6 34 T17 178 T127 53
auto[1] auto[1] auto[1] auto[0] auto[0] 602 1 T9 31 T81 1 T128 386
auto[1] auto[1] auto[1] auto[0] auto[1] 2492 1 T6 1 T9 2 T125 6
auto[1] auto[1] auto[1] auto[1] auto[0] 1813 1 T81 100 T126 4 T124 30
auto[1] auto[1] auto[1] auto[1] auto[1] 57 1 T9 1 T129 2 T20 9


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 193562 1 T1 356 T8 348 T5 552
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 198728 1 T1 790 T2 499 T8 283
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 219946 1 T1 290 T8 2 T7 2
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 222976 1 T1 407 T7 483 T5 578
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1767013 1 T1 535 T8 238 T7 601
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 200640 1 T8 442 T7 761 T5 1877
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 214179 1 T1 440 T7 250 T5 475
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 222287 1 T1 296 T8 271 T7 515
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 498433 1 T1 424 T2 645 T4 4401
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 555648 1 T1 359 T2 348 T4 3716
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 538216 1 T4 3543 T8 264 T7 964
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 557201 1 T1 1233 T2 272 T4 6379
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 548989 1 T1 1447 T2 293 T4 253
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 507750 1 T1 155 T4 2901 T7 487
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 528155 1 T1 922 T2 236 T4 4388
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 529242 1 T1 1732 T4 2 T8 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4173 1 T1 18 T8 5 T5 9
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4188 1 T1 13 T2 8 T7 14
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4358 1 T5 10 T6 27 T111 69
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4846 1 T1 8 T7 36 T5 12
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 42977 1 T1 10 T7 17 T5 31
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3974 1 T7 30 T5 21 T19 20
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4320 1 T1 32 T7 11 T5 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4228 1 T1 29 T7 24 T6 1
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 7687 1 T1 15 T5 10 T6 78
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7527 1 T4 84 T5 18 T6 107
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 7547 1 T4 4 T7 6 T5 82
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6162 1 T4 128 T7 43 T9 84
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 9188 1 T1 13 T5 36 T19 53
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6739 1 T1 17 T7 11 T5 4
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6803 1 T2 8 T5 1 T19 23
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6468 1 T1 23 T5 2 T6 74
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3608 1 T1 14 T8 1 T5 2
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3520 1 T1 14 T2 5 T7 10
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3470 1 T5 3 T6 13 T25 1
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3821 1 T1 8 T7 32 T5 3
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 25705 1 T1 13 T7 20 T5 23
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3434 1 T7 29 T5 7 T19 15
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3587 1 T1 27 T7 15 T19 31
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3262 1 T1 26 T7 24 T120 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6254 1 T1 22 T5 20 T6 83
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 6464 1 T4 111 T5 7 T6 102
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 6154 1 T4 11 T7 12 T5 15
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5287 1 T4 120 T7 26 T6 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7421 1 T1 13 T5 10 T19 54
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5668 1 T1 14 T7 17 T5 4
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6183 1 T2 2 T19 23 T130 186
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5273 1 T1 21 T6 80 T122 103
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2857 1 T1 14 T8 2 T5 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2826 1 T1 16 T2 1 T7 7
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2647 1 T5 1 T6 26 T111 61
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 3058 1 T1 8 T7 29 T6 30
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 17029 1 T1 13 T7 17 T5 4
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2750 1 T7 23 T5 1 T19 17
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2625 1 T1 32 T7 9 T19 27
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2472 1 T1 26 T7 24 T6 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5274 1 T1 18 T5 6 T6 89
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 5540 1 T4 112 T6 108 T48 63
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 5092 1 T4 8 T7 12 T5 9
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4473 1 T4 113 T7 36 T6 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6314 1 T1 7 T5 4 T19 34
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4801 1 T1 15 T7 14 T5 5
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5361 1 T19 23 T130 166 T122 90
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4341 1 T1 35 T6 79 T122 113
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2808 1 T1 13 T5 1 T6 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 3121 1 T1 12 T7 10 T26 3
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2742 1 T6 42 T23 1 T111 42
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 3014 1 T1 4 T7 26 T5 2
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 12437 1 T1 15 T7 18 T5 4
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2742 1 T7 25 T5 1 T19 14
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2739 1 T1 26 T7 13 T19 30
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2391 1 T1 30 T7 14 T110 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 5061 1 T1 22 T5 8 T6 75
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 5220 1 T4 114 T6 104 T48 64
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 5259 1 T4 11 T7 13 T5 2
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4323 1 T4 119 T7 29 T6 3
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5913 1 T1 8 T5 1 T19 31
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4616 1 T1 19 T7 12 T5 3
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5299 1 T19 20 T130 161 T122 90
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4090 1 T1 25 T5 1 T6 77
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1954 1 T1 12 T5 2 T6 18
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2255 1 T1 13 T2 1 T7 7
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2114 1 T6 25 T111 34 T9 136
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2403 1 T1 6 T7 21 T6 22
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 8675 1 T1 15 T7 14 T111 13
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2230 1 T7 30 T19 14 T9 94
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1965 1 T1 29 T7 4 T25 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1862 1 T1 16 T7 17 T6 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4334 1 T1 20 T5 2 T6 70
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4500 1 T4 109 T6 104 T48 48
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 4352 1 T4 3 T7 11 T5 4
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3817 1 T4 113 T7 32 T6 3
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4967 1 T1 12 T19 16 T9 64
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3751 1 T1 15 T7 10 T5 5
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4541 1 T2 1 T19 14 T130 167
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3435 1 T1 27 T6 59 T122 64
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1621 1 T1 14 T5 1 T6 3
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 2254 1 T1 11 T7 11 T131 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1883 1 T6 49 T25 1 T23 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 2103 1 T1 7 T7 15 T6 31
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6139 1 T1 7 T7 12 T5 4
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1974 1 T7 10 T19 10 T9 79
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1765 1 T1 9 T7 7 T19 33
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1564 1 T1 8 T7 13 T6 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3514 1 T1 12 T5 5 T6 59
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3524 1 T4 96 T6 81 T48 32
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3648 1 T4 3 T7 8 T5 1
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3049 1 T4 90 T7 21 T6 5
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 4032 1 T1 9 T19 6 T9 56
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3268 1 T1 13 T7 13 T5 4
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3853 1 T19 11 T130 139 T122 58
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2754 1 T1 11 T6 35 T122 38
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1092 1 T1 10 T6 18 T9 38
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1464 1 T1 9 T7 4 T9 36
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1348 1 T6 32 T111 8 T9 94
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1451 1 T1 6 T7 9 T6 23
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 3803 1 T1 10 T7 6 T5 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1303 1 T7 3 T19 6 T9 40
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1130 1 T1 6 T7 4 T19 21
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1114 1 T1 1 T7 18 T9 23
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2389 1 T1 6 T6 42 T130 6
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2389 1 T4 54 T6 53 T48 38
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2422 1 T4 3 T7 7 T5 3
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2063 1 T4 56 T7 13 T6 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2978 1 T1 8 T9 33 T68 51
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2178 1 T1 6 T7 8 T5 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 3032 1 T19 2 T130 104 T122 49
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1841 1 T1 16 T6 17 T122 26

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%