Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	20307685	1			T1	21090		T2	4639		T4	54689
all_pins[1]	20307685	1			T1	21090		T2	4639		T4	54689
all_pins[2]	20307685	1			T1	21090		T2	4639		T4	54689

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51759134	1			T1	53628		T2	11596		T4	134788
values[0x1]	9163921	1			T1	9642		T2	2321		T4	29279
transitions[0x0=>0x1]	9163742	1			T1	9642		T2	2321		T4	29279
transitions[0x1=>0x0]	9163761	1			T1	9642		T2	2321		T4	29279

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	20285031	1			T1	21069		T2	4635		T4	54675
all_pins[0]	values[0x1]	22654	1			T1	21		T2	4		T4	14
all_pins[0]	transitions[0x0=>0x1]	22572	1			T1	21		T2	4		T4	14
all_pins[0]	transitions[0x1=>0x0]	9140806	1			T1	9621		T2	2317		T4	29265
all_pins[1]	values[0x0]	20307287	1			T1	21090		T2	4639		T4	54689
all_pins[1]	values[0x1]	398	1			T6	2		T9	6		T24	1
all_pins[1]	transitions[0x0=>0x1]	347	1			T6	2		T9	6		T24	1
all_pins[1]	transitions[0x1=>0x0]	22603	1			T1	21		T2	4		T4	14
all_pins[2]	values[0x0]	11166816	1			T1	11469		T2	2322		T4	25424
all_pins[2]	values[0x1]	9140869	1			T1	9621		T2	2317		T4	29265
all_pins[2]	transitions[0x0=>0x1]	9140823	1			T1	9621		T2	2317		T4	29265
all_pins[2]	transitions[0x1=>0x0]	352	1			T6	2		T9	6		T24	1