Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1041 1 T9 14 T10 10 T44 7
all_values[1] 1041 1 T9 14 T10 10 T44 7
all_values[2] 1041 1 T9 14 T10 10 T44 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1576 1 T9 24 T10 17 T44 10
auto[1] 1547 1 T9 18 T10 13 T44 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1124 1 T9 12 T10 7 T44 4
auto[1] 1999 1 T9 30 T10 23 T44 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1795 1 T9 24 T10 13 T44 9
auto[1] 1328 1 T9 18 T10 17 T44 12


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 187 1 T9 4 T44 1 T70 1
all_values[0] auto[0] auto[0] auto[1] 95 1 T9 3 T44 1 T70 1
all_values[0] auto[0] auto[1] auto[0] 207 1 T10 1 T44 2 T70 7
all_values[0] auto[0] auto[1] auto[1] 116 1 T9 2 T10 1 T44 1
all_values[0] auto[1] auto[0] auto[1] 204 1 T9 3 T10 1 T44 2
all_values[0] auto[1] auto[1] auto[1] 232 1 T9 2 T10 7 T70 3
all_values[1] auto[0] auto[0] auto[0] 168 1 T9 2 T10 2 T44 1
all_values[1] auto[0] auto[0] auto[1] 137 1 T9 4 T10 1 T70 2
all_values[1] auto[0] auto[1] auto[0] 162 1 T9 2 T70 2 T81 1
all_values[1] auto[0] auto[1] auto[1] 130 1 T10 3 T44 1 T70 4
all_values[1] auto[1] auto[0] auto[1] 232 1 T9 2 T10 3 T44 4
all_values[1] auto[1] auto[1] auto[1] 212 1 T9 4 T10 1 T44 1
all_values[2] auto[0] auto[0] auto[0] 201 1 T9 2 T10 4 T70 2
all_values[2] auto[0] auto[0] auto[1] 105 1 T10 1 T70 3 T81 1
all_values[2] auto[0] auto[1] auto[0] 199 1 T9 2 T70 4 T71 4
all_values[2] auto[0] auto[1] auto[1] 88 1 T9 3 T44 2 T70 2
all_values[2] auto[1] auto[0] auto[1] 247 1 T9 4 T10 5 T44 1
all_values[2] auto[1] auto[1] auto[1] 201 1 T9 3 T44 4 T70 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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