Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	5087	1			T1	12		T2	2		T4	8
sha2_none	5017	1			T1	3		T2	1		T4	6
sha2_512	8353	1			T1	11		T2	1		T4	7
sha2_384	8246	1			T1	7		T4	9		T8	1
sha2_256	7072	1			T1	7		T2	3		T4	12

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20709

1

T1

18

T2

5

T4

20

auto[1]

13508

1

T1

22

T2

2

T4

22

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13188

1

T1

17

T2

5

T4

26

auto[1]

21029

1

T1

23

T2

2

T4

16

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17820

1

T1

21

T2

6

T4

42

disabled

16397

1

T1

19

T2

1

T8

16

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5518	1			T1	12		T2	1		T4	11
key_none	8318	1			T1	3		T2	3		T4	10
key_1024	4872	1			T1	6		T2	1		T4	7
key_512	4381	1			T1	3		T4	3		T8	1
key_384	3904	1			T1	4		T4	4		T8	1
key_256	3642	1			T1	6		T4	2		T8	8
key_128	3501	1			T1	6		T2	2		T4	4

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20801

1

T1

20

T2

4

T4

23

auto[1]

13416

1

T1

20

T2

3

T4

19

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33949

1

T1

40

T2

7

T4

42

disabled

268

1

T8

2

T26

1

T19

5

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1824

1

T1

2

T2

2

T4

7

enabled

auto[0]

auto[0]

auto[1]

1880

1

T1

1

T2

1

T4

5

enabled

auto[0]

auto[1]

auto[0]

1804

1

T4

7

T8

1

T7

3

enabled

auto[0]

auto[1]

auto[1]

1917

1

T1

4

T2

1

T4

7

enabled

auto[1]

auto[0]

auto[0]

4557

1

T1

4

T2

1

T4

3

enabled

auto[1]

auto[0]

auto[1]

1928

1

T1

2

T4

5

T8

1

enabled

auto[1]

auto[1]

auto[0]

2013

1

T1

2

T2

1

T4

6

enabled

auto[1]

auto[1]

auto[1]

1897

1

T1

6

T4

2

T7

1

disabled

auto[0]

auto[0]

auto[0]

1369

1

T1

2

T8

4

T5

7

disabled

auto[0]

auto[0]

auto[1]

1415

1

T1

3

T2

1

T8

2

disabled

auto[0]

auto[1]

auto[0]

1508

1

T1

3

T7

2

T5

7

disabled

auto[0]

auto[1]

auto[1]

1471

1

T1

2

T8

1

T7

2

disabled

auto[1]

auto[0]

auto[0]

6270

1

T1

4

T8

2

T7

3

disabled

auto[1]

auto[0]

auto[1]

1466

1

T8

3

T7

2

T5

8

disabled

auto[1]

auto[1]

auto[0]

1456

1

T1

3

T8

2

T7

1

disabled

auto[1]

auto[1]

auto[1]

1442

1

T1

2

T8

2

T7

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17732

1

T1

21

T2

6

T4

42

enabled

disabled

88

1

T8

1

T19

2

T42

1

disabled

disabled

180

1

T8

1

T26

1

T19

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

16217

1

T1

19

T2

1

T8

15

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1337	1			T1	3		T2	1		T8	6
key_invalid	sha2_none	995	1			T1	1		T4	1		T7	1
key_invalid	sha2_512	1023	1			T1	2		T4	3		T8	1
key_invalid	sha2_384	1036	1			T1	1		T4	2		T7	1
key_invalid	sha2_256	1017	1			T1	5		T4	5		T7	1
key_none	sha2_invalid	630	1			T2	1		T4	1		T8	1
key_none	sha2_none	657	1			T2	1		T4	1		T8	1
key_none	sha2_512	2631	1			T1	2		T4	1		T7	1
key_none	sha2_384	2717	1			T1	1		T4	5		T7	1
key_none	sha2_256	1631	1			T2	1		T4	2		T8	1
key_1024	sha2_invalid	652	1			T1	2		T4	4		T8	1
key_1024	sha2_none	627	1			T4	1		T8	1		T7	1
key_1024	sha2_512	1870	1			T1	3		T4	1		T7	1
key_1024	sha2_384	990	1			T1	1		T5	3		T6	1
key_512	sha2_invalid	618	1			T1	3		T7	2		T5	2
key_512	sha2_none	678	1			T4	1		T7	1		T5	5
key_512	sha2_512	732	1			T4	2		T8	1		T5	3
key_512	sha2_384	1343	1			T7	1		T5	3		T25	2
key_512	sha2_256	951	1			T5	2		T6	1		T16	1
key_384	sha2_invalid	595	1			T4	2		T7	1		T5	2
key_384	sha2_none	660	1			T1	1		T4	1		T7	2
key_384	sha2_512	701	1			T1	2		T8	1		T7	1
key_384	sha2_384	681	1			T7	2		T5	2		T6	2
key_384	sha2_256	1207	1			T1	1		T4	1		T5	1
key_256	sha2_invalid	587	1			T1	3		T8	2		T7	1
key_256	sha2_none	718	1			T1	1		T8	1		T7	1
key_256	sha2_512	704	1			T8	3		T7	1		T5	5
key_256	sha2_384	726	1			T1	2		T4	1		T5	8
key_256	sha2_256	861	1			T4	1		T8	1		T5	3
key_128	sha2_invalid	652	1			T1	1		T4	1		T7	1
key_128	sha2_none	666	1			T4	1		T8	1		T5	2
key_128	sha2_512	677	1			T1	2		T2	1		T7	1
key_128	sha2_384	736	1			T1	2		T8	1		T5	3
key_128	sha2_256	722	1			T1	1		T2	1		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

669

1

T2

1

T4

1

T5

10

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1337	1			T1	3		T2	1		T8	6
key_invalid	sha2_none	995	1			T1	1		T4	1		T7	1
key_invalid	sha2_512	1023	1			T1	2		T4	3		T8	1
key_invalid	sha2_384	1036	1			T1	1		T4	2		T7	1
key_invalid	sha2_256	1017	1			T1	5		T4	5		T7	1
key_none	sha2_invalid	630	1			T2	1		T4	1		T8	1
key_none	sha2_none	657	1			T2	1		T4	1		T8	1
key_none	sha2_512	2631	1			T1	2		T4	1		T7	1
key_none	sha2_384	2717	1			T1	1		T4	5		T7	1
key_none	sha2_256	1631	1			T2	1		T4	2		T8	1
key_1024	sha2_invalid	652	1			T1	2		T4	4		T8	1
key_1024	sha2_none	627	1			T4	1		T8	1		T7	1
key_1024	sha2_512	1870	1			T1	3		T4	1		T7	1
key_1024	sha2_384	990	1			T1	1		T5	3		T6	1
key_1024	sha2_256	669	1			T2	1		T4	1		T5	10
key_512	sha2_invalid	618	1			T1	3		T7	2		T5	2
key_512	sha2_none	678	1			T4	1		T7	1		T5	5
key_512	sha2_512	732	1			T4	2		T8	1		T5	3
key_512	sha2_384	1343	1			T7	1		T5	3		T25	2
key_512	sha2_256	951	1			T5	2		T6	1		T16	1
key_384	sha2_invalid	595	1			T4	2		T7	1		T5	2
key_384	sha2_none	660	1			T1	1		T4	1		T7	2
key_384	sha2_512	701	1			T1	2		T8	1		T7	1
key_384	sha2_384	681	1			T7	2		T5	2		T6	2
key_384	sha2_256	1207	1			T1	1		T4	1		T5	1
key_256	sha2_invalid	587	1			T1	3		T8	2		T7	1
key_256	sha2_none	718	1			T1	1		T8	1		T7	1
key_256	sha2_512	704	1			T8	3		T7	1		T5	5
key_256	sha2_384	726	1			T1	2		T4	1		T5	8
key_256	sha2_256	861	1			T4	1		T8	1		T5	3
key_128	sha2_invalid	652	1			T1	1		T4	1		T7	1
key_128	sha2_none	666	1			T4	1		T8	1		T5	2
key_128	sha2_512	677	1			T1	2		T2	1		T7	1
key_128	sha2_384	736	1			T1	2		T8	1		T5	3
key_128	sha2_256	722	1			T1	1		T2	1		T4	2