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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.45 95.40 97.17 100.00 100.00 98.27 98.48 99.85


Total test records in report: 660
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T104 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3503933504 Aug 10 06:03:27 PM PDT 24 Aug 10 06:03:30 PM PDT 24 1214211368 ps
T62 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.141672469 Aug 10 06:03:46 PM PDT 24 Aug 10 06:03:49 PM PDT 24 308250727 ps
T530 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.654264771 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:55 PM PDT 24 83963863 ps
T531 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.673946219 Aug 10 06:03:44 PM PDT 24 Aug 10 06:03:46 PM PDT 24 97966238 ps
T532 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1425177992 Aug 10 06:04:18 PM PDT 24 Aug 10 06:04:19 PM PDT 24 117965856 ps
T90 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3933475400 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:56 PM PDT 24 28118782 ps
T533 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1886835413 Aug 10 06:04:12 PM PDT 24 Aug 10 06:04:16 PM PDT 24 345346369 ps
T105 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.511609446 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:56 PM PDT 24 1265937429 ps
T534 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2706777989 Aug 10 06:03:45 PM PDT 24 Aug 10 06:03:46 PM PDT 24 32984758 ps
T91 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2128831669 Aug 10 06:03:19 PM PDT 24 Aug 10 06:03:25 PM PDT 24 108933179 ps
T535 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3451270725 Aug 10 06:04:02 PM PDT 24 Aug 10 06:04:03 PM PDT 24 29655311 ps
T536 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1008588337 Aug 10 06:03:53 PM PDT 24 Aug 10 06:03:54 PM PDT 24 115409478 ps
T537 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4266342585 Aug 10 06:03:18 PM PDT 24 Aug 10 06:03:20 PM PDT 24 26879142 ps
T538 /workspace/coverage/cover_reg_top/8.hmac_intr_test.271532435 Aug 10 06:03:46 PM PDT 24 Aug 10 06:03:47 PM PDT 24 20577972 ps
T539 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2795098977 Aug 10 06:04:18 PM PDT 24 Aug 10 06:04:19 PM PDT 24 14493188 ps
T540 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2001601243 Aug 10 06:03:58 PM PDT 24 Aug 10 06:04:00 PM PDT 24 374047717 ps
T106 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.994634014 Aug 10 06:03:45 PM PDT 24 Aug 10 06:03:46 PM PDT 24 12766739 ps
T541 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.4117619330 Aug 10 06:03:59 PM PDT 24 Aug 10 06:04:01 PM PDT 24 98422764 ps
T542 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3371608554 Aug 10 06:04:17 PM PDT 24 Aug 10 06:04:18 PM PDT 24 17975616 ps
T543 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1302284466 Aug 10 06:04:17 PM PDT 24 Aug 10 06:04:18 PM PDT 24 23651441 ps
T544 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1625455592 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:57 PM PDT 24 41881539 ps
T545 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4251716056 Aug 10 06:04:12 PM PDT 24 Aug 10 06:04:16 PM PDT 24 844660316 ps
T546 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2963491550 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:12 PM PDT 24 44564513 ps
T547 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1960343488 Aug 10 06:04:19 PM PDT 24 Aug 10 06:04:20 PM PDT 24 28689096 ps
T548 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3311996769 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:17 PM PDT 24 1083953347 ps
T549 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2834769105 Aug 10 06:04:02 PM PDT 24 Aug 10 06:04:03 PM PDT 24 76847599 ps
T63 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2454084282 Aug 10 06:03:12 PM PDT 24 Aug 10 06:03:16 PM PDT 24 122760275 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.842941725 Aug 10 06:03:27 PM PDT 24 Aug 10 06:03:29 PM PDT 24 45035175 ps
T107 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1060155837 Aug 10 06:04:02 PM PDT 24 Aug 10 06:04:04 PM PDT 24 620446061 ps
T550 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3585890441 Aug 10 06:04:08 PM PDT 24 Aug 10 06:04:09 PM PDT 24 53443327 ps
T551 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.470752850 Aug 10 06:03:48 PM PDT 24 Aug 10 06:03:50 PM PDT 24 162488802 ps
T552 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1101368221 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:12 PM PDT 24 42862173 ps
T553 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2074669506 Aug 10 06:04:09 PM PDT 24 Aug 10 06:04:10 PM PDT 24 12465996 ps
T554 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2054849895 Aug 10 06:03:46 PM PDT 24 Aug 10 06:03:49 PM PDT 24 86932791 ps
T555 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3991669849 Aug 10 06:04:18 PM PDT 24 Aug 10 06:04:19 PM PDT 24 43824307 ps
T93 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1347276191 Aug 10 06:03:46 PM PDT 24 Aug 10 06:03:47 PM PDT 24 72942276 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1626201692 Aug 10 06:03:26 PM PDT 24 Aug 10 06:03:39 PM PDT 24 328173877 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3681594802 Aug 10 06:03:48 PM PDT 24 Aug 10 06:03:51 PM PDT 24 443142420 ps
T64 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3005540395 Aug 10 06:03:48 PM PDT 24 Aug 10 06:03:50 PM PDT 24 125203128 ps
T108 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.407601450 Aug 10 06:03:38 PM PDT 24 Aug 10 06:03:39 PM PDT 24 294553766 ps
T109 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3565589220 Aug 10 06:03:45 PM PDT 24 Aug 10 06:03:46 PM PDT 24 167995118 ps
T94 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.302601697 Aug 10 06:04:01 PM PDT 24 Aug 10 06:04:02 PM PDT 24 180534827 ps
T557 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.253079033 Aug 10 06:03:20 PM PDT 24 Aug 10 06:03:21 PM PDT 24 264950447 ps
T558 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.854070846 Aug 10 06:03:57 PM PDT 24 Aug 10 06:03:59 PM PDT 24 26075815 ps
T559 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2136957163 Aug 10 06:03:48 PM PDT 24 Aug 10 06:03:50 PM PDT 24 393678301 ps
T560 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3162565115 Aug 10 06:03:20 PM PDT 24 Aug 10 06:03:21 PM PDT 24 133893120 ps
T101 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1788960457 Aug 10 06:03:19 PM PDT 24 Aug 10 06:03:36 PM PDT 24 1648912895 ps
T561 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3042436535 Aug 10 06:03:36 PM PDT 24 Aug 10 06:03:39 PM PDT 24 122965753 ps
T113 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4184244127 Aug 10 06:04:01 PM PDT 24 Aug 10 06:04:06 PM PDT 24 1559584469 ps
T562 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3110817233 Aug 10 06:04:17 PM PDT 24 Aug 10 06:04:17 PM PDT 24 11949310 ps
T563 /workspace/coverage/cover_reg_top/38.hmac_intr_test.4167620184 Aug 10 06:04:20 PM PDT 24 Aug 10 06:04:20 PM PDT 24 15785594 ps
T564 /workspace/coverage/cover_reg_top/24.hmac_intr_test.4275042163 Aug 10 06:04:10 PM PDT 24 Aug 10 06:04:11 PM PDT 24 39161464 ps
T565 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3194382650 Aug 10 06:03:45 PM PDT 24 Aug 10 06:03:48 PM PDT 24 317804205 ps
T566 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.798787073 Aug 10 06:03:17 PM PDT 24 Aug 10 06:03:18 PM PDT 24 26671193 ps
T567 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1147331367 Aug 10 06:03:36 PM PDT 24 Aug 10 06:03:37 PM PDT 24 19402556 ps
T568 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1916526795 Aug 10 06:04:01 PM PDT 24 Aug 10 06:04:02 PM PDT 24 38047133 ps
T569 /workspace/coverage/cover_reg_top/22.hmac_intr_test.124505631 Aug 10 06:04:04 PM PDT 24 Aug 10 06:04:05 PM PDT 24 21092967 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2173291991 Aug 10 06:03:10 PM PDT 24 Aug 10 06:03:14 PM PDT 24 798519843 ps
T570 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.394464387 Aug 10 06:03:44 PM PDT 24 Aug 10 06:03:46 PM PDT 24 99198284 ps
T571 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2135907503 Aug 10 06:03:18 PM PDT 24 Aug 10 06:03:18 PM PDT 24 11606928 ps
T572 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3548680398 Aug 10 06:04:02 PM PDT 24 Aug 10 06:04:05 PM PDT 24 653091666 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1417243476 Aug 10 06:03:20 PM PDT 24 Aug 10 06:03:26 PM PDT 24 1079095773 ps
T96 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1456239410 Aug 10 06:03:19 PM PDT 24 Aug 10 06:03:20 PM PDT 24 21947437 ps
T573 /workspace/coverage/cover_reg_top/15.hmac_intr_test.466621560 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:55 PM PDT 24 11199432 ps
T574 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1849041993 Aug 10 06:04:00 PM PDT 24 Aug 10 06:04:02 PM PDT 24 222131384 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2039822530 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:12 PM PDT 24 20413839 ps
T98 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.500111961 Aug 10 06:03:48 PM PDT 24 Aug 10 06:03:49 PM PDT 24 19845846 ps
T575 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1186927997 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:57 PM PDT 24 79599819 ps
T99 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2381288973 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:55 PM PDT 24 55220453 ps
T576 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.282597850 Aug 10 06:04:11 PM PDT 24 Aug 10 06:04:12 PM PDT 24 14316915 ps
T577 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3940646447 Aug 10 06:03:53 PM PDT 24 Aug 10 06:03:55 PM PDT 24 245634245 ps
T578 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2033089264 Aug 10 06:04:10 PM PDT 24 Aug 10 06:04:10 PM PDT 24 43486904 ps
T579 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1780322957 Aug 10 06:03:19 PM PDT 24 Aug 10 06:03:20 PM PDT 24 59050860 ps
T580 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.51865437 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:56 PM PDT 24 27612278 ps
T581 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1054780456 Aug 10 06:03:26 PM PDT 24 Aug 10 06:03:27 PM PDT 24 46128304 ps
T582 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.212415634 Aug 10 06:03:27 PM PDT 24 Aug 10 06:03:29 PM PDT 24 190635052 ps
T115 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3906411392 Aug 10 06:03:35 PM PDT 24 Aug 10 06:03:39 PM PDT 24 242846560 ps
T583 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3256087082 Aug 10 06:03:56 PM PDT 24 Aug 10 06:03:57 PM PDT 24 47821287 ps
T584 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3064429737 Aug 10 06:03:09 PM PDT 24 Aug 10 06:03:10 PM PDT 24 16839604 ps
T585 /workspace/coverage/cover_reg_top/30.hmac_intr_test.189388784 Aug 10 06:04:11 PM PDT 24 Aug 10 06:04:12 PM PDT 24 11429657 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4013695115 Aug 10 06:03:57 PM PDT 24 Aug 10 06:03:59 PM PDT 24 46086233 ps
T587 /workspace/coverage/cover_reg_top/9.hmac_intr_test.960084944 Aug 10 06:03:47 PM PDT 24 Aug 10 06:03:48 PM PDT 24 33743831 ps
T588 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1628825615 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:56 PM PDT 24 103657674 ps
T589 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2386077067 Aug 10 06:03:28 PM PDT 24 Aug 10 06:03:29 PM PDT 24 11808578 ps
T590 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2378154531 Aug 10 06:03:57 PM PDT 24 Aug 10 06:03:59 PM PDT 24 42556942 ps
T591 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1896591955 Aug 10 06:04:17 PM PDT 24 Aug 10 06:04:17 PM PDT 24 13666377 ps
T592 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.833594355 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:13 PM PDT 24 79532530 ps
T593 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2819904419 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:55 PM PDT 24 13933434 ps
T594 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3271345301 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:58 PM PDT 24 479763684 ps
T595 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3159242122 Aug 10 06:04:12 PM PDT 24 Aug 10 06:04:12 PM PDT 24 60000407 ps
T596 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2856443248 Aug 10 06:04:18 PM PDT 24 Aug 10 06:04:19 PM PDT 24 15685410 ps
T597 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2615385494 Aug 10 06:04:17 PM PDT 24 Aug 10 06:04:18 PM PDT 24 17556002 ps
T598 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1263154721 Aug 10 06:03:58 PM PDT 24 Aug 10 06:03:58 PM PDT 24 20665533 ps
T599 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1152434976 Aug 10 06:03:38 PM PDT 24 Aug 10 06:03:41 PM PDT 24 161858479 ps
T600 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.534268956 Aug 10 06:04:12 PM PDT 24 Aug 10 06:04:14 PM PDT 24 228862775 ps
T601 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3840183048 Aug 10 06:03:53 PM PDT 24 Aug 10 06:03:54 PM PDT 24 21307825 ps
T602 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2261560581 Aug 10 06:03:20 PM PDT 24 Aug 10 06:03:22 PM PDT 24 215803974 ps
T603 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1269077769 Aug 10 06:03:37 PM PDT 24 Aug 10 06:03:40 PM PDT 24 468327924 ps
T604 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1840296236 Aug 10 06:03:12 PM PDT 24 Aug 10 06:03:13 PM PDT 24 23232512 ps
T605 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3879218829 Aug 10 06:03:36 PM PDT 24 Aug 10 06:03:37 PM PDT 24 51288058 ps
T116 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3369809463 Aug 10 06:03:52 PM PDT 24 Aug 10 06:03:54 PM PDT 24 106336789 ps
T606 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3986121079 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:56 PM PDT 24 403716505 ps
T607 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4256532849 Aug 10 06:03:58 PM PDT 24 Aug 10 06:03:59 PM PDT 24 212652209 ps
T608 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4108353454 Aug 10 06:03:55 PM PDT 24 Aug 10 06:20:54 PM PDT 24 424259726385 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.155079057 Aug 10 06:03:29 PM PDT 24 Aug 10 06:03:39 PM PDT 24 597593731 ps
T610 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.102491943 Aug 10 06:03:29 PM PDT 24 Aug 10 06:03:31 PM PDT 24 156039298 ps
T611 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1525365898 Aug 10 06:03:36 PM PDT 24 Aug 10 06:03:37 PM PDT 24 42088307 ps
T612 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2755068160 Aug 10 06:03:20 PM PDT 24 Aug 10 06:03:22 PM PDT 24 29905752 ps
T613 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1918019846 Aug 10 06:04:17 PM PDT 24 Aug 10 06:04:18 PM PDT 24 12223858 ps
T614 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1020106843 Aug 10 06:03:45 PM PDT 24 Aug 10 06:03:46 PM PDT 24 77099023 ps
T114 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3223825475 Aug 10 06:04:03 PM PDT 24 Aug 10 06:04:08 PM PDT 24 275229210 ps
T615 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.947756618 Aug 10 06:03:23 PM PDT 24 Aug 10 06:03:24 PM PDT 24 67415812 ps
T616 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.276656241 Aug 10 06:03:29 PM PDT 24 Aug 10 06:03:33 PM PDT 24 2715974452 ps
T617 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1819713478 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:12 PM PDT 24 91212632 ps
T618 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2878185624 Aug 10 06:04:11 PM PDT 24 Aug 10 06:04:11 PM PDT 24 11207058 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4245937457 Aug 10 06:03:28 PM PDT 24 Aug 10 06:03:36 PM PDT 24 924853750 ps
T118 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1123257246 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:57 PM PDT 24 372414241 ps
T620 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.356982248 Aug 10 06:03:53 PM PDT 24 Aug 10 06:03:56 PM PDT 24 44690205 ps
T621 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1531874629 Aug 10 06:03:46 PM PDT 24 Aug 10 06:12:26 PM PDT 24 511249480349 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.288824876 Aug 10 06:03:18 PM PDT 24 Aug 10 06:03:21 PM PDT 24 595333510 ps
T623 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2875010694 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:57 PM PDT 24 332358206 ps
T624 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.912435326 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:59 PM PDT 24 435472076 ps
T625 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3650352145 Aug 10 06:03:57 PM PDT 24 Aug 10 06:03:58 PM PDT 24 63794711 ps
T626 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3236966776 Aug 10 06:03:55 PM PDT 24 Aug 10 06:03:58 PM PDT 24 157186104 ps
T627 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3309524727 Aug 10 06:04:20 PM PDT 24 Aug 10 06:04:21 PM PDT 24 13150879 ps
T628 /workspace/coverage/cover_reg_top/26.hmac_intr_test.43757456 Aug 10 06:04:19 PM PDT 24 Aug 10 06:04:20 PM PDT 24 69597725 ps
T629 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1881429495 Aug 10 06:03:53 PM PDT 24 Aug 10 06:03:57 PM PDT 24 133578744 ps
T630 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1628635410 Aug 10 06:03:53 PM PDT 24 Aug 10 06:03:53 PM PDT 24 27606096 ps
T631 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3789017834 Aug 10 06:03:21 PM PDT 24 Aug 10 06:03:22 PM PDT 24 55182203 ps
T632 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2278870476 Aug 10 06:03:12 PM PDT 24 Aug 10 06:03:13 PM PDT 24 29620986 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1108115285 Aug 10 06:03:12 PM PDT 24 Aug 10 06:03:14 PM PDT 24 411287435 ps
T634 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1450861091 Aug 10 06:03:38 PM PDT 24 Aug 10 06:03:38 PM PDT 24 32998597 ps
T635 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2212199397 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:56 PM PDT 24 78535000 ps
T636 /workspace/coverage/cover_reg_top/36.hmac_intr_test.104201570 Aug 10 06:04:19 PM PDT 24 Aug 10 06:04:20 PM PDT 24 16885337 ps
T637 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.221556089 Aug 10 06:03:28 PM PDT 24 Aug 10 06:03:29 PM PDT 24 57392500 ps
T638 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3893252178 Aug 10 06:04:19 PM PDT 24 Aug 10 06:04:19 PM PDT 24 46130689 ps
T639 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1791893582 Aug 10 06:03:44 PM PDT 24 Aug 10 06:03:48 PM PDT 24 272644488 ps
T640 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3844054233 Aug 10 06:04:11 PM PDT 24 Aug 10 06:04:14 PM PDT 24 563694468 ps
T641 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2900997599 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:54 PM PDT 24 14741180 ps
T642 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3347910030 Aug 10 06:04:09 PM PDT 24 Aug 10 06:04:10 PM PDT 24 40214001 ps
T643 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1377257486 Aug 10 06:04:14 PM PDT 24 Aug 10 06:04:15 PM PDT 24 14228879 ps
T644 /workspace/coverage/cover_reg_top/16.hmac_intr_test.985084575 Aug 10 06:04:01 PM PDT 24 Aug 10 06:04:02 PM PDT 24 15356266 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1547564647 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:56 PM PDT 24 39296466 ps
T119 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1681484293 Aug 10 06:03:18 PM PDT 24 Aug 10 06:03:23 PM PDT 24 857622700 ps
T117 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1545830582 Aug 10 06:03:56 PM PDT 24 Aug 10 06:04:00 PM PDT 24 314175822 ps
T646 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3829858857 Aug 10 06:04:03 PM PDT 24 Aug 10 06:04:03 PM PDT 24 273845242 ps
T647 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.50950142 Aug 10 06:03:18 PM PDT 24 Aug 10 06:03:24 PM PDT 24 476951511 ps
T648 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3517081587 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:12 PM PDT 24 30146042 ps
T649 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2884175302 Aug 10 06:03:35 PM PDT 24 Aug 10 06:03:36 PM PDT 24 50788742 ps
T650 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3591988229 Aug 10 06:04:00 PM PDT 24 Aug 10 06:04:02 PM PDT 24 709522854 ps
T651 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.744571327 Aug 10 06:04:13 PM PDT 24 Aug 10 06:04:15 PM PDT 24 88101530 ps
T652 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2818780190 Aug 10 06:04:02 PM PDT 24 Aug 10 06:04:02 PM PDT 24 17803237 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.103263701 Aug 10 06:03:20 PM PDT 24 Aug 10 06:03:25 PM PDT 24 106706835 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3731432833 Aug 10 06:04:02 PM PDT 24 Aug 10 06:10:21 PM PDT 24 35043188145 ps
T655 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4039975486 Aug 10 06:03:23 PM PDT 24 Aug 10 06:03:24 PM PDT 24 121932714 ps
T656 /workspace/coverage/cover_reg_top/25.hmac_intr_test.628681942 Aug 10 06:04:10 PM PDT 24 Aug 10 06:04:10 PM PDT 24 56193433 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3544208421 Aug 10 06:03:44 PM PDT 24 Aug 10 06:03:47 PM PDT 24 364988491 ps
T658 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2345310277 Aug 10 06:03:38 PM PDT 24 Aug 10 06:03:42 PM PDT 24 438789883 ps
T659 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2509245013 Aug 10 06:03:54 PM PDT 24 Aug 10 06:03:55 PM PDT 24 52484114 ps
T660 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2724335894 Aug 10 06:03:11 PM PDT 24 Aug 10 06:03:14 PM PDT 24 114337876 ps

Test location /workspace/coverage/default/34.hmac_stress_all.2485332224
Short name T5
Test name
Test status
Simulation time 21115764921 ps
CPU time 561.17 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:13:32 PM PDT 24
Peak memory 650844 kb
Host smart-0aba60eb-c5c4-41e2-a27d-0fdb8c08cd71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485332224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2485332224
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1349959294
Short name T9
Test name
Test status
Simulation time 56298117340 ps
CPU time 1982.29 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:36:38 PM PDT 24
Peak memory 731920 kb
Host smart-2303d777-4199-4277-837e-1209476f73e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349959294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1349959294
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3951588771
Short name T20
Test name
Test status
Simulation time 79754823052 ps
CPU time 3464.9 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 06:01:08 PM PDT 24
Peak memory 739404 kb
Host smart-dd9dea72-fd07-481a-a7b8-1ace90ea182b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951588771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3951588771
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4184244127
Short name T113
Test name
Test status
Simulation time 1559584469 ps
CPU time 4.48 seconds
Started Aug 10 06:04:01 PM PDT 24
Finished Aug 10 06:04:06 PM PDT 24
Peak memory 200116 kb
Host smart-55b97e9e-cb1e-4503-8055-8a89abe4ff4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184244127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4184244127
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1686545451
Short name T22
Test name
Test status
Simulation time 107494030841 ps
CPU time 6439.09 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 06:50:43 PM PDT 24
Peak memory 885092 kb
Host smart-ed5ed6e8-c512-4c24-972a-600533c698f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686545451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1686545451
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.819689097
Short name T50
Test name
Test status
Simulation time 57055437 ps
CPU time 0.91 seconds
Started Aug 10 05:03:09 PM PDT 24
Finished Aug 10 05:03:10 PM PDT 24
Peak memory 218384 kb
Host smart-d500885a-9cee-4d23-9fdb-c012836adfdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819689097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.819689097
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/42.hmac_stress_all.4100363424
Short name T70
Test name
Test status
Simulation time 172334669673 ps
CPU time 4158.38 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 06:14:05 PM PDT 24
Peak memory 773712 kb
Host smart-8d971310-f2fb-46db-85c2-facbdd65e136
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100363424 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.4100363424
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3933475400
Short name T90
Test name
Test status
Simulation time 28118782 ps
CPU time 0.8 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 199372 kb
Host smart-64c4255b-f42c-4748-a50c-e8044dc16261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933475400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3933475400
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.148567618
Short name T12
Test name
Test status
Simulation time 1433098565 ps
CPU time 81.28 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:05:11 PM PDT 24
Peak memory 199824 kb
Host smart-7454c234-ebd8-4f99-b654-cfb0c2b9649f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148567618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.148567618
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3802878765
Short name T6
Test name
Test status
Simulation time 14916602999 ps
CPU time 409.53 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:10:24 PM PDT 24
Peak memory 661996 kb
Host smart-30b0e644-bb40-4863-92f9-7b0293dc8f27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802878765 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3802878765
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1989997951
Short name T86
Test name
Test status
Simulation time 52411647 ps
CPU time 0.64 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 195952 kb
Host smart-3b33a59d-6ba2-4071-a5dc-dcda9d375c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989997951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1989997951
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1545830582
Short name T117
Test name
Test status
Simulation time 314175822 ps
CPU time 4.01 seconds
Started Aug 10 06:03:56 PM PDT 24
Finished Aug 10 06:04:00 PM PDT 24
Peak memory 200172 kb
Host smart-091551f4-f8b1-490b-a0fd-a925594c2d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545830582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1545830582
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3159012927
Short name T124
Test name
Test status
Simulation time 10545372531 ps
CPU time 1303.86 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:25:32 PM PDT 24
Peak memory 742332 kb
Host smart-ddf3c658-bafa-4e9a-814c-59d96760df94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159012927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3159012927
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2454084282
Short name T63
Test name
Test status
Simulation time 122760275 ps
CPU time 3.89 seconds
Started Aug 10 06:03:12 PM PDT 24
Finished Aug 10 06:03:16 PM PDT 24
Peak memory 200128 kb
Host smart-5148136e-9989-4ac6-b91a-ac5a829f385b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454084282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2454084282
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.4090198547
Short name T154
Test name
Test status
Simulation time 834782635155 ps
CPU time 2563.76 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:45:52 PM PDT 24
Peak memory 215300 kb
Host smart-cce07a69-f6cd-4de6-96ce-24a0a360274e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4090198547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.4090198547
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.366838671
Short name T11
Test name
Test status
Simulation time 159862784035 ps
CPU time 1450.32 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:27:45 PM PDT 24
Peak memory 446624 kb
Host smart-be2e51fe-c4ab-4603-b58b-aef25608872b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=366838671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.366838671
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2173291991
Short name T95
Test name
Test status
Simulation time 798519843 ps
CPU time 3.32 seconds
Started Aug 10 06:03:10 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 200204 kb
Host smart-81713fc1-751a-4c5b-b67d-1d5e1f1de85b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173291991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2173291991
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3311996769
Short name T548
Test name
Test status
Simulation time 1083953347 ps
CPU time 5.94 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:17 PM PDT 24
Peak memory 199232 kb
Host smart-e68ddc4d-7f1a-44e1-9bba-60117b67be1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311996769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3311996769
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3064429737
Short name T584
Test name
Test status
Simulation time 16839604 ps
CPU time 0.71 seconds
Started Aug 10 06:03:09 PM PDT 24
Finished Aug 10 06:03:10 PM PDT 24
Peak memory 198520 kb
Host smart-8527b6a2-6415-45a4-bc74-d690669a23f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064429737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3064429737
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2724335894
Short name T660
Test name
Test status
Simulation time 114337876 ps
CPU time 2.39 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 215840 kb
Host smart-cd15eea3-77f6-41e8-9c75-b785375ad0bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724335894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2724335894
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3517081587
Short name T648
Test name
Test status
Simulation time 30146042 ps
CPU time 0.66 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:12 PM PDT 24
Peak memory 197988 kb
Host smart-22127e85-2769-40f8-82e4-cca5eb58baa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517081587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3517081587
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2963491550
Short name T546
Test name
Test status
Simulation time 44564513 ps
CPU time 0.56 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:12 PM PDT 24
Peak memory 195120 kb
Host smart-c3990283-d6c2-4bfa-9027-2a59a7b99cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963491550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2963491550
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2278870476
Short name T632
Test name
Test status
Simulation time 29620986 ps
CPU time 1.12 seconds
Started Aug 10 06:03:12 PM PDT 24
Finished Aug 10 06:03:13 PM PDT 24
Peak memory 198616 kb
Host smart-9f44144c-741c-460d-bdfc-24ef3a1a2fea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278870476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2278870476
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.833594355
Short name T592
Test name
Test status
Simulation time 79532530 ps
CPU time 1.9 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:13 PM PDT 24
Peak memory 200176 kb
Host smart-957ed60b-0f88-4aa8-81cd-5045002dc9c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833594355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.833594355
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.103263701
Short name T653
Test name
Test status
Simulation time 106706835 ps
CPU time 5.11 seconds
Started Aug 10 06:03:20 PM PDT 24
Finished Aug 10 06:03:25 PM PDT 24
Peak memory 200088 kb
Host smart-375e0a93-8e32-45c4-afae-39f0f2f804a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103263701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.103263701
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1788960457
Short name T101
Test name
Test status
Simulation time 1648912895 ps
CPU time 16.19 seconds
Started Aug 10 06:03:19 PM PDT 24
Finished Aug 10 06:03:36 PM PDT 24
Peak memory 200032 kb
Host smart-31f8e78d-cc48-46cd-933e-277d2855b373
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788960457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1788960457
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2039822530
Short name T97
Test name
Test status
Simulation time 20413839 ps
CPU time 1 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:12 PM PDT 24
Peak memory 199952 kb
Host smart-22e086b8-1ac5-458d-bea8-dae4d912e25e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039822530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2039822530
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.253079033
Short name T557
Test name
Test status
Simulation time 264950447 ps
CPU time 1.25 seconds
Started Aug 10 06:03:20 PM PDT 24
Finished Aug 10 06:03:21 PM PDT 24
Peak memory 200108 kb
Host smart-84fbbdc3-fd8a-46bd-a508-194d701f3ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253079033 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.253079033
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1819713478
Short name T617
Test name
Test status
Simulation time 91212632 ps
CPU time 0.68 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:12 PM PDT 24
Peak memory 197924 kb
Host smart-99b5b00f-6663-4226-995f-0ec39be7eb7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819713478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1819713478
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1101368221
Short name T552
Test name
Test status
Simulation time 42862173 ps
CPU time 0.57 seconds
Started Aug 10 06:03:11 PM PDT 24
Finished Aug 10 06:03:12 PM PDT 24
Peak memory 195004 kb
Host smart-dfb50888-aa57-49d8-b8df-9143ad65adc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101368221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1101368221
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2261560581
Short name T602
Test name
Test status
Simulation time 215803974 ps
CPU time 2.25 seconds
Started Aug 10 06:03:20 PM PDT 24
Finished Aug 10 06:03:22 PM PDT 24
Peak memory 200052 kb
Host smart-7d4f59a9-a495-4fbc-9dda-4c1ab1c3b9b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261560581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2261560581
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1840296236
Short name T604
Test name
Test status
Simulation time 23232512 ps
CPU time 1.11 seconds
Started Aug 10 06:03:12 PM PDT 24
Finished Aug 10 06:03:13 PM PDT 24
Peak memory 200044 kb
Host smart-8763c9ea-f0ec-4b29-9ee4-8bf14c6edfe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840296236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1840296236
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1108115285
Short name T633
Test name
Test status
Simulation time 411287435 ps
CPU time 1.79 seconds
Started Aug 10 06:03:12 PM PDT 24
Finished Aug 10 06:03:14 PM PDT 24
Peak memory 200136 kb
Host smart-9373f47d-cb05-45c7-82f4-fdf0b90b4c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108115285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1108115285
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.854070846
Short name T558
Test name
Test status
Simulation time 26075815 ps
CPU time 1.6 seconds
Started Aug 10 06:03:57 PM PDT 24
Finished Aug 10 06:03:59 PM PDT 24
Peak memory 200140 kb
Host smart-8bcc8711-cd60-4862-b420-463d3830a2af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854070846 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.854070846
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.654264771
Short name T530
Test name
Test status
Simulation time 83963863 ps
CPU time 0.66 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:55 PM PDT 24
Peak memory 197620 kb
Host smart-ba7c8863-ca80-4df9-8e1c-a85a5b746ac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654264771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.654264771
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1628635410
Short name T630
Test name
Test status
Simulation time 27606096 ps
CPU time 0.6 seconds
Started Aug 10 06:03:53 PM PDT 24
Finished Aug 10 06:03:53 PM PDT 24
Peak memory 195100 kb
Host smart-799931a7-b11e-47eb-9e23-b30aba99e47e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628635410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1628635410
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.511609446
Short name T105
Test name
Test status
Simulation time 1265937429 ps
CPU time 2.33 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200168 kb
Host smart-1fbb0540-c1a7-42db-810a-77dbb30b7274
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511609446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.511609446
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1547564647
Short name T645
Test name
Test status
Simulation time 39296466 ps
CPU time 1.93 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200232 kb
Host smart-d3cc5d18-42be-4ed6-8d3a-70eab6f74c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547564647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1547564647
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3236966776
Short name T626
Test name
Test status
Simulation time 157186104 ps
CPU time 2.97 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:58 PM PDT 24
Peak memory 200172 kb
Host smart-7e60bde4-3cd5-4372-98b4-dfa6239a54c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236966776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3236966776
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4108353454
Short name T608
Test name
Test status
Simulation time 424259726385 ps
CPU time 1019.29 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:20:54 PM PDT 24
Peak memory 216668 kb
Host smart-258f39c2-77bc-4683-863e-518ad412474d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108353454 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4108353454
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1263154721
Short name T598
Test name
Test status
Simulation time 20665533 ps
CPU time 0.73 seconds
Started Aug 10 06:03:58 PM PDT 24
Finished Aug 10 06:03:58 PM PDT 24
Peak memory 198300 kb
Host smart-5a4d4b10-7429-4700-819a-4fa31f37b85c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263154721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1263154721
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2509245013
Short name T659
Test name
Test status
Simulation time 52484114 ps
CPU time 0.63 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:55 PM PDT 24
Peak memory 194996 kb
Host smart-1446f857-5aa4-4fff-8e12-0234cbf0f9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509245013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2509245013
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.356982248
Short name T620
Test name
Test status
Simulation time 44690205 ps
CPU time 2.17 seconds
Started Aug 10 06:03:53 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200128 kb
Host smart-d8a47117-ff11-45f7-8bed-26f63234796d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356982248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.356982248
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4256532849
Short name T607
Test name
Test status
Simulation time 212652209 ps
CPU time 1.31 seconds
Started Aug 10 06:03:58 PM PDT 24
Finished Aug 10 06:03:59 PM PDT 24
Peak memory 200156 kb
Host smart-5024c71f-80ba-4154-b8ce-fbb819a8275f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256532849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4256532849
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2875010694
Short name T623
Test name
Test status
Simulation time 332358206 ps
CPU time 2.76 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 200116 kb
Host smart-89afaf2c-1772-4221-93c4-47e0c0deda1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875010694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2875010694
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2001601243
Short name T540
Test name
Test status
Simulation time 374047717 ps
CPU time 2.55 seconds
Started Aug 10 06:03:58 PM PDT 24
Finished Aug 10 06:04:00 PM PDT 24
Peak memory 200312 kb
Host smart-430a0378-a1da-48dc-8ab1-284cff1bf352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001601243 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2001601243
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.51865437
Short name T580
Test name
Test status
Simulation time 27612278 ps
CPU time 0.68 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 198024 kb
Host smart-b4166702-dbff-4dac-8efd-2bf4fbd96f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51865437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.51865437
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2900997599
Short name T641
Test name
Test status
Simulation time 14741180 ps
CPU time 0.6 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:54 PM PDT 24
Peak memory 195012 kb
Host smart-27750851-6aec-4f0f-96c1-a6f4b0069dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900997599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2900997599
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4013695115
Short name T586
Test name
Test status
Simulation time 46086233 ps
CPU time 1.15 seconds
Started Aug 10 06:03:57 PM PDT 24
Finished Aug 10 06:03:59 PM PDT 24
Peak memory 200048 kb
Host smart-7c371438-1c89-463a-a2b2-5247c9fe4ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013695115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4013695115
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3940646447
Short name T577
Test name
Test status
Simulation time 245634245 ps
CPU time 1.45 seconds
Started Aug 10 06:03:53 PM PDT 24
Finished Aug 10 06:03:55 PM PDT 24
Peak memory 200140 kb
Host smart-c7d9732c-368d-4716-bb22-5eaa8972a828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940646447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3940646447
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1881429495
Short name T629
Test name
Test status
Simulation time 133578744 ps
CPU time 3.91 seconds
Started Aug 10 06:03:53 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 200376 kb
Host smart-ad77d18a-b3db-4491-ab11-3a62af43f489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881429495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1881429495
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1008588337
Short name T536
Test name
Test status
Simulation time 115409478 ps
CPU time 1.22 seconds
Started Aug 10 06:03:53 PM PDT 24
Finished Aug 10 06:03:54 PM PDT 24
Peak memory 200136 kb
Host smart-3c5b9517-82bb-4ced-a46b-e2222cad064b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008588337 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1008588337
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2381288973
Short name T99
Test name
Test status
Simulation time 55220453 ps
CPU time 0.89 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:55 PM PDT 24
Peak memory 199900 kb
Host smart-135f280b-b9f4-4959-a159-104d69a0684a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381288973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2381288973
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2819904419
Short name T593
Test name
Test status
Simulation time 13933434 ps
CPU time 0.59 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:55 PM PDT 24
Peak memory 194944 kb
Host smart-57fe199b-5003-4521-a42e-9450900cfcae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819904419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2819904419
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3986121079
Short name T606
Test name
Test status
Simulation time 403716505 ps
CPU time 1.8 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200168 kb
Host smart-04be8250-a4f6-4973-8b60-d82975d61e08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986121079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3986121079
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.4117619330
Short name T541
Test name
Test status
Simulation time 98422764 ps
CPU time 1.94 seconds
Started Aug 10 06:03:59 PM PDT 24
Finished Aug 10 06:04:01 PM PDT 24
Peak memory 200232 kb
Host smart-1cbddd59-4483-4187-ae4d-7e43508fdb37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117619330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.4117619330
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3271345301
Short name T594
Test name
Test status
Simulation time 479763684 ps
CPU time 3.95 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:58 PM PDT 24
Peak memory 200148 kb
Host smart-a6ec1621-f79f-40aa-bc4b-be3ffcbddbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271345301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3271345301
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1628825615
Short name T588
Test name
Test status
Simulation time 103657674 ps
CPU time 2.29 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200244 kb
Host smart-2a37ead5-2b2f-4369-8dc3-37456d5cb7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628825615 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1628825615
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3840183048
Short name T601
Test name
Test status
Simulation time 21307825 ps
CPU time 0.58 seconds
Started Aug 10 06:03:53 PM PDT 24
Finished Aug 10 06:03:54 PM PDT 24
Peak memory 195112 kb
Host smart-515480f8-c100-4eb5-b93f-4687e72305ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840183048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3840183048
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1186927997
Short name T575
Test name
Test status
Simulation time 79599819 ps
CPU time 1.66 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 200176 kb
Host smart-cd04bf06-7230-4f2c-9fd1-7eaac635c726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186927997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1186927997
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3256087082
Short name T583
Test name
Test status
Simulation time 47821287 ps
CPU time 1.31 seconds
Started Aug 10 06:03:56 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 200148 kb
Host smart-f8be99a3-76b4-4d70-aa64-5834f76f4991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256087082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3256087082
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2212199397
Short name T635
Test name
Test status
Simulation time 78535000 ps
CPU time 1.96 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200184 kb
Host smart-beb48638-944d-47ae-b552-82b645de68fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212199397 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2212199397
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3650352145
Short name T625
Test name
Test status
Simulation time 63794711 ps
CPU time 0.9 seconds
Started Aug 10 06:03:57 PM PDT 24
Finished Aug 10 06:03:58 PM PDT 24
Peak memory 199976 kb
Host smart-60422ade-bda8-4923-a1f8-23d2ae6b7827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650352145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3650352145
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.466621560
Short name T573
Test name
Test status
Simulation time 11199432 ps
CPU time 0.57 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:55 PM PDT 24
Peak memory 195044 kb
Host smart-597ca1ca-8514-4a91-8d8c-edc02d0c3f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466621560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.466621560
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1476377301
Short name T103
Test name
Test status
Simulation time 153426848 ps
CPU time 2.44 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:56 PM PDT 24
Peak memory 200160 kb
Host smart-9ae745a7-8dca-4d65-852d-7f551301ddd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476377301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1476377301
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1625455592
Short name T544
Test name
Test status
Simulation time 41881539 ps
CPU time 2.07 seconds
Started Aug 10 06:03:55 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 200132 kb
Host smart-2bae6a6c-b825-445d-a008-0e2fa6fbee36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625455592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1625455592
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3369809463
Short name T116
Test name
Test status
Simulation time 106336789 ps
CPU time 1.66 seconds
Started Aug 10 06:03:52 PM PDT 24
Finished Aug 10 06:03:54 PM PDT 24
Peak memory 200180 kb
Host smart-25d27228-1846-4020-8564-332196026d44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369809463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3369809463
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.534268956
Short name T600
Test name
Test status
Simulation time 228862775 ps
CPU time 1.06 seconds
Started Aug 10 06:04:12 PM PDT 24
Finished Aug 10 06:04:14 PM PDT 24
Peak memory 200056 kb
Host smart-65b39744-23ed-4ab4-b57d-d1c0fa4fe0d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534268956 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.534268956
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.302601697
Short name T94
Test name
Test status
Simulation time 180534827 ps
CPU time 0.96 seconds
Started Aug 10 06:04:01 PM PDT 24
Finished Aug 10 06:04:02 PM PDT 24
Peak memory 199960 kb
Host smart-0fb11bc4-594a-4d76-ad62-f1ecc1b8c66b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302601697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.302601697
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.985084575
Short name T644
Test name
Test status
Simulation time 15356266 ps
CPU time 0.62 seconds
Started Aug 10 06:04:01 PM PDT 24
Finished Aug 10 06:04:02 PM PDT 24
Peak memory 195200 kb
Host smart-89e6381c-fe52-464d-a656-50f25ba5748a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985084575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.985084575
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2378154531
Short name T590
Test name
Test status
Simulation time 42556942 ps
CPU time 2.03 seconds
Started Aug 10 06:03:57 PM PDT 24
Finished Aug 10 06:03:59 PM PDT 24
Peak memory 200088 kb
Host smart-5c3ec6e0-dbde-471f-b0ed-d293427fb88d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378154531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2378154531
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.912435326
Short name T624
Test name
Test status
Simulation time 435472076 ps
CPU time 4.6 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:59 PM PDT 24
Peak memory 200192 kb
Host smart-d08caec7-75f9-4b24-bb92-76592d7e53e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912435326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.912435326
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1123257246
Short name T118
Test name
Test status
Simulation time 372414241 ps
CPU time 3.24 seconds
Started Aug 10 06:03:54 PM PDT 24
Finished Aug 10 06:03:57 PM PDT 24
Peak memory 200116 kb
Host smart-05e115e9-5af7-4949-aa40-a0622758101d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123257246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1123257246
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4251716056
Short name T545
Test name
Test status
Simulation time 844660316 ps
CPU time 3.08 seconds
Started Aug 10 06:04:12 PM PDT 24
Finished Aug 10 06:04:16 PM PDT 24
Peak memory 215580 kb
Host smart-c5f34a73-998d-4d0f-9d36-0d810f375fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251716056 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4251716056
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.282597850
Short name T576
Test name
Test status
Simulation time 14316915 ps
CPU time 0.77 seconds
Started Aug 10 06:04:11 PM PDT 24
Finished Aug 10 06:04:12 PM PDT 24
Peak memory 200004 kb
Host smart-20b47b9a-3a5b-4d00-a092-777af8b99105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282597850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.282597850
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1916526795
Short name T568
Test name
Test status
Simulation time 38047133 ps
CPU time 0.55 seconds
Started Aug 10 06:04:01 PM PDT 24
Finished Aug 10 06:04:02 PM PDT 24
Peak memory 195008 kb
Host smart-74fb7bc8-606c-4be9-b235-9528776bb1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916526795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1916526795
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1060155837
Short name T107
Test name
Test status
Simulation time 620446061 ps
CPU time 1.55 seconds
Started Aug 10 06:04:02 PM PDT 24
Finished Aug 10 06:04:04 PM PDT 24
Peak memory 200228 kb
Host smart-3b1f6693-83ee-4cd3-af2e-dedd3923c54c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060155837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1060155837
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3591988229
Short name T650
Test name
Test status
Simulation time 709522854 ps
CPU time 2.28 seconds
Started Aug 10 06:04:00 PM PDT 24
Finished Aug 10 06:04:02 PM PDT 24
Peak memory 200072 kb
Host smart-2f4a0be0-fb98-45dd-8aae-1123456dac5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591988229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3591988229
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3223825475
Short name T114
Test name
Test status
Simulation time 275229210 ps
CPU time 4.33 seconds
Started Aug 10 06:04:03 PM PDT 24
Finished Aug 10 06:04:08 PM PDT 24
Peak memory 200212 kb
Host smart-d30a59af-c645-4b62-a6ff-5da4066014a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223825475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3223825475
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3731432833
Short name T654
Test name
Test status
Simulation time 35043188145 ps
CPU time 378.59 seconds
Started Aug 10 06:04:02 PM PDT 24
Finished Aug 10 06:10:21 PM PDT 24
Peak memory 215540 kb
Host smart-679fd69f-c339-4aef-ab0d-41041727f046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731432833 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3731432833
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3829858857
Short name T646
Test name
Test status
Simulation time 273845242 ps
CPU time 0.85 seconds
Started Aug 10 06:04:03 PM PDT 24
Finished Aug 10 06:04:03 PM PDT 24
Peak memory 199748 kb
Host smart-61d79889-2301-4124-8b8b-c4e9a02e4e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829858857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3829858857
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2834769105
Short name T549
Test name
Test status
Simulation time 76847599 ps
CPU time 0.59 seconds
Started Aug 10 06:04:02 PM PDT 24
Finished Aug 10 06:04:03 PM PDT 24
Peak memory 195000 kb
Host smart-d96ca86d-6cd8-4e97-8999-ecd05890cfec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834769105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2834769105
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3548680398
Short name T572
Test name
Test status
Simulation time 653091666 ps
CPU time 2.32 seconds
Started Aug 10 06:04:02 PM PDT 24
Finished Aug 10 06:04:05 PM PDT 24
Peak memory 200148 kb
Host smart-32c410e2-3bcb-4483-85a8-d89c217bda2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548680398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3548680398
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1849041993
Short name T574
Test name
Test status
Simulation time 222131384 ps
CPU time 2.14 seconds
Started Aug 10 06:04:00 PM PDT 24
Finished Aug 10 06:04:02 PM PDT 24
Peak memory 200176 kb
Host smart-4a1eae59-2152-48d6-aeb9-229f724ea254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849041993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1849041993
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.744571327
Short name T651
Test name
Test status
Simulation time 88101530 ps
CPU time 1.67 seconds
Started Aug 10 06:04:13 PM PDT 24
Finished Aug 10 06:04:15 PM PDT 24
Peak memory 200188 kb
Host smart-4ed4272f-f9c5-4ec4-9070-993511bb31aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744571327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.744571327
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.846392685
Short name T526
Test name
Test status
Simulation time 71849796436 ps
CPU time 414.76 seconds
Started Aug 10 06:04:04 PM PDT 24
Finished Aug 10 06:10:59 PM PDT 24
Peak memory 216160 kb
Host smart-c1b7266d-de3b-4890-adf2-9f1c208d67ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846392685 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.846392685
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3451270725
Short name T535
Test name
Test status
Simulation time 29655311 ps
CPU time 0.7 seconds
Started Aug 10 06:04:02 PM PDT 24
Finished Aug 10 06:04:03 PM PDT 24
Peak memory 198004 kb
Host smart-de0cd84d-5e82-4a70-a4e3-fd41145869a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451270725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3451270725
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3159242122
Short name T595
Test name
Test status
Simulation time 60000407 ps
CPU time 0.61 seconds
Started Aug 10 06:04:12 PM PDT 24
Finished Aug 10 06:04:12 PM PDT 24
Peak memory 195156 kb
Host smart-7cb7c721-4af7-450f-9d3d-af00e42c493c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159242122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3159242122
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3844054233
Short name T640
Test name
Test status
Simulation time 563694468 ps
CPU time 2.37 seconds
Started Aug 10 06:04:11 PM PDT 24
Finished Aug 10 06:04:14 PM PDT 24
Peak memory 200168 kb
Host smart-63b30837-5aa8-424a-87ad-41e35d68d4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844054233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3844054233
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1886835413
Short name T533
Test name
Test status
Simulation time 345346369 ps
CPU time 3.38 seconds
Started Aug 10 06:04:12 PM PDT 24
Finished Aug 10 06:04:16 PM PDT 24
Peak memory 200136 kb
Host smart-5d8a2a84-b62d-4cff-85aa-74de770246af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886835413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1886835413
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2128831669
Short name T91
Test name
Test status
Simulation time 108933179 ps
CPU time 5.33 seconds
Started Aug 10 06:03:19 PM PDT 24
Finished Aug 10 06:03:25 PM PDT 24
Peak memory 200192 kb
Host smart-6b1b218d-d4ba-426c-b1fa-5411bfa73fb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128831669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2128831669
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1417243476
Short name T102
Test name
Test status
Simulation time 1079095773 ps
CPU time 5.88 seconds
Started Aug 10 06:03:20 PM PDT 24
Finished Aug 10 06:03:26 PM PDT 24
Peak memory 200144 kb
Host smart-49cb26c0-854a-4aff-97f6-40f718078eac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417243476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1417243476
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.798787073
Short name T566
Test name
Test status
Simulation time 26671193 ps
CPU time 0.8 seconds
Started Aug 10 06:03:17 PM PDT 24
Finished Aug 10 06:03:18 PM PDT 24
Peak memory 199220 kb
Host smart-ec86d6cd-71bb-474a-8c50-ef5adccf29d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798787073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.798787073
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3162565115
Short name T560
Test name
Test status
Simulation time 133893120 ps
CPU time 1.1 seconds
Started Aug 10 06:03:20 PM PDT 24
Finished Aug 10 06:03:21 PM PDT 24
Peak memory 200064 kb
Host smart-74992c6a-6a28-4600-a69a-34baa32c9a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162565115 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3162565115
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1780322957
Short name T579
Test name
Test status
Simulation time 59050860 ps
CPU time 0.91 seconds
Started Aug 10 06:03:19 PM PDT 24
Finished Aug 10 06:03:20 PM PDT 24
Peak memory 199992 kb
Host smart-c03f9d57-766a-4c65-a342-bf3d470dd61f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780322957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1780322957
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2135907503
Short name T571
Test name
Test status
Simulation time 11606928 ps
CPU time 0.6 seconds
Started Aug 10 06:03:18 PM PDT 24
Finished Aug 10 06:03:18 PM PDT 24
Peak memory 195208 kb
Host smart-5b9367d9-9c01-4ac2-8b5d-b60dc1152d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135907503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2135907503
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3789017834
Short name T631
Test name
Test status
Simulation time 55182203 ps
CPU time 1.14 seconds
Started Aug 10 06:03:21 PM PDT 24
Finished Aug 10 06:03:22 PM PDT 24
Peak memory 198624 kb
Host smart-c691b611-8476-4087-9865-f70bc6554ac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789017834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3789017834
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4266342585
Short name T537
Test name
Test status
Simulation time 26879142 ps
CPU time 1.37 seconds
Started Aug 10 06:03:18 PM PDT 24
Finished Aug 10 06:03:20 PM PDT 24
Peak memory 200156 kb
Host smart-9bb51c02-3945-47a0-859d-482484e3566f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266342585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.4266342585
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1681484293
Short name T119
Test name
Test status
Simulation time 857622700 ps
CPU time 4.24 seconds
Started Aug 10 06:03:18 PM PDT 24
Finished Aug 10 06:03:23 PM PDT 24
Peak memory 200056 kb
Host smart-5a9f722a-ba2d-4d8c-a5f9-80611b1a511e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681484293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1681484293
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2818780190
Short name T652
Test name
Test status
Simulation time 17803237 ps
CPU time 0.62 seconds
Started Aug 10 06:04:02 PM PDT 24
Finished Aug 10 06:04:02 PM PDT 24
Peak memory 195056 kb
Host smart-eeeb6a6a-9391-4cb0-b45b-a580f7cfddbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818780190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2818780190
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1377257486
Short name T643
Test name
Test status
Simulation time 14228879 ps
CPU time 0.63 seconds
Started Aug 10 06:04:14 PM PDT 24
Finished Aug 10 06:04:15 PM PDT 24
Peak memory 195140 kb
Host smart-c3a67b6f-0006-4adb-a6a1-b07c5b64bf9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377257486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1377257486
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.124505631
Short name T569
Test name
Test status
Simulation time 21092967 ps
CPU time 0.55 seconds
Started Aug 10 06:04:04 PM PDT 24
Finished Aug 10 06:04:05 PM PDT 24
Peak memory 195032 kb
Host smart-3e946026-081a-4a9e-916f-fb54a1a2cc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124505631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.124505631
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2074669506
Short name T553
Test name
Test status
Simulation time 12465996 ps
CPU time 0.58 seconds
Started Aug 10 06:04:09 PM PDT 24
Finished Aug 10 06:04:10 PM PDT 24
Peak memory 195044 kb
Host smart-b6a84adc-a2ad-42e7-be5d-0c24cce16520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074669506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2074669506
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4275042163
Short name T564
Test name
Test status
Simulation time 39161464 ps
CPU time 0.57 seconds
Started Aug 10 06:04:10 PM PDT 24
Finished Aug 10 06:04:11 PM PDT 24
Peak memory 195092 kb
Host smart-c402bb69-9a2e-4eca-8fe5-f6f2a120937a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275042163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4275042163
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.628681942
Short name T656
Test name
Test status
Simulation time 56193433 ps
CPU time 0.59 seconds
Started Aug 10 06:04:10 PM PDT 24
Finished Aug 10 06:04:10 PM PDT 24
Peak memory 195052 kb
Host smart-07058436-7e7f-4b33-b042-25df147b21ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628681942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.628681942
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.43757456
Short name T628
Test name
Test status
Simulation time 69597725 ps
CPU time 0.6 seconds
Started Aug 10 06:04:19 PM PDT 24
Finished Aug 10 06:04:20 PM PDT 24
Peak memory 194840 kb
Host smart-18420cf3-cd8e-4a02-a674-45bef97abc70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43757456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.43757456
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2033089264
Short name T578
Test name
Test status
Simulation time 43486904 ps
CPU time 0.55 seconds
Started Aug 10 06:04:10 PM PDT 24
Finished Aug 10 06:04:10 PM PDT 24
Peak memory 195036 kb
Host smart-a7fed956-1d15-41f5-b08e-00592712bd60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033089264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2033089264
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1960343488
Short name T547
Test name
Test status
Simulation time 28689096 ps
CPU time 0.66 seconds
Started Aug 10 06:04:19 PM PDT 24
Finished Aug 10 06:04:20 PM PDT 24
Peak memory 195024 kb
Host smart-f08f02a5-920a-43d4-9b89-e23eb7239ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960343488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1960343488
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3347910030
Short name T642
Test name
Test status
Simulation time 40214001 ps
CPU time 0.59 seconds
Started Aug 10 06:04:09 PM PDT 24
Finished Aug 10 06:04:10 PM PDT 24
Peak memory 195156 kb
Host smart-b3def7a8-566e-45f0-9182-ff25e4dd4b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347910030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3347910030
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4245937457
Short name T619
Test name
Test status
Simulation time 924853750 ps
CPU time 8.64 seconds
Started Aug 10 06:03:28 PM PDT 24
Finished Aug 10 06:03:36 PM PDT 24
Peak memory 199992 kb
Host smart-7409e899-d646-47f5-a920-7450e544e828
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245937457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4245937457
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.50950142
Short name T647
Test name
Test status
Simulation time 476951511 ps
CPU time 5.69 seconds
Started Aug 10 06:03:18 PM PDT 24
Finished Aug 10 06:03:24 PM PDT 24
Peak memory 200172 kb
Host smart-dc851424-3afe-424d-ab01-945b010e2147
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50950142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.50950142
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.947756618
Short name T615
Test name
Test status
Simulation time 67415812 ps
CPU time 0.88 seconds
Started Aug 10 06:03:23 PM PDT 24
Finished Aug 10 06:03:24 PM PDT 24
Peak memory 199216 kb
Host smart-83df5a8b-0c1f-4f66-8ce9-a20b2b21bade
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947756618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.947756618
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.212415634
Short name T582
Test name
Test status
Simulation time 190635052 ps
CPU time 2.45 seconds
Started Aug 10 06:03:27 PM PDT 24
Finished Aug 10 06:03:29 PM PDT 24
Peak memory 208488 kb
Host smart-3e7c337c-ce6b-4dcd-ba4f-caca19b74268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212415634 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.212415634
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1456239410
Short name T96
Test name
Test status
Simulation time 21947437 ps
CPU time 0.69 seconds
Started Aug 10 06:03:19 PM PDT 24
Finished Aug 10 06:03:20 PM PDT 24
Peak memory 198144 kb
Host smart-27eb8fe0-1fd9-497b-8098-7ecd06c27af4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456239410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1456239410
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4039975486
Short name T655
Test name
Test status
Simulation time 121932714 ps
CPU time 0.6 seconds
Started Aug 10 06:03:23 PM PDT 24
Finished Aug 10 06:03:24 PM PDT 24
Peak memory 195024 kb
Host smart-28d9993a-e4fd-42bf-bfc6-8c8d540e9c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039975486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4039975486
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.102491943
Short name T610
Test name
Test status
Simulation time 156039298 ps
CPU time 2.33 seconds
Started Aug 10 06:03:29 PM PDT 24
Finished Aug 10 06:03:31 PM PDT 24
Peak memory 200004 kb
Host smart-a4a98592-5213-4344-ab80-a86266335862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102491943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.102491943
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2755068160
Short name T612
Test name
Test status
Simulation time 29905752 ps
CPU time 1.44 seconds
Started Aug 10 06:03:20 PM PDT 24
Finished Aug 10 06:03:22 PM PDT 24
Peak memory 200088 kb
Host smart-65ca7b5b-ea1d-4029-a142-e7d88bdb6c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755068160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2755068160
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.288824876
Short name T622
Test name
Test status
Simulation time 595333510 ps
CPU time 2.85 seconds
Started Aug 10 06:03:18 PM PDT 24
Finished Aug 10 06:03:21 PM PDT 24
Peak memory 200156 kb
Host smart-81395a42-e5c2-4d7b-90fc-caec36603ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288824876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.288824876
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.189388784
Short name T585
Test name
Test status
Simulation time 11429657 ps
CPU time 0.56 seconds
Started Aug 10 06:04:11 PM PDT 24
Finished Aug 10 06:04:12 PM PDT 24
Peak memory 195032 kb
Host smart-f07c347f-bbc7-4c89-8235-84a82db78ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189388784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.189388784
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3975743550
Short name T528
Test name
Test status
Simulation time 31874647 ps
CPU time 0.57 seconds
Started Aug 10 06:04:10 PM PDT 24
Finished Aug 10 06:04:11 PM PDT 24
Peak memory 194992 kb
Host smart-227bfafd-89c8-49a7-9dc1-ffa8902e154a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975743550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3975743550
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2878185624
Short name T618
Test name
Test status
Simulation time 11207058 ps
CPU time 0.59 seconds
Started Aug 10 06:04:11 PM PDT 24
Finished Aug 10 06:04:11 PM PDT 24
Peak memory 195028 kb
Host smart-1bd0e54d-0b7b-4f06-90d5-a5f4fe3dd096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878185624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2878185624
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3585890441
Short name T550
Test name
Test status
Simulation time 53443327 ps
CPU time 0.6 seconds
Started Aug 10 06:04:08 PM PDT 24
Finished Aug 10 06:04:09 PM PDT 24
Peak memory 195092 kb
Host smart-1b4f7f09-40cd-44dc-8cea-7030db05515e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585890441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3585890441
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1302284466
Short name T543
Test name
Test status
Simulation time 23651441 ps
CPU time 0.59 seconds
Started Aug 10 06:04:17 PM PDT 24
Finished Aug 10 06:04:18 PM PDT 24
Peak memory 195032 kb
Host smart-e57be56a-87cb-4189-bd57-9b5fbeab25c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302284466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1302284466
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3309524727
Short name T627
Test name
Test status
Simulation time 13150879 ps
CPU time 0.57 seconds
Started Aug 10 06:04:20 PM PDT 24
Finished Aug 10 06:04:21 PM PDT 24
Peak memory 195060 kb
Host smart-1e5475da-9bad-4708-9443-a9cd9df0c28c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309524727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3309524727
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.104201570
Short name T636
Test name
Test status
Simulation time 16885337 ps
CPU time 0.59 seconds
Started Aug 10 06:04:19 PM PDT 24
Finished Aug 10 06:04:20 PM PDT 24
Peak memory 195112 kb
Host smart-4d638594-4632-4b0e-a72f-b1d16fd348c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104201570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.104201570
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3371608554
Short name T542
Test name
Test status
Simulation time 17975616 ps
CPU time 0.57 seconds
Started Aug 10 06:04:17 PM PDT 24
Finished Aug 10 06:04:18 PM PDT 24
Peak memory 194992 kb
Host smart-cfa5b968-b14f-4b0a-9a16-06e244e7c964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371608554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3371608554
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4167620184
Short name T563
Test name
Test status
Simulation time 15785594 ps
CPU time 0.6 seconds
Started Aug 10 06:04:20 PM PDT 24
Finished Aug 10 06:04:20 PM PDT 24
Peak memory 195232 kb
Host smart-9744b19d-624e-4369-b25a-a34be9ade7e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167620184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4167620184
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2448064761
Short name T527
Test name
Test status
Simulation time 45183150 ps
CPU time 0.55 seconds
Started Aug 10 06:04:16 PM PDT 24
Finished Aug 10 06:04:17 PM PDT 24
Peak memory 195040 kb
Host smart-d1d05456-71b3-479f-8cd8-6f8cf98091eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448064761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2448064761
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.155079057
Short name T609
Test name
Test status
Simulation time 597593731 ps
CPU time 9.24 seconds
Started Aug 10 06:03:29 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 200100 kb
Host smart-16b855f1-01d8-4608-a83f-c6590bedda2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155079057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.155079057
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1626201692
Short name T100
Test name
Test status
Simulation time 328173877 ps
CPU time 13.51 seconds
Started Aug 10 06:03:26 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 200156 kb
Host smart-27193e72-224c-409b-b64d-04b60bb298b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626201692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1626201692
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.842941725
Short name T92
Test name
Test status
Simulation time 45035175 ps
CPU time 1 seconds
Started Aug 10 06:03:27 PM PDT 24
Finished Aug 10 06:03:29 PM PDT 24
Peak memory 199444 kb
Host smart-e07edd5a-8697-479c-8c2d-cf4ba203d4b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842941725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.842941725
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1525365898
Short name T611
Test name
Test status
Simulation time 42088307 ps
CPU time 1.18 seconds
Started Aug 10 06:03:36 PM PDT 24
Finished Aug 10 06:03:37 PM PDT 24
Peak memory 200076 kb
Host smart-1107210e-d14f-40ce-b378-de67ac540acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525365898 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1525365898
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1054780456
Short name T581
Test name
Test status
Simulation time 46128304 ps
CPU time 0.77 seconds
Started Aug 10 06:03:26 PM PDT 24
Finished Aug 10 06:03:27 PM PDT 24
Peak memory 199640 kb
Host smart-7e33fef8-12b9-4563-8ea8-6fe69a45ef64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054780456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1054780456
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2386077067
Short name T589
Test name
Test status
Simulation time 11808578 ps
CPU time 0.59 seconds
Started Aug 10 06:03:28 PM PDT 24
Finished Aug 10 06:03:29 PM PDT 24
Peak memory 195072 kb
Host smart-bb01398e-610b-4db4-950c-a17181eb3dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386077067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2386077067
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3503933504
Short name T104
Test name
Test status
Simulation time 1214211368 ps
CPU time 2.34 seconds
Started Aug 10 06:03:27 PM PDT 24
Finished Aug 10 06:03:30 PM PDT 24
Peak memory 200212 kb
Host smart-00b44339-70ec-4b7b-af98-92c534c856be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503933504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3503933504
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.221556089
Short name T637
Test name
Test status
Simulation time 57392500 ps
CPU time 1.39 seconds
Started Aug 10 06:03:28 PM PDT 24
Finished Aug 10 06:03:29 PM PDT 24
Peak memory 200148 kb
Host smart-a81ddf52-6591-4b9b-90ce-92f9ee50be62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221556089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.221556089
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.276656241
Short name T616
Test name
Test status
Simulation time 2715974452 ps
CPU time 4.13 seconds
Started Aug 10 06:03:29 PM PDT 24
Finished Aug 10 06:03:33 PM PDT 24
Peak memory 200192 kb
Host smart-8330db79-9412-4d07-993f-2d4e2e0a12f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276656241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.276656241
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1425177992
Short name T532
Test name
Test status
Simulation time 117965856 ps
CPU time 0.57 seconds
Started Aug 10 06:04:18 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 194980 kb
Host smart-a273960b-77cc-4902-80d3-be0a837b76b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425177992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1425177992
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2856443248
Short name T596
Test name
Test status
Simulation time 15685410 ps
CPU time 0.58 seconds
Started Aug 10 06:04:18 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 195048 kb
Host smart-d8b6bb6e-281a-4cfb-bc86-5b5ececa09c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856443248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2856443248
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1918019846
Short name T613
Test name
Test status
Simulation time 12223858 ps
CPU time 0.56 seconds
Started Aug 10 06:04:17 PM PDT 24
Finished Aug 10 06:04:18 PM PDT 24
Peak memory 194944 kb
Host smart-d3d80453-dffb-4d95-a65c-51f3952fc301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918019846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1918019846
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3893252178
Short name T638
Test name
Test status
Simulation time 46130689 ps
CPU time 0.6 seconds
Started Aug 10 06:04:19 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 195088 kb
Host smart-cd237c20-9e2d-4d50-acd5-40a069217e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893252178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3893252178
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3970435401
Short name T529
Test name
Test status
Simulation time 22637330 ps
CPU time 0.58 seconds
Started Aug 10 06:04:18 PM PDT 24
Finished Aug 10 06:04:18 PM PDT 24
Peak memory 195024 kb
Host smart-088cacd1-63d1-4da3-acb6-25c6c6d8e117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970435401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3970435401
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2615385494
Short name T597
Test name
Test status
Simulation time 17556002 ps
CPU time 0.61 seconds
Started Aug 10 06:04:17 PM PDT 24
Finished Aug 10 06:04:18 PM PDT 24
Peak memory 194944 kb
Host smart-7cdb2472-799e-44f8-8475-e3673d465846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615385494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2615385494
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2795098977
Short name T539
Test name
Test status
Simulation time 14493188 ps
CPU time 0.66 seconds
Started Aug 10 06:04:18 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 195036 kb
Host smart-4d625c18-6200-405d-bb0c-604db90382da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795098977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2795098977
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1896591955
Short name T591
Test name
Test status
Simulation time 13666377 ps
CPU time 0.6 seconds
Started Aug 10 06:04:17 PM PDT 24
Finished Aug 10 06:04:17 PM PDT 24
Peak memory 195072 kb
Host smart-85b06d97-bd41-4503-b9a0-e08dd55f818b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896591955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1896591955
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3110817233
Short name T562
Test name
Test status
Simulation time 11949310 ps
CPU time 0.6 seconds
Started Aug 10 06:04:17 PM PDT 24
Finished Aug 10 06:04:17 PM PDT 24
Peak memory 195368 kb
Host smart-03d38050-affa-4534-b277-5fba377e3ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110817233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3110817233
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3991669849
Short name T555
Test name
Test status
Simulation time 43824307 ps
CPU time 0.61 seconds
Started Aug 10 06:04:18 PM PDT 24
Finished Aug 10 06:04:19 PM PDT 24
Peak memory 195012 kb
Host smart-4aec119c-a032-4fa3-8abd-14783584a41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991669849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3991669849
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1152434976
Short name T599
Test name
Test status
Simulation time 161858479 ps
CPU time 2.7 seconds
Started Aug 10 06:03:38 PM PDT 24
Finished Aug 10 06:03:41 PM PDT 24
Peak memory 208448 kb
Host smart-a96c2ced-cf15-460b-8789-c99f935a9fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152434976 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1152434976
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2884175302
Short name T649
Test name
Test status
Simulation time 50788742 ps
CPU time 0.75 seconds
Started Aug 10 06:03:35 PM PDT 24
Finished Aug 10 06:03:36 PM PDT 24
Peak memory 199036 kb
Host smart-c02372f8-a500-46f6-a14b-fd287818f9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884175302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2884175302
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1450861091
Short name T634
Test name
Test status
Simulation time 32998597 ps
CPU time 0.62 seconds
Started Aug 10 06:03:38 PM PDT 24
Finished Aug 10 06:03:38 PM PDT 24
Peak memory 195352 kb
Host smart-6912e933-1b08-49db-bd73-9b3a1b1d2f0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450861091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1450861091
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.407601450
Short name T108
Test name
Test status
Simulation time 294553766 ps
CPU time 1.14 seconds
Started Aug 10 06:03:38 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 200108 kb
Host smart-cc982f08-8bbe-4434-a7cf-c285d500c4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407601450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.407601450
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3042436535
Short name T561
Test name
Test status
Simulation time 122965753 ps
CPU time 2.58 seconds
Started Aug 10 06:03:36 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 200156 kb
Host smart-1a749b15-b6de-47a1-bc43-600ee2fea435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042436535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3042436535
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3906411392
Short name T115
Test name
Test status
Simulation time 242846560 ps
CPU time 3.82 seconds
Started Aug 10 06:03:35 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 200080 kb
Host smart-30a99183-7320-4a7a-9def-77aac7374102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906411392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3906411392
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1531874629
Short name T621
Test name
Test status
Simulation time 511249480349 ps
CPU time 519.72 seconds
Started Aug 10 06:03:46 PM PDT 24
Finished Aug 10 06:12:26 PM PDT 24
Peak memory 215872 kb
Host smart-3e567216-df3d-4faf-8801-3e9dfee1a479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531874629 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1531874629
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3879218829
Short name T605
Test name
Test status
Simulation time 51288058 ps
CPU time 0.87 seconds
Started Aug 10 06:03:36 PM PDT 24
Finished Aug 10 06:03:37 PM PDT 24
Peak memory 199804 kb
Host smart-0d631279-8137-4da3-998e-19acfa979299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879218829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3879218829
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1147331367
Short name T567
Test name
Test status
Simulation time 19402556 ps
CPU time 0.63 seconds
Started Aug 10 06:03:36 PM PDT 24
Finished Aug 10 06:03:37 PM PDT 24
Peak memory 195136 kb
Host smart-90b0bfdf-9f39-4c5e-aca9-032f886efdee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147331367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1147331367
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2136957163
Short name T559
Test name
Test status
Simulation time 393678301 ps
CPU time 2.39 seconds
Started Aug 10 06:03:48 PM PDT 24
Finished Aug 10 06:03:50 PM PDT 24
Peak memory 200168 kb
Host smart-91bd664b-d687-4c65-aff0-05c585b46f0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136957163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2136957163
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1269077769
Short name T603
Test name
Test status
Simulation time 468327924 ps
CPU time 2.78 seconds
Started Aug 10 06:03:37 PM PDT 24
Finished Aug 10 06:03:40 PM PDT 24
Peak memory 200116 kb
Host smart-e128e423-bf70-49e5-9c64-c0a05fc1b371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269077769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1269077769
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2345310277
Short name T658
Test name
Test status
Simulation time 438789883 ps
CPU time 3.86 seconds
Started Aug 10 06:03:38 PM PDT 24
Finished Aug 10 06:03:42 PM PDT 24
Peak memory 200144 kb
Host smart-3141b41b-4e02-4e14-998b-7a38da4fd457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345310277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2345310277
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.673946219
Short name T531
Test name
Test status
Simulation time 97966238 ps
CPU time 2.39 seconds
Started Aug 10 06:03:44 PM PDT 24
Finished Aug 10 06:03:46 PM PDT 24
Peak memory 200320 kb
Host smart-9611e701-70a7-4fd8-928d-169dc857eb07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673946219 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.673946219
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.994634014
Short name T106
Test name
Test status
Simulation time 12766739 ps
CPU time 0.69 seconds
Started Aug 10 06:03:45 PM PDT 24
Finished Aug 10 06:03:46 PM PDT 24
Peak memory 198288 kb
Host smart-ab1e44df-b897-44b4-9993-19a9509fbbae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994634014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.994634014
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2706777989
Short name T534
Test name
Test status
Simulation time 32984758 ps
CPU time 0.64 seconds
Started Aug 10 06:03:45 PM PDT 24
Finished Aug 10 06:03:46 PM PDT 24
Peak memory 195184 kb
Host smart-fffe5e7e-753b-46cc-81d4-dccb5b81383e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706777989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2706777989
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3565589220
Short name T109
Test name
Test status
Simulation time 167995118 ps
CPU time 1.09 seconds
Started Aug 10 06:03:45 PM PDT 24
Finished Aug 10 06:03:46 PM PDT 24
Peak memory 199924 kb
Host smart-5fdf1192-0091-4913-a83c-be24a48c9c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565589220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3565589220
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3681594802
Short name T556
Test name
Test status
Simulation time 443142420 ps
CPU time 3.03 seconds
Started Aug 10 06:03:48 PM PDT 24
Finished Aug 10 06:03:51 PM PDT 24
Peak memory 200140 kb
Host smart-02725897-2ed2-4163-8ba0-f1b7e816432d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681594802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3681594802
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1791893582
Short name T639
Test name
Test status
Simulation time 272644488 ps
CPU time 3.58 seconds
Started Aug 10 06:03:44 PM PDT 24
Finished Aug 10 06:03:48 PM PDT 24
Peak memory 200104 kb
Host smart-85ed24f5-6d5d-4149-afcd-cd42c8d9c13d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791893582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1791893582
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.470752850
Short name T551
Test name
Test status
Simulation time 162488802 ps
CPU time 2.39 seconds
Started Aug 10 06:03:48 PM PDT 24
Finished Aug 10 06:03:50 PM PDT 24
Peak memory 215796 kb
Host smart-16823027-221d-44c3-a185-23ca9dda3a96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470752850 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.470752850
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.500111961
Short name T98
Test name
Test status
Simulation time 19845846 ps
CPU time 0.9 seconds
Started Aug 10 06:03:48 PM PDT 24
Finished Aug 10 06:03:49 PM PDT 24
Peak memory 199836 kb
Host smart-d89f8076-aade-4e10-9dca-cd437a27b4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500111961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.500111961
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.271532435
Short name T538
Test name
Test status
Simulation time 20577972 ps
CPU time 0.61 seconds
Started Aug 10 06:03:46 PM PDT 24
Finished Aug 10 06:03:47 PM PDT 24
Peak memory 194956 kb
Host smart-ed854272-df3b-4366-b4d1-79b18d9aabc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271532435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.271532435
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.394464387
Short name T570
Test name
Test status
Simulation time 99198284 ps
CPU time 1.75 seconds
Started Aug 10 06:03:44 PM PDT 24
Finished Aug 10 06:03:46 PM PDT 24
Peak memory 200168 kb
Host smart-b2aaac40-f6ce-4b2a-875a-6e9a579d89fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394464387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.394464387
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3544208421
Short name T657
Test name
Test status
Simulation time 364988491 ps
CPU time 2.98 seconds
Started Aug 10 06:03:44 PM PDT 24
Finished Aug 10 06:03:47 PM PDT 24
Peak memory 200156 kb
Host smart-d0e5b5cc-bb30-40c1-8c1e-b222725119d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544208421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3544208421
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.141672469
Short name T62
Test name
Test status
Simulation time 308250727 ps
CPU time 3.15 seconds
Started Aug 10 06:03:46 PM PDT 24
Finished Aug 10 06:03:49 PM PDT 24
Peak memory 200204 kb
Host smart-ca6e0ea3-0b5e-4dad-84ee-2c63451fbfbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141672469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.141672469
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2054849895
Short name T554
Test name
Test status
Simulation time 86932791 ps
CPU time 2.38 seconds
Started Aug 10 06:03:46 PM PDT 24
Finished Aug 10 06:03:49 PM PDT 24
Peak memory 215632 kb
Host smart-d677422d-d74b-4c3f-861e-39f3d3cb47fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054849895 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2054849895
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1347276191
Short name T93
Test name
Test status
Simulation time 72942276 ps
CPU time 0.96 seconds
Started Aug 10 06:03:46 PM PDT 24
Finished Aug 10 06:03:47 PM PDT 24
Peak memory 199920 kb
Host smart-38e16627-25cd-4e10-927b-900960b86fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347276191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1347276191
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.960084944
Short name T587
Test name
Test status
Simulation time 33743831 ps
CPU time 0.61 seconds
Started Aug 10 06:03:47 PM PDT 24
Finished Aug 10 06:03:48 PM PDT 24
Peak memory 195020 kb
Host smart-998497da-59e0-4ca1-8a91-c1e62b702a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960084944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.960084944
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3194382650
Short name T565
Test name
Test status
Simulation time 317804205 ps
CPU time 2.15 seconds
Started Aug 10 06:03:45 PM PDT 24
Finished Aug 10 06:03:48 PM PDT 24
Peak memory 200064 kb
Host smart-a756affa-5a59-42f9-8dfe-181b02d4e467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194382650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3194382650
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1020106843
Short name T614
Test name
Test status
Simulation time 77099023 ps
CPU time 1.69 seconds
Started Aug 10 06:03:45 PM PDT 24
Finished Aug 10 06:03:46 PM PDT 24
Peak memory 200168 kb
Host smart-d6ae8cf4-2433-4544-ab95-01b8383afc06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020106843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1020106843
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3005540395
Short name T64
Test name
Test status
Simulation time 125203128 ps
CPU time 1.65 seconds
Started Aug 10 06:03:48 PM PDT 24
Finished Aug 10 06:03:50 PM PDT 24
Peak memory 200088 kb
Host smart-45bf0332-05f2-49c1-b2aa-000751d70be3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005540395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3005540395
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1779181907
Short name T453
Test name
Test status
Simulation time 14514241 ps
CPU time 0.61 seconds
Started Aug 10 05:03:10 PM PDT 24
Finished Aug 10 05:03:11 PM PDT 24
Peak memory 195872 kb
Host smart-4526bd3d-3d09-4d5b-bffe-d78587cb50a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779181907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1779181907
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2083066397
Short name T43
Test name
Test status
Simulation time 1820369025 ps
CPU time 25.89 seconds
Started Aug 10 05:03:11 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 199788 kb
Host smart-6b09df6f-1db7-4276-b982-c0695a38cfb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083066397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2083066397
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3271047522
Short name T422
Test name
Test status
Simulation time 9575794612 ps
CPU time 43.34 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:03:51 PM PDT 24
Peak memory 199868 kb
Host smart-82f9afdd-0949-430f-ac8c-68d2510e3be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271047522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3271047522
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1635907595
Short name T497
Test name
Test status
Simulation time 90415894 ps
CPU time 6.33 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:03:14 PM PDT 24
Peak memory 199780 kb
Host smart-93bc1d25-88de-4e84-81d7-e07f64a879f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635907595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1635907595
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.233320464
Short name T158
Test name
Test status
Simulation time 3714662922 ps
CPU time 126.19 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 199852 kb
Host smart-b23c13b8-43df-4223-bbe3-29779583bb4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233320464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.233320464
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1481271978
Short name T402
Test name
Test status
Simulation time 20458249182 ps
CPU time 136.6 seconds
Started Aug 10 05:03:10 PM PDT 24
Finished Aug 10 05:05:26 PM PDT 24
Peak memory 216072 kb
Host smart-06a6abce-37d9-4418-bf15-af5595205fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481271978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1481271978
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2879535695
Short name T430
Test name
Test status
Simulation time 212244861 ps
CPU time 9.25 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:03:18 PM PDT 24
Peak memory 199696 kb
Host smart-a8c47552-97aa-4d06-a30a-08298ed88cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879535695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2879535695
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3844847039
Short name T400
Test name
Test status
Simulation time 115270280395 ps
CPU time 1755.25 seconds
Started Aug 10 05:03:05 PM PDT 24
Finished Aug 10 05:32:21 PM PDT 24
Peak memory 722556 kb
Host smart-0c86c85c-cc58-4071-8835-a7847f0c88d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844847039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3844847039
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3241397172
Short name T21
Test name
Test status
Simulation time 336496135721 ps
CPU time 2038.8 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:37:07 PM PDT 24
Peak memory 396488 kb
Host smart-1a6ba619-af82-4ed2-b781-af810a76894c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241397172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3241397172
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1015812204
Short name T207
Test name
Test status
Simulation time 31381591504 ps
CPU time 77.15 seconds
Started Aug 10 05:03:07 PM PDT 24
Finished Aug 10 05:04:24 PM PDT 24
Peak memory 199852 kb
Host smart-76863930-de1f-4419-8c33-801a90e72e0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1015812204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1015812204
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.4271158352
Short name T187
Test name
Test status
Simulation time 10926276936 ps
CPU time 57.64 seconds
Started Aug 10 05:03:10 PM PDT 24
Finished Aug 10 05:04:08 PM PDT 24
Peak memory 199820 kb
Host smart-9f1d1493-05b0-4bad-814b-17ab90202e03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4271158352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4271158352
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3609858436
Short name T415
Test name
Test status
Simulation time 43977693169 ps
CPU time 133.47 seconds
Started Aug 10 05:03:10 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 199836 kb
Host smart-986e5412-4745-4070-8a62-ddcfce072e23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3609858436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3609858436
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3719905283
Short name T458
Test name
Test status
Simulation time 112717815725 ps
CPU time 688.8 seconds
Started Aug 10 05:03:09 PM PDT 24
Finished Aug 10 05:14:38 PM PDT 24
Peak memory 199724 kb
Host smart-fefbf556-6519-4a1d-9c76-ed2c8556c208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3719905283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3719905283
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1299643626
Short name T276
Test name
Test status
Simulation time 2234606897111 ps
CPU time 2392.21 seconds
Started Aug 10 05:03:07 PM PDT 24
Finished Aug 10 05:43:00 PM PDT 24
Peak memory 215228 kb
Host smart-bc36218a-f44e-465e-9785-e63674dcda1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1299643626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1299643626
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.849229683
Short name T174
Test name
Test status
Simulation time 7697425153 ps
CPU time 26.26 seconds
Started Aug 10 05:03:10 PM PDT 24
Finished Aug 10 05:03:36 PM PDT 24
Peak memory 199820 kb
Host smart-437db576-fe38-498c-9a31-d14ff947cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849229683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.849229683
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2518808667
Short name T398
Test name
Test status
Simulation time 23842367 ps
CPU time 0.6 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:03:20 PM PDT 24
Peak memory 195924 kb
Host smart-ac3ad2e2-132d-444f-84e3-0fef5c6281fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518808667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2518808667
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.6683617
Short name T258
Test name
Test status
Simulation time 5904199362 ps
CPU time 84.41 seconds
Started Aug 10 05:03:08 PM PDT 24
Finished Aug 10 05:04:32 PM PDT 24
Peak memory 216232 kb
Host smart-aec0618c-cf6b-4dd9-888a-d7b8e517d8fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6683617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.6683617
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1901320998
Short name T287
Test name
Test status
Simulation time 7001088043 ps
CPU time 46.2 seconds
Started Aug 10 05:03:07 PM PDT 24
Finished Aug 10 05:03:53 PM PDT 24
Peak memory 199844 kb
Host smart-c0c5b76f-c3f9-4e1b-8866-e3d00e773b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901320998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1901320998
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2273706407
Short name T206
Test name
Test status
Simulation time 1832580921 ps
CPU time 304.62 seconds
Started Aug 10 05:03:06 PM PDT 24
Finished Aug 10 05:08:10 PM PDT 24
Peak memory 664928 kb
Host smart-b69e1981-4739-4715-922a-d65bc35341d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273706407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2273706407
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3462962745
Short name T487
Test name
Test status
Simulation time 33871197542 ps
CPU time 99.99 seconds
Started Aug 10 05:03:07 PM PDT 24
Finished Aug 10 05:04:47 PM PDT 24
Peak memory 199860 kb
Host smart-4836af29-0c4f-4096-955a-8d1ca83ca06e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462962745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3462962745
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.180089797
Short name T156
Test name
Test status
Simulation time 26004715566 ps
CPU time 98.44 seconds
Started Aug 10 05:03:07 PM PDT 24
Finished Aug 10 05:04:46 PM PDT 24
Peak memory 208092 kb
Host smart-bcb43cb1-6f49-4fd9-a8b1-949175717b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180089797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.180089797
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1678435365
Short name T36
Test name
Test status
Simulation time 97728349 ps
CPU time 0.96 seconds
Started Aug 10 05:03:18 PM PDT 24
Finished Aug 10 05:03:19 PM PDT 24
Peak memory 218416 kb
Host smart-e5cbd641-ca69-4665-82d3-bc71fc12cea3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678435365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1678435365
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1731244322
Short name T323
Test name
Test status
Simulation time 1071317800 ps
CPU time 12.52 seconds
Started Aug 10 05:03:10 PM PDT 24
Finished Aug 10 05:03:23 PM PDT 24
Peak memory 199776 kb
Host smart-2ca10117-5c00-4198-8c92-bb63e9def1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731244322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1731244322
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4273626899
Short name T185
Test name
Test status
Simulation time 153301717043 ps
CPU time 1244.43 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:24:20 PM PDT 24
Peak memory 704416 kb
Host smart-a8c8a37e-28c9-4dd9-8bc4-d2cccef4a5ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273626899 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4273626899
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1707785699
Short name T55
Test name
Test status
Simulation time 16789095691 ps
CPU time 48.45 seconds
Started Aug 10 05:03:20 PM PDT 24
Finished Aug 10 05:04:08 PM PDT 24
Peak memory 199884 kb
Host smart-82953577-98b8-4882-aa47-9c0848421f1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1707785699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1707785699
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.107356837
Short name T463
Test name
Test status
Simulation time 4463420404 ps
CPU time 65.3 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:04:25 PM PDT 24
Peak memory 199872 kb
Host smart-d3f91566-4036-4639-86ea-4f3e41eedb26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=107356837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.107356837
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.455226696
Short name T525
Test name
Test status
Simulation time 29848689735 ps
CPU time 137.81 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:05:54 PM PDT 24
Peak memory 199956 kb
Host smart-88e51d06-e58c-4de4-bb46-2a7dd1d1a03d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=455226696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.455226696
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1388300261
Short name T123
Test name
Test status
Simulation time 283791774451 ps
CPU time 590.61 seconds
Started Aug 10 05:03:09 PM PDT 24
Finished Aug 10 05:12:59 PM PDT 24
Peak memory 199832 kb
Host smart-b6162bc6-476f-493b-89e3-41dda956e35c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1388300261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1388300261
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1727184479
Short name T213
Test name
Test status
Simulation time 603046896700 ps
CPU time 2473.52 seconds
Started Aug 10 05:03:09 PM PDT 24
Finished Aug 10 05:44:23 PM PDT 24
Peak memory 215496 kb
Host smart-a240bf53-2d7b-4ada-ab2b-d4e895690109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1727184479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1727184479
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2604656473
Short name T227
Test name
Test status
Simulation time 567463597548 ps
CPU time 2398.56 seconds
Started Aug 10 05:03:09 PM PDT 24
Finished Aug 10 05:43:08 PM PDT 24
Peak memory 208052 kb
Host smart-31bf2f7a-104c-44a0-a01e-9cc10b4a0e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2604656473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2604656473
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.694424981
Short name T383
Test name
Test status
Simulation time 5813850778 ps
CPU time 105.69 seconds
Started Aug 10 05:03:07 PM PDT 24
Finished Aug 10 05:04:53 PM PDT 24
Peak memory 199860 kb
Host smart-5a012af2-ae04-4f55-897f-2de11f1f2adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694424981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.694424981
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3568608913
Short name T25
Test name
Test status
Simulation time 1736336454 ps
CPU time 50.19 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:04:28 PM PDT 24
Peak memory 199776 kb
Host smart-ccca6734-b3e8-4f7f-ac29-1108ca7992f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568608913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3568608913
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4284546381
Short name T330
Test name
Test status
Simulation time 3268465960 ps
CPU time 68.42 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:04:47 PM PDT 24
Peak memory 199432 kb
Host smart-772429aa-d0a9-463e-bcb3-356141b356e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284546381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4284546381
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2729034120
Short name T295
Test name
Test status
Simulation time 2477266674 ps
CPU time 475.36 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:11:30 PM PDT 24
Peak memory 491084 kb
Host smart-77ed8613-dac5-4953-af78-8411b1902c1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729034120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2729034120
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1985151588
Short name T349
Test name
Test status
Simulation time 49931079681 ps
CPU time 147.85 seconds
Started Aug 10 05:03:33 PM PDT 24
Finished Aug 10 05:06:01 PM PDT 24
Peak memory 199860 kb
Host smart-6e3657bd-b647-4074-9dbd-7b8f41ea458f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985151588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1985151588
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.132402833
Short name T507
Test name
Test status
Simulation time 2626539397 ps
CPU time 148.8 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:06:04 PM PDT 24
Peak memory 199792 kb
Host smart-cd6d215a-6b29-42b9-b4f4-488a14809efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132402833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.132402833
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.29879135
Short name T265
Test name
Test status
Simulation time 1322471021 ps
CPU time 11.33 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:03:46 PM PDT 24
Peak memory 199856 kb
Host smart-e89629f8-6402-4ede-a832-aca00798027d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29879135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.29879135
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.423510905
Short name T495
Test name
Test status
Simulation time 16720773748 ps
CPU time 299.53 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:08:35 PM PDT 24
Peak memory 288080 kb
Host smart-ede383cb-c228-43d4-b8db-58005d18058a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423510905 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.423510905
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.840056431
Short name T494
Test name
Test status
Simulation time 2587221807 ps
CPU time 124.06 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:05:40 PM PDT 24
Peak memory 199756 kb
Host smart-7067e5dd-4542-45f3-825b-5585b5dc0957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840056431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.840056431
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3959587291
Short name T49
Test name
Test status
Simulation time 44304415 ps
CPU time 0.6 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:03:36 PM PDT 24
Peak memory 195904 kb
Host smart-15067669-9c18-4914-9c27-0d6733700b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959587291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3959587291
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1417586018
Short name T236
Test name
Test status
Simulation time 409538023 ps
CPU time 11.94 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:49 PM PDT 24
Peak memory 199612 kb
Host smart-d7aa8b57-2755-4765-9c5d-b34aa45bdf3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417586018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1417586018
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3993760192
Short name T423
Test name
Test status
Simulation time 2901732092 ps
CPU time 36.68 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:04:14 PM PDT 24
Peak memory 199752 kb
Host smart-2d2a1eae-ed5e-44bd-a2c1-5c1db4392824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993760192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3993760192
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3140046636
Short name T122
Test name
Test status
Simulation time 20143310771 ps
CPU time 489.54 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:11:46 PM PDT 24
Peak memory 682216 kb
Host smart-c8c6f263-4991-4c93-8e3f-78288ecbba69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140046636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3140046636
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.79990971
Short name T203
Test name
Test status
Simulation time 33706839096 ps
CPU time 180.92 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:06:39 PM PDT 24
Peak memory 199732 kb
Host smart-ef37b3ec-9a58-41cd-b7ce-6d4db2d0aa3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79990971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.79990971
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2756119592
Short name T279
Test name
Test status
Simulation time 53525288711 ps
CPU time 162.12 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:06:22 PM PDT 24
Peak memory 208156 kb
Host smart-ec7ddd6b-4cd8-44d9-a554-58a7c39da80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756119592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2756119592
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1925947356
Short name T335
Test name
Test status
Simulation time 807202527 ps
CPU time 9.58 seconds
Started Aug 10 05:03:33 PM PDT 24
Finished Aug 10 05:03:43 PM PDT 24
Peak memory 199868 kb
Host smart-bd0103df-83b3-4a20-bfd0-83ae1c133d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925947356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1925947356
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1202401663
Short name T77
Test name
Test status
Simulation time 169743825028 ps
CPU time 4305.61 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 06:15:24 PM PDT 24
Peak memory 772160 kb
Host smart-53f2ba52-bf24-4b19-9b19-fdc92b7a42cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202401663 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1202401663
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2063189167
Short name T267
Test name
Test status
Simulation time 9482552344 ps
CPU time 59.56 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:04:35 PM PDT 24
Peak memory 199824 kb
Host smart-9350cc45-47c7-4a13-96eb-57e3a45ea026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063189167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2063189167
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.922374920
Short name T519
Test name
Test status
Simulation time 18773559 ps
CPU time 0.57 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:03:40 PM PDT 24
Peak memory 196620 kb
Host smart-74883003-319d-45db-836f-56cfc920b880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922374920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.922374920
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1344463435
Short name T412
Test name
Test status
Simulation time 895972740 ps
CPU time 46.34 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:04:24 PM PDT 24
Peak memory 199812 kb
Host smart-71f3887f-4d2d-4436-bdf5-91a6b1e43323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344463435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1344463435
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2302914568
Short name T468
Test name
Test status
Simulation time 3538976066 ps
CPU time 48.64 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:04:23 PM PDT 24
Peak memory 199876 kb
Host smart-1e4b3783-49bf-4255-a1f8-65f18e000e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302914568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2302914568
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2497114796
Short name T303
Test name
Test status
Simulation time 3278424005 ps
CPU time 695.17 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 738272 kb
Host smart-c54ab729-98f0-42ec-a286-14071c68dd88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497114796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2497114796
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3249673524
Short name T182
Test name
Test status
Simulation time 28170169730 ps
CPU time 232.64 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:07:32 PM PDT 24
Peak memory 199824 kb
Host smart-6ea6ac54-e6a6-400a-99f6-a0981cc7e795
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249673524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3249673524
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2014422388
Short name T220
Test name
Test status
Simulation time 29511587023 ps
CPU time 194.61 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:06:50 PM PDT 24
Peak memory 216228 kb
Host smart-81e82194-65d9-43dd-9400-6896080db45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014422388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2014422388
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2955972987
Short name T136
Test name
Test status
Simulation time 773094529 ps
CPU time 12.14 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:50 PM PDT 24
Peak memory 199792 kb
Host smart-4914eeef-3d08-4474-b123-abc3eeaa4c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955972987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2955972987
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.738248554
Short name T460
Test name
Test status
Simulation time 76208878251 ps
CPU time 2143.62 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:39:18 PM PDT 24
Peak memory 749796 kb
Host smart-99156750-7544-4eee-8abb-ca4f45ff8874
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738248554 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.738248554
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3882344992
Short name T440
Test name
Test status
Simulation time 1204244015 ps
CPU time 66.92 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:04:41 PM PDT 24
Peak memory 199904 kb
Host smart-b4c98c52-2cc4-40a9-a5bf-5e6fdfc6a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882344992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3882344992
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2555655905
Short name T191
Test name
Test status
Simulation time 12234206 ps
CPU time 0.62 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:38 PM PDT 24
Peak memory 195828 kb
Host smart-2d5e199e-9024-46ef-82e8-9a2d8ddf8660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555655905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2555655905
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.175129772
Short name T254
Test name
Test status
Simulation time 1714324137 ps
CPU time 53.16 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:04:31 PM PDT 24
Peak memory 199772 kb
Host smart-a99441dd-c9e3-47a3-948d-a00ef2e2d311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175129772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.175129772
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3157701687
Short name T317
Test name
Test status
Simulation time 4018615118 ps
CPU time 51.18 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:04:26 PM PDT 24
Peak memory 200012 kb
Host smart-530882a2-c1ac-406a-a0f8-e7d035ce7069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157701687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3157701687
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2381156352
Short name T324
Test name
Test status
Simulation time 6190920125 ps
CPU time 250.61 seconds
Started Aug 10 05:03:39 PM PDT 24
Finished Aug 10 05:07:50 PM PDT 24
Peak memory 458424 kb
Host smart-bef9b238-58bb-4915-9d04-9da05279b5b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381156352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2381156352
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.822434563
Short name T8
Test name
Test status
Simulation time 20670186534 ps
CPU time 90.35 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:05:08 PM PDT 24
Peak memory 199832 kb
Host smart-e9da64d3-ef84-4ee0-892b-c2495acffca5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822434563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.822434563
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1125146066
Short name T518
Test name
Test status
Simulation time 15988753635 ps
CPU time 146.27 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:06:01 PM PDT 24
Peak memory 199872 kb
Host smart-5352f4ed-5bb9-448c-adb7-4d03ba1bc7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125146066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1125146066
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.145149848
Short name T372
Test name
Test status
Simulation time 452290912 ps
CPU time 5.07 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:42 PM PDT 24
Peak memory 199764 kb
Host smart-9bce6fd2-a48c-4cf4-a6d1-8de52706b948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145149848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.145149848
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1233703449
Short name T257
Test name
Test status
Simulation time 37963163299 ps
CPU time 1430.65 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:27:29 PM PDT 24
Peak memory 716252 kb
Host smart-45034c76-fd0e-440e-b054-2076544d6143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233703449 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1233703449
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3819709474
Short name T199
Test name
Test status
Simulation time 11677567127 ps
CPU time 105.22 seconds
Started Aug 10 05:03:42 PM PDT 24
Finished Aug 10 05:05:27 PM PDT 24
Peak memory 199912 kb
Host smart-8dcb9706-59b1-4e85-b9f5-a19eeb489071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819709474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3819709474
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3281509180
Short name T379
Test name
Test status
Simulation time 10948903 ps
CPU time 0.57 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:03:39 PM PDT 24
Peak memory 194780 kb
Host smart-e181f3ef-9177-48cc-b504-3e2e4bdc10dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281509180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3281509180
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2252153609
Short name T29
Test name
Test status
Simulation time 10282169243 ps
CPU time 93.67 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:05:10 PM PDT 24
Peak memory 199756 kb
Host smart-36b40f65-d0a1-4de4-bcb9-293e6103bde4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252153609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2252153609
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.997862695
Short name T445
Test name
Test status
Simulation time 180265514 ps
CPU time 3.4 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:41 PM PDT 24
Peak memory 199904 kb
Host smart-ccc89e7a-7546-44ed-a89f-4b8f82bff6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997862695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.997862695
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.424114402
Short name T280
Test name
Test status
Simulation time 4191244978 ps
CPU time 133.28 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:05:52 PM PDT 24
Peak memory 437008 kb
Host smart-2b139142-e59b-4adb-bd8b-135b4fc54014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424114402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.424114402
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1046336368
Short name T263
Test name
Test status
Simulation time 6809456389 ps
CPU time 88.88 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:05:07 PM PDT 24
Peak memory 199940 kb
Host smart-3bd77528-f4ba-44c9-b21d-c1690076a5ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046336368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1046336368
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1550135660
Short name T285
Test name
Test status
Simulation time 8729979369 ps
CPU time 149.79 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:06:06 PM PDT 24
Peak memory 216212 kb
Host smart-886006d3-17dd-49fe-bf63-36ff36d86228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550135660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1550135660
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3945735948
Short name T353
Test name
Test status
Simulation time 15765808269 ps
CPU time 13.65 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:50 PM PDT 24
Peak memory 199940 kb
Host smart-025e2c87-15c2-457c-a13d-cbdc7f516cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945735948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3945735948
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3896369037
Short name T71
Test name
Test status
Simulation time 458452328325 ps
CPU time 3137.32 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:55:56 PM PDT 24
Peak memory 827884 kb
Host smart-7a59e7e9-ccee-45a1-b2c3-7192c7a22c17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896369037 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3896369037
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.629873040
Short name T222
Test name
Test status
Simulation time 17224925825 ps
CPU time 113.96 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:05:31 PM PDT 24
Peak memory 199808 kb
Host smart-f5690c86-f7dc-4f14-8bbf-0a92ca56d0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629873040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.629873040
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4287264998
Short name T215
Test name
Test status
Simulation time 13101821 ps
CPU time 0.58 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:03:41 PM PDT 24
Peak memory 195440 kb
Host smart-ebf7f0b0-5bbd-492b-8a0a-e165badea8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287264998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4287264998
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3137568038
Short name T189
Test name
Test status
Simulation time 54413831 ps
CPU time 3.18 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:03:42 PM PDT 24
Peak memory 199664 kb
Host smart-7cad03de-988b-4e93-851f-e3476f3b1900
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137568038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3137568038
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3605352631
Short name T17
Test name
Test status
Simulation time 4309583610 ps
CPU time 51.82 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:04:32 PM PDT 24
Peak memory 216332 kb
Host smart-1a806532-f0aa-4504-bce5-6b89645860e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605352631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3605352631
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3007411229
Short name T351
Test name
Test status
Simulation time 1173713697 ps
CPU time 32.13 seconds
Started Aug 10 05:03:39 PM PDT 24
Finished Aug 10 05:04:12 PM PDT 24
Peak memory 299336 kb
Host smart-dc6d65e8-540e-48e4-b6af-91498f0d0bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007411229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3007411229
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3433160944
Short name T133
Test name
Test status
Simulation time 2733758105 ps
CPU time 143.78 seconds
Started Aug 10 05:03:43 PM PDT 24
Finished Aug 10 05:06:06 PM PDT 24
Peak memory 199860 kb
Host smart-eebd5e9b-d4b1-4930-a343-e52036df6022
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433160944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3433160944
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.302359700
Short name T233
Test name
Test status
Simulation time 74130253958 ps
CPU time 122.1 seconds
Started Aug 10 05:03:39 PM PDT 24
Finished Aug 10 05:05:41 PM PDT 24
Peak memory 199748 kb
Host smart-ce93edad-c85a-400e-ba22-14b2cf1238fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302359700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.302359700
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2270104543
Short name T503
Test name
Test status
Simulation time 651185400 ps
CPU time 2.67 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:40 PM PDT 24
Peak memory 199828 kb
Host smart-a30d550e-72c3-4f9c-af54-9b47ab45273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270104543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2270104543
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.339707213
Short name T492
Test name
Test status
Simulation time 16588168984 ps
CPU time 604.51 seconds
Started Aug 10 05:03:43 PM PDT 24
Finished Aug 10 05:13:47 PM PDT 24
Peak memory 199792 kb
Host smart-5129ee43-091a-41e3-80bc-eb0562a9458e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339707213 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.339707213
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.817734640
Short name T195
Test name
Test status
Simulation time 6655821291 ps
CPU time 97.22 seconds
Started Aug 10 05:03:39 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 199824 kb
Host smart-cde844bc-516e-40df-b86b-61f082cf8c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817734640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.817734640
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2947998096
Short name T338
Test name
Test status
Simulation time 52682180 ps
CPU time 0.59 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:03:50 PM PDT 24
Peak memory 195532 kb
Host smart-2c76dd5a-9ebd-48cb-9d0d-3e8d7f017b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947998096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2947998096
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1459375238
Short name T132
Test name
Test status
Simulation time 14171254754 ps
CPU time 75.56 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:05:10 PM PDT 24
Peak memory 216328 kb
Host smart-516d696b-4ac5-4553-ab79-9edb64a04707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459375238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1459375238
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.19422388
Short name T319
Test name
Test status
Simulation time 944414937 ps
CPU time 18.08 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:07 PM PDT 24
Peak memory 199852 kb
Host smart-870736ac-fecc-4b81-9aa3-798bb46ddd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19422388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.19422388
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3771319656
Short name T438
Test name
Test status
Simulation time 21201210458 ps
CPU time 916.07 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:19:09 PM PDT 24
Peak memory 725440 kb
Host smart-a37d3290-b360-42b3-b6aa-a513009c4871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771319656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3771319656
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2763509008
Short name T192
Test name
Test status
Simulation time 512618207 ps
CPU time 27.38 seconds
Started Aug 10 05:03:46 PM PDT 24
Finished Aug 10 05:04:14 PM PDT 24
Peak memory 199692 kb
Host smart-84db0a6b-b86c-4fe0-be36-6d2f178ddadf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763509008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2763509008
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2584425931
Short name T282
Test name
Test status
Simulation time 12192724489 ps
CPU time 156.81 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:06:15 PM PDT 24
Peak memory 199780 kb
Host smart-ee8a7126-dd41-4bc2-bde0-a5f15b5d0887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584425931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2584425931
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.436938522
Short name T134
Test name
Test status
Simulation time 905947867 ps
CPU time 7.51 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:03:48 PM PDT 24
Peak memory 199780 kb
Host smart-5e167478-c6ca-4eed-b7d7-94e38c19ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436938522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.436938522
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2570751290
Short name T18
Test name
Test status
Simulation time 10858708846 ps
CPU time 779.24 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:16:54 PM PDT 24
Peak memory 713908 kb
Host smart-4abbf189-d2e2-4995-89a7-8878411e4e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570751290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2570751290
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3556248212
Short name T30
Test name
Test status
Simulation time 2745196319 ps
CPU time 9.9 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:04:01 PM PDT 24
Peak memory 199884 kb
Host smart-85ac2017-02c7-4daa-8312-494e90debaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556248212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3556248212
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3744631144
Short name T436
Test name
Test status
Simulation time 87023619 ps
CPU time 0.58 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:03:48 PM PDT 24
Peak memory 194792 kb
Host smart-ff70bcc5-7c93-4890-97d1-e7cbffbbbbe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744631144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3744631144
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.421374294
Short name T307
Test name
Test status
Simulation time 2701127292 ps
CPU time 66.72 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 199808 kb
Host smart-adf64091-f9b4-4bcb-b6b6-60a7f42b24bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421374294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.421374294
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1923789121
Short name T47
Test name
Test status
Simulation time 2456201865 ps
CPU time 47.95 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:36 PM PDT 24
Peak memory 199884 kb
Host smart-ee3dc715-144c-4ef9-8a48-84de84c07ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923789121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1923789121
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1243223080
Short name T331
Test name
Test status
Simulation time 40374078341 ps
CPU time 1197.67 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 744228 kb
Host smart-1a8942aa-768a-4755-9b97-14e7d34277d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243223080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1243223080
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2062216200
Short name T389
Test name
Test status
Simulation time 13474676261 ps
CPU time 92.95 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 200136 kb
Host smart-d8b83b40-179a-4dc7-a56d-59b1117b1e68
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062216200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2062216200
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.212784770
Short name T209
Test name
Test status
Simulation time 22123539917 ps
CPU time 57.63 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:04:51 PM PDT 24
Peak memory 216240 kb
Host smart-1f6877f6-2767-4781-b998-99fa1905e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212784770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.212784770
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2408297786
Short name T169
Test name
Test status
Simulation time 195829797 ps
CPU time 2.43 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:51 PM PDT 24
Peak memory 199780 kb
Host smart-0af9c502-af1c-45c4-8b6d-9a7da42a2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408297786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2408297786
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1408507228
Short name T229
Test name
Test status
Simulation time 1214582978 ps
CPU time 53.66 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:41 PM PDT 24
Peak memory 199752 kb
Host smart-f9c50945-11d5-48fe-b765-017e72a2c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408507228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1408507228
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.840490661
Short name T443
Test name
Test status
Simulation time 39983244 ps
CPU time 0.56 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 195492 kb
Host smart-2700a4f7-f929-4e1b-bea7-626d8b9281a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840490661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.840490661
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2736366268
Short name T381
Test name
Test status
Simulation time 432030810 ps
CPU time 24.89 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:04:14 PM PDT 24
Peak memory 199852 kb
Host smart-74f739b2-1c46-43ea-9c18-b2641a3c5eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736366268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2736366268
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1389192395
Short name T489
Test name
Test status
Simulation time 1671213870 ps
CPU time 5.08 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:03:52 PM PDT 24
Peak memory 199652 kb
Host smart-9b6a57d6-45e7-42a5-9e9f-9fb3a5571245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389192395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1389192395
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.544513225
Short name T256
Test name
Test status
Simulation time 33865711277 ps
CPU time 1912.88 seconds
Started Aug 10 05:03:46 PM PDT 24
Finished Aug 10 05:35:39 PM PDT 24
Peak memory 739300 kb
Host smart-a1563257-9cbe-4242-acf5-2c1bb677f11c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544513225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.544513225
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2110133557
Short name T16
Test name
Test status
Simulation time 4035556481 ps
CPU time 72.7 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:05:03 PM PDT 24
Peak memory 199772 kb
Host smart-d811be39-77a0-4be6-994e-c933d781defe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110133557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2110133557
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.322360592
Short name T151
Test name
Test status
Simulation time 11289620512 ps
CPU time 104.37 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:05:39 PM PDT 24
Peak memory 199956 kb
Host smart-c7c6e08c-5f11-4b78-b355-470d2fc27fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322360592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.322360592
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3769073193
Short name T450
Test name
Test status
Simulation time 634516608 ps
CPU time 12.34 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:00 PM PDT 24
Peak memory 199744 kb
Host smart-fdeb2a1d-0ec5-406e-a869-cc65627f0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769073193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3769073193
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.232332567
Short name T75
Test name
Test status
Simulation time 382479933264 ps
CPU time 2109.15 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:38:58 PM PDT 24
Peak memory 676224 kb
Host smart-11e1c8bf-8dd4-4f30-89b4-0b3926db4c29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232332567 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.232332567
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1514052556
Short name T84
Test name
Test status
Simulation time 3868795816 ps
CPU time 69.55 seconds
Started Aug 10 05:03:57 PM PDT 24
Finished Aug 10 05:05:06 PM PDT 24
Peak memory 199728 kb
Host smart-ac8c9e45-eeac-4bc0-b716-6f523cf68d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514052556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1514052556
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2921443461
Short name T493
Test name
Test status
Simulation time 49398762 ps
CPU time 0.58 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:03:55 PM PDT 24
Peak memory 194908 kb
Host smart-d0f61cac-0252-4b2f-89b0-8af145a5546f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921443461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2921443461
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2269765649
Short name T432
Test name
Test status
Simulation time 4266944527 ps
CPU time 62.61 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:51 PM PDT 24
Peak memory 199740 kb
Host smart-d261612e-b62e-481f-82d6-cd6de62370f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269765649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2269765649
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1137183478
Short name T469
Test name
Test status
Simulation time 1975365632 ps
CPU time 54.58 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:04:44 PM PDT 24
Peak memory 199856 kb
Host smart-647a0fd3-5b2b-4ec5-ad7a-5aa2f4ce51f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137183478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1137183478
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3587841450
Short name T68
Test name
Test status
Simulation time 14740166958 ps
CPU time 652.75 seconds
Started Aug 10 05:03:52 PM PDT 24
Finished Aug 10 05:14:45 PM PDT 24
Peak memory 522412 kb
Host smart-17d5e0c1-dfd8-4cd9-ab19-694fa63be5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587841450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3587841450
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.689518139
Short name T490
Test name
Test status
Simulation time 203136399 ps
CPU time 5.66 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:04:01 PM PDT 24
Peak memory 199580 kb
Host smart-1e19ed4a-d17f-4955-ba75-83593933a2cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689518139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.689518139
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1330732312
Short name T449
Test name
Test status
Simulation time 13782705613 ps
CPU time 109.94 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:05:39 PM PDT 24
Peak memory 199820 kb
Host smart-d6616055-ca57-4faa-aae6-2263073012c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330732312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1330732312
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.342973893
Short name T268
Test name
Test status
Simulation time 185874008 ps
CPU time 2.36 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:51 PM PDT 24
Peak memory 199768 kb
Host smart-28f4df6d-652f-4b6c-ab87-f344107ad50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342973893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.342973893
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2986203322
Short name T313
Test name
Test status
Simulation time 25590103007 ps
CPU time 1024.54 seconds
Started Aug 10 05:03:57 PM PDT 24
Finished Aug 10 05:21:02 PM PDT 24
Peak memory 678028 kb
Host smart-06582b7d-6124-49df-aedd-2042168499c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986203322 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2986203322
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3627385364
Short name T271
Test name
Test status
Simulation time 862087445 ps
CPU time 41.59 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:30 PM PDT 24
Peak memory 199740 kb
Host smart-69421260-bc1a-4f12-969b-a75c1e4fcb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627385364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3627385364
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.777752849
Short name T471
Test name
Test status
Simulation time 15034187 ps
CPU time 0.61 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:03:22 PM PDT 24
Peak memory 195828 kb
Host smart-bc902a7d-6ba5-416b-92fc-8fc482a93a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777752849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.777752849
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3672603558
Short name T27
Test name
Test status
Simulation time 6240267298 ps
CPU time 88.16 seconds
Started Aug 10 05:03:20 PM PDT 24
Finished Aug 10 05:04:48 PM PDT 24
Peak memory 199808 kb
Host smart-df1be060-bdc5-4644-b470-b726ef666a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672603558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3672603558
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3521061256
Short name T339
Test name
Test status
Simulation time 4937131918 ps
CPU time 65.21 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:04:25 PM PDT 24
Peak memory 199844 kb
Host smart-a0c7b351-d830-42f8-8367-c7da560c725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521061256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3521061256
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1720521145
Short name T168
Test name
Test status
Simulation time 15497308495 ps
CPU time 640.86 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:14:04 PM PDT 24
Peak memory 685132 kb
Host smart-f6b409dd-3efd-4022-81db-ccc842b60df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720521145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1720521145
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3961097477
Short name T172
Test name
Test status
Simulation time 779458398 ps
CPU time 40.96 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:04:00 PM PDT 24
Peak memory 199680 kb
Host smart-db56c9b1-f4bb-48c9-9ebc-976547fc6b64
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961097477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3961097477
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3953998574
Short name T508
Test name
Test status
Simulation time 3100833705 ps
CPU time 11.6 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:03:33 PM PDT 24
Peak memory 199976 kb
Host smart-60a8b9dd-57a7-4b7a-8a32-e56630e9a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953998574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3953998574
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3963809294
Short name T52
Test name
Test status
Simulation time 471812340 ps
CPU time 1 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:03:20 PM PDT 24
Peak memory 218484 kb
Host smart-3fd350e3-1176-4132-93ed-6078cb6a3764
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963809294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3963809294
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4041003643
Short name T228
Test name
Test status
Simulation time 77954133 ps
CPU time 3.13 seconds
Started Aug 10 05:03:16 PM PDT 24
Finished Aug 10 05:03:19 PM PDT 24
Peak memory 199736 kb
Host smart-22168fff-45e8-4fa2-ba9e-c3f1446bbcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041003643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4041003643
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4158706429
Short name T74
Test name
Test status
Simulation time 32298931151 ps
CPU time 387.16 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:10:03 PM PDT 24
Peak memory 199948 kb
Host smart-b0d6703a-47e2-4e71-b66e-7f596dbfce0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158706429 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4158706429
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3030872248
Short name T399
Test name
Test status
Simulation time 6396210841 ps
CPU time 66.69 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:04:30 PM PDT 24
Peak memory 199940 kb
Host smart-555a0d12-74bd-4ef9-be42-ee878eabd16a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3030872248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3030872248
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.20804230
Short name T520
Test name
Test status
Simulation time 26084082361 ps
CPU time 60.17 seconds
Started Aug 10 05:03:24 PM PDT 24
Finished Aug 10 05:04:24 PM PDT 24
Peak memory 199888 kb
Host smart-05fea5a5-5f87-4a88-b861-4bbb7e82bdfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=20804230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.20804230
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2398059554
Short name T205
Test name
Test status
Simulation time 4294183167 ps
CPU time 67.4 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:04:44 PM PDT 24
Peak memory 199896 kb
Host smart-d9e44751-1660-4e7b-bcf3-ef7aba422477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2398059554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2398059554
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.4158440944
Short name T477
Test name
Test status
Simulation time 48425196569 ps
CPU time 580.57 seconds
Started Aug 10 05:03:24 PM PDT 24
Finished Aug 10 05:13:04 PM PDT 24
Peak memory 199880 kb
Host smart-77090a39-e391-458f-82f5-5fa3bdcf690d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4158440944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.4158440944
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.770476597
Short name T170
Test name
Test status
Simulation time 159800795067 ps
CPU time 2341.05 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:42:24 PM PDT 24
Peak memory 215816 kb
Host smart-8ef5ad63-4858-430f-95d3-5570a7bd03ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=770476597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.770476597
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3743775732
Short name T147
Test name
Test status
Simulation time 298389704566 ps
CPU time 2554.55 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:45:54 PM PDT 24
Peak memory 216160 kb
Host smart-aed7f638-5350-4353-b79d-8cc84c2bdbc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3743775732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3743775732
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2220727901
Short name T251
Test name
Test status
Simulation time 5360703308 ps
CPU time 116.55 seconds
Started Aug 10 05:03:20 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 199940 kb
Host smart-1bcd54db-e220-4ce6-a27e-e3abc96485c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220727901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2220727901
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1110491150
Short name T336
Test name
Test status
Simulation time 12387485 ps
CPU time 0.58 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:03:50 PM PDT 24
Peak memory 194832 kb
Host smart-b45b2bfb-16c6-4dcc-b951-a871fa019c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110491150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1110491150
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4270413281
Short name T226
Test name
Test status
Simulation time 43420526 ps
CPU time 2.48 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:51 PM PDT 24
Peak memory 199708 kb
Host smart-4b9900fd-125e-480e-bf40-9809f06dd46b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270413281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4270413281
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.89252324
Short name T261
Test name
Test status
Simulation time 621296340 ps
CPU time 21.85 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:04:16 PM PDT 24
Peak memory 199844 kb
Host smart-c2b7056a-065b-496c-a928-f8b8218b03de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89252324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.89252324
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3640707721
Short name T393
Test name
Test status
Simulation time 7970788188 ps
CPU time 396.15 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:10:30 PM PDT 24
Peak memory 682440 kb
Host smart-e4115672-2366-47a3-8cbb-8ec8cea498e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640707721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3640707721
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3771718462
Short name T289
Test name
Test status
Simulation time 4092287553 ps
CPU time 180.01 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:06:48 PM PDT 24
Peak memory 199796 kb
Host smart-f6bd2b90-d877-4cae-a20b-f9633991af53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771718462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3771718462
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.136285471
Short name T242
Test name
Test status
Simulation time 18562517654 ps
CPU time 96.62 seconds
Started Aug 10 05:03:46 PM PDT 24
Finished Aug 10 05:05:23 PM PDT 24
Peak memory 199796 kb
Host smart-ea4847a7-90ca-40c4-931f-21fbbe420607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136285471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.136285471
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1389870187
Short name T184
Test name
Test status
Simulation time 112877633 ps
CPU time 5.91 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:03:53 PM PDT 24
Peak memory 199812 kb
Host smart-8b62f9a2-8d04-41d6-b216-d52a9504a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389870187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1389870187
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2500343442
Short name T310
Test name
Test status
Simulation time 25416375216 ps
CPU time 3688.28 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 06:05:23 PM PDT 24
Peak memory 802080 kb
Host smart-fee61be6-00a6-4a98-b012-bdbce0676058
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500343442 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2500343442
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4029787710
Short name T404
Test name
Test status
Simulation time 1510387454 ps
CPU time 62.56 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:04:51 PM PDT 24
Peak memory 199880 kb
Host smart-5f8fcec8-76e4-42e7-a84f-053c4255de8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029787710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4029787710
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3343272303
Short name T448
Test name
Test status
Simulation time 12171760 ps
CPU time 0.62 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:49 PM PDT 24
Peak memory 196452 kb
Host smart-29abab1c-bcbe-4fa9-8755-483e856fa62a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343272303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3343272303
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1296047261
Short name T249
Test name
Test status
Simulation time 5011623573 ps
CPU time 65.13 seconds
Started Aug 10 05:03:57 PM PDT 24
Finished Aug 10 05:05:02 PM PDT 24
Peak memory 199768 kb
Host smart-b323cc5b-aad6-40cb-9ba2-6b0d129b960b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296047261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1296047261
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2293591079
Short name T152
Test name
Test status
Simulation time 2829397870 ps
CPU time 30.99 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:04:18 PM PDT 24
Peak memory 199844 kb
Host smart-2581b997-5730-4cd5-aafe-92ebad7447cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293591079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2293591079
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2097755844
Short name T4
Test name
Test status
Simulation time 18557664340 ps
CPU time 859.51 seconds
Started Aug 10 05:03:46 PM PDT 24
Finished Aug 10 05:18:05 PM PDT 24
Peak memory 748644 kb
Host smart-1939c1f6-53aa-4275-ae34-cbe42d5999a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097755844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2097755844
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3228697016
Short name T419
Test name
Test status
Simulation time 15753724271 ps
CPU time 138.53 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:06:12 PM PDT 24
Peak memory 199904 kb
Host smart-36cc3a93-55a0-402c-befb-59348c408db3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228697016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3228697016
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1284443435
Short name T496
Test name
Test status
Simulation time 2520545878 ps
CPU time 43.31 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:04:33 PM PDT 24
Peak memory 199952 kb
Host smart-bad3c48f-5de9-4243-bddc-c0ec8475f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284443435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1284443435
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3645744066
Short name T420
Test name
Test status
Simulation time 1088791747 ps
CPU time 10.18 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:04:05 PM PDT 24
Peak memory 199724 kb
Host smart-a61dee9b-78d2-43d0-94a2-adb996abeafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645744066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3645744066
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.453716088
Short name T498
Test name
Test status
Simulation time 132018512454 ps
CPU time 2404.58 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:43:59 PM PDT 24
Peak memory 810748 kb
Host smart-d7e80dca-a8bb-4a77-93a4-fe0823fe89d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453716088 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.453716088
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.166056215
Short name T374
Test name
Test status
Simulation time 7663197536 ps
CPU time 140.5 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:06:09 PM PDT 24
Peak memory 199820 kb
Host smart-87c488f5-5a95-496e-92f7-e0cec63c07c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166056215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.166056215
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1878106272
Short name T329
Test name
Test status
Simulation time 74506729 ps
CPU time 0.57 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:03:51 PM PDT 24
Peak memory 194796 kb
Host smart-fccadcfc-af2a-4f1a-9f81-2cbdfae7a266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878106272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1878106272
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1745147203
Short name T486
Test name
Test status
Simulation time 3166108867 ps
CPU time 39.88 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:04:30 PM PDT 24
Peak memory 199828 kb
Host smart-d618d626-b27a-41a9-8643-3275e648015b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1745147203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1745147203
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2922962951
Short name T516
Test name
Test status
Simulation time 912330103 ps
CPU time 50.41 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:04:39 PM PDT 24
Peak memory 199836 kb
Host smart-d5e780f3-4fcc-4ba5-bd1d-a552656035e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922962951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2922962951
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.933673813
Short name T278
Test name
Test status
Simulation time 5655119148 ps
CPU time 1068.76 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:21:39 PM PDT 24
Peak memory 759128 kb
Host smart-06b483fd-db48-4e6f-9092-851870b63fce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933673813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.933673813
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3607150088
Short name T302
Test name
Test status
Simulation time 9824791091 ps
CPU time 130.03 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:06:00 PM PDT 24
Peak memory 199884 kb
Host smart-9b0e4243-a192-431c-8457-dbc762a6a407
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607150088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3607150088
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.502105339
Short name T480
Test name
Test status
Simulation time 16464793122 ps
CPU time 164.63 seconds
Started Aug 10 05:03:51 PM PDT 24
Finished Aug 10 05:06:36 PM PDT 24
Peak memory 216480 kb
Host smart-41f7b542-25b5-4fe9-b25b-525b56d0b4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502105339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.502105339
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.403792006
Short name T57
Test name
Test status
Simulation time 273376700 ps
CPU time 6.95 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:04:02 PM PDT 24
Peak memory 199840 kb
Host smart-7affaf5d-a559-4f88-9657-6e526daf81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403792006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.403792006
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1495083537
Short name T340
Test name
Test status
Simulation time 30073582714 ps
CPU time 265.36 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:08:16 PM PDT 24
Peak memory 200568 kb
Host smart-3ef105d2-422b-4d1f-9036-0595659c388b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495083537 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1495083537
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.828695256
Short name T408
Test name
Test status
Simulation time 1057073752 ps
CPU time 5.69 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 199904 kb
Host smart-e9ac132f-c926-41f4-9f54-712ee4fa10c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828695256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.828695256
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3480045633
Short name T150
Test name
Test status
Simulation time 12958447 ps
CPU time 0.59 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:03:56 PM PDT 24
Peak memory 195932 kb
Host smart-f879918d-8a04-4d0e-8b3c-f58bc0e0bdff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480045633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3480045633
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1094092531
Short name T31
Test name
Test status
Simulation time 965332235 ps
CPU time 54.76 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:04:48 PM PDT 24
Peak memory 199848 kb
Host smart-8ec60436-eb2a-41ba-87c9-b95619ce033e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094092531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1094092531
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2729565394
Short name T218
Test name
Test status
Simulation time 933255170 ps
CPU time 9.54 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:04:04 PM PDT 24
Peak memory 199888 kb
Host smart-11d4d93b-d535-4091-be26-7ef61905f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729565394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2729565394
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2671633411
Short name T217
Test name
Test status
Simulation time 2525078282 ps
CPU time 372.11 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:10:06 PM PDT 24
Peak memory 659188 kb
Host smart-1aa38f38-b56d-401a-b150-e2da0b1423fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671633411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2671633411
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3190707825
Short name T292
Test name
Test status
Simulation time 21981782 ps
CPU time 0.68 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 196264 kb
Host smart-9b3a78ef-a0c8-4e9a-838f-de0a4b28e38b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190707825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3190707825
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2729267166
Short name T425
Test name
Test status
Simulation time 1124821609 ps
CPU time 29.14 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:04:19 PM PDT 24
Peak memory 199720 kb
Host smart-f6daad89-100e-43d8-9b1f-8d6e6e2e8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729267166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2729267166
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3435723050
Short name T54
Test name
Test status
Simulation time 2713258573 ps
CPU time 11.78 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:04:05 PM PDT 24
Peak memory 199952 kb
Host smart-15151dea-37e7-4234-8989-15b8d650c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435723050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3435723050
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1146706175
Short name T239
Test name
Test status
Simulation time 283172639256 ps
CPU time 1178.63 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:23:32 PM PDT 24
Peak memory 631440 kb
Host smart-199a0475-2ce4-49e4-86f4-52453743f5ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146706175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1146706175
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2824099840
Short name T318
Test name
Test status
Simulation time 7579355908 ps
CPU time 103.08 seconds
Started Aug 10 05:03:52 PM PDT 24
Finished Aug 10 05:05:35 PM PDT 24
Peak memory 200072 kb
Host smart-432a75ab-0ea1-4520-aa82-0db2e2af84a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824099840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2824099840
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2633021907
Short name T183
Test name
Test status
Simulation time 12033777 ps
CPU time 0.64 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 195780 kb
Host smart-5f6ab546-40c4-476a-a316-f57ba1a35b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633021907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2633021907
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2675170381
Short name T523
Test name
Test status
Simulation time 1033831372 ps
CPU time 15.2 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:04:02 PM PDT 24
Peak memory 199744 kb
Host smart-fef8926c-2ead-46b7-a8c9-87c8c55fcae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675170381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2675170381
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3235550617
Short name T343
Test name
Test status
Simulation time 1714010041 ps
CPU time 22.59 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:04:17 PM PDT 24
Peak memory 199752 kb
Host smart-8affa7f3-132e-434c-9dfa-f954153dcaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235550617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3235550617
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2154049734
Short name T446
Test name
Test status
Simulation time 506978681 ps
CPU time 105.78 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:05:40 PM PDT 24
Peak memory 569692 kb
Host smart-acbe4a3a-e57a-428f-a4b0-ca42dad33f0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154049734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2154049734
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2973381873
Short name T359
Test name
Test status
Simulation time 20232438050 ps
CPU time 185.84 seconds
Started Aug 10 05:03:47 PM PDT 24
Finished Aug 10 05:06:53 PM PDT 24
Peak memory 199916 kb
Host smart-0ea7a429-2f00-4099-b227-b6dab1867aae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973381873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2973381873
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3013422451
Short name T479
Test name
Test status
Simulation time 11274682372 ps
CPU time 47.48 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:04:43 PM PDT 24
Peak memory 199908 kb
Host smart-7ceb12fd-943e-494b-aedf-04014731bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013422451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3013422451
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1816254656
Short name T219
Test name
Test status
Simulation time 974127347 ps
CPU time 9.41 seconds
Started Aug 10 05:03:51 PM PDT 24
Finished Aug 10 05:04:00 PM PDT 24
Peak memory 200000 kb
Host smart-350bc7ce-8420-4fd8-af86-0f5336c5927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816254656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1816254656
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2622045925
Short name T248
Test name
Test status
Simulation time 5699669717 ps
CPU time 80.48 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 208176 kb
Host smart-99dfb1ec-861f-4ef7-896d-be43c54078b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622045925 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2622045925
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3661397909
Short name T380
Test name
Test status
Simulation time 515821313 ps
CPU time 9.58 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:04:03 PM PDT 24
Peak memory 199852 kb
Host smart-5f5a39b8-16eb-43ff-be12-464566677636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661397909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3661397909
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4137992827
Short name T46
Test name
Test status
Simulation time 89759756 ps
CPU time 0.6 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 195816 kb
Host smart-19b0a088-7a5a-4699-821d-603554febb09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137992827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4137992827
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.245531792
Short name T13
Test name
Test status
Simulation time 1497655057 ps
CPU time 85.59 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:05:20 PM PDT 24
Peak memory 199788 kb
Host smart-190d57f3-ad32-4afb-8be6-9ae97b5ec5d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245531792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.245531792
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2971162142
Short name T447
Test name
Test status
Simulation time 31190319 ps
CPU time 0.87 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:49 PM PDT 24
Peak memory 198448 kb
Host smart-eac27cbe-e6e9-4b27-bc10-398d3f019ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971162142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2971162142
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.586254986
Short name T441
Test name
Test status
Simulation time 5246835607 ps
CPU time 1047.2 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:21:21 PM PDT 24
Peak memory 699424 kb
Host smart-930dc1ce-861b-4d64-8d11-c66f0869d8d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586254986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.586254986
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3812524669
Short name T444
Test name
Test status
Simulation time 1169521060 ps
CPU time 64.65 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:04:59 PM PDT 24
Peak memory 199732 kb
Host smart-31920cc3-18dc-4973-bce8-b554eeb8cb3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812524669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3812524669
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2826469587
Short name T290
Test name
Test status
Simulation time 307992804 ps
CPU time 4.9 seconds
Started Aug 10 05:03:48 PM PDT 24
Finished Aug 10 05:03:53 PM PDT 24
Peak memory 199728 kb
Host smart-ed44fa40-85f7-48fd-9ba8-f94a12ae10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826469587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2826469587
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2193072707
Short name T467
Test name
Test status
Simulation time 587980476 ps
CPU time 7.29 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:03:57 PM PDT 24
Peak memory 199776 kb
Host smart-551eafbc-5a7d-4e0b-9027-b0c8ef520cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193072707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2193072707
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2669927696
Short name T48
Test name
Test status
Simulation time 2320365260 ps
CPU time 59.37 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 316432 kb
Host smart-163049c4-a86a-4039-9534-1d3e2650f9f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669927696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2669927696
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2238991922
Short name T321
Test name
Test status
Simulation time 6331682952 ps
CPU time 60.28 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:04:51 PM PDT 24
Peak memory 199740 kb
Host smart-73bbabc9-34d9-4a13-b128-c8d9aaf270c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238991922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2238991922
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1067810196
Short name T512
Test name
Test status
Simulation time 21781753 ps
CPU time 0.61 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:03:50 PM PDT 24
Peak memory 195564 kb
Host smart-a7677e04-cdf1-4d13-8cc4-aeccb91bcfcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067810196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1067810196
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1651744545
Short name T373
Test name
Test status
Simulation time 882042924 ps
CPU time 17.13 seconds
Started Aug 10 05:03:56 PM PDT 24
Finished Aug 10 05:04:13 PM PDT 24
Peak memory 199728 kb
Host smart-5716eb7f-d822-4596-9da6-7feab4d71ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651744545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1651744545
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3282720893
Short name T316
Test name
Test status
Simulation time 24780406109 ps
CPU time 647.12 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:14:37 PM PDT 24
Peak memory 671592 kb
Host smart-54e2f88d-fe70-4a1f-9078-24059192e447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282720893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3282720893
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.244376180
Short name T161
Test name
Test status
Simulation time 41117751343 ps
CPU time 132.14 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:06:02 PM PDT 24
Peak memory 199932 kb
Host smart-c109eb0e-a8c4-4440-b445-d2d8b828cf8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244376180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.244376180
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2301057944
Short name T358
Test name
Test status
Simulation time 12361648803 ps
CPU time 158.89 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:06:32 PM PDT 24
Peak memory 199876 kb
Host smart-78f28bb3-26d5-4818-8cbe-1caa02d5dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301057944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2301057944
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1656656355
Short name T34
Test name
Test status
Simulation time 60078317 ps
CPU time 1.56 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 199668 kb
Host smart-54bca358-adfd-4a0d-b9a0-7324618cda0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656656355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1656656355
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1681708294
Short name T234
Test name
Test status
Simulation time 165821058312 ps
CPU time 1021.46 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:20:55 PM PDT 24
Peak memory 662468 kb
Host smart-982c79a9-692e-4fe8-9878-d033abae822d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681708294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1681708294
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3056457464
Short name T153
Test name
Test status
Simulation time 4043825805 ps
CPU time 18 seconds
Started Aug 10 05:03:56 PM PDT 24
Finished Aug 10 05:04:14 PM PDT 24
Peak memory 199800 kb
Host smart-2109428c-745d-4bf6-a8f1-f713ef8632e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056457464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3056457464
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3644081247
Short name T506
Test name
Test status
Simulation time 36170623 ps
CPU time 0.56 seconds
Started Aug 10 05:04:07 PM PDT 24
Finished Aug 10 05:04:07 PM PDT 24
Peak memory 195856 kb
Host smart-15e9ffe9-84be-4494-a894-34382dedb37a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644081247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3644081247
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2818901679
Short name T363
Test name
Test status
Simulation time 1376972274 ps
CPU time 75.43 seconds
Started Aug 10 05:03:51 PM PDT 24
Finished Aug 10 05:05:07 PM PDT 24
Peak memory 199716 kb
Host smart-6d95154c-1e16-4cdf-be45-5bef932fdc92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818901679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2818901679
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3568652424
Short name T208
Test name
Test status
Simulation time 13987680431 ps
CPU time 46.47 seconds
Started Aug 10 05:03:54 PM PDT 24
Finished Aug 10 05:04:41 PM PDT 24
Peak memory 199868 kb
Host smart-c88903dd-1d34-48a8-a480-b34f987430a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568652424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3568652424
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.563458179
Short name T378
Test name
Test status
Simulation time 4507668633 ps
CPU time 202.03 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:07:11 PM PDT 24
Peak memory 450292 kb
Host smart-27caad36-7904-4b67-bff5-eb168dcf12fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563458179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.563458179
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4102931097
Short name T240
Test name
Test status
Simulation time 4507269572 ps
CPU time 64.8 seconds
Started Aug 10 05:03:53 PM PDT 24
Finished Aug 10 05:04:57 PM PDT 24
Peak memory 199848 kb
Host smart-4126a1fb-d293-4afa-8a0c-f177d21a4c49
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102931097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4102931097
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1906922709
Short name T111
Test name
Test status
Simulation time 4811830283 ps
CPU time 38.41 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:04:28 PM PDT 24
Peak memory 199844 kb
Host smart-c018f050-93f2-453e-9725-61230dace7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906922709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1906922709
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1069016060
Short name T320
Test name
Test status
Simulation time 20688274 ps
CPU time 1.16 seconds
Started Aug 10 05:03:49 PM PDT 24
Finished Aug 10 05:03:50 PM PDT 24
Peak memory 199720 kb
Host smart-1147d4b5-28c4-406d-b87f-230e908539d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069016060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1069016060
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2132311882
Short name T390
Test name
Test status
Simulation time 216976224072 ps
CPU time 1624.26 seconds
Started Aug 10 05:04:07 PM PDT 24
Finished Aug 10 05:31:12 PM PDT 24
Peak memory 695748 kb
Host smart-68f5d621-f86d-432a-8524-7765b6cb6bd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132311882 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2132311882
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4234792477
Short name T89
Test name
Test status
Simulation time 11275045113 ps
CPU time 153.18 seconds
Started Aug 10 05:03:50 PM PDT 24
Finished Aug 10 05:06:24 PM PDT 24
Peak memory 199784 kb
Host smart-bfb8f3be-b2c8-490b-95de-7b86c82a11a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234792477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4234792477
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2214174871
Short name T509
Test name
Test status
Simulation time 13345741 ps
CPU time 0.58 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:04:10 PM PDT 24
Peak memory 196472 kb
Host smart-f2195860-8a1c-44bf-8a65-c5308113f0fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214174871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2214174871
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2737290628
Short name T309
Test name
Test status
Simulation time 3874885707 ps
CPU time 56.05 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:05:05 PM PDT 24
Peak memory 199732 kb
Host smart-958141a7-6a2e-4b7d-ad7e-c6af6a021988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737290628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2737290628
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3379765627
Short name T126
Test name
Test status
Simulation time 719881642 ps
CPU time 37.88 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:04:43 PM PDT 24
Peak memory 199768 kb
Host smart-e33e3eec-9004-45bb-88e8-112f6713445d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379765627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3379765627
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1803961739
Short name T259
Test name
Test status
Simulation time 4879551150 ps
CPU time 861.11 seconds
Started Aug 10 05:03:55 PM PDT 24
Finished Aug 10 05:18:17 PM PDT 24
Peak memory 693256 kb
Host smart-f35d9b04-834b-4518-a737-f1838772071a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803961739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1803961739
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1838027296
Short name T426
Test name
Test status
Simulation time 2101747799 ps
CPU time 17.46 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:04:23 PM PDT 24
Peak memory 199788 kb
Host smart-c2c3c9b2-5e47-451b-ad95-a6cd4e12fa63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838027296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1838027296
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2717856259
Short name T342
Test name
Test status
Simulation time 4544808132 ps
CPU time 80.57 seconds
Started Aug 10 05:04:06 PM PDT 24
Finished Aug 10 05:05:27 PM PDT 24
Peak memory 199892 kb
Host smart-620d0985-c386-4f23-bcf6-f6f40169ddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717856259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2717856259
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2287609753
Short name T186
Test name
Test status
Simulation time 1292053554 ps
CPU time 4.2 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:04:10 PM PDT 24
Peak memory 199836 kb
Host smart-cb79e604-e37a-4186-b36b-70df7d976ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287609753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2287609753
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3671550683
Short name T485
Test name
Test status
Simulation time 212407593 ps
CPU time 11.96 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:04:20 PM PDT 24
Peak memory 199864 kb
Host smart-5e75e5ef-b4ef-47ab-bf74-cb8f5f8b617c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671550683 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3671550683
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.670263222
Short name T283
Test name
Test status
Simulation time 18925582640 ps
CPU time 71.79 seconds
Started Aug 10 05:03:56 PM PDT 24
Finished Aug 10 05:05:07 PM PDT 24
Peak memory 199860 kb
Host smart-b1331628-8ef3-49bc-8d58-65d42f929967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670263222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.670263222
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3742549169
Short name T405
Test name
Test status
Simulation time 96183212 ps
CPU time 0.66 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:04:09 PM PDT 24
Peak memory 196636 kb
Host smart-821b74be-0f65-4b2d-9113-9585ab30c5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742549169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3742549169
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.931409246
Short name T296
Test name
Test status
Simulation time 718375432 ps
CPU time 41.03 seconds
Started Aug 10 05:04:03 PM PDT 24
Finished Aug 10 05:04:44 PM PDT 24
Peak memory 199708 kb
Host smart-84ec44a3-48f7-4c11-b8b7-4fe27ebb7e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931409246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.931409246
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3613283524
Short name T294
Test name
Test status
Simulation time 1578555652 ps
CPU time 28.76 seconds
Started Aug 10 05:03:58 PM PDT 24
Finished Aug 10 05:04:27 PM PDT 24
Peak memory 199880 kb
Host smart-6963d2f5-a9ac-41cc-bd67-71c9064ba571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613283524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3613283524
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.81353277
Short name T478
Test name
Test status
Simulation time 5472146521 ps
CPU time 1008.74 seconds
Started Aug 10 05:03:57 PM PDT 24
Finished Aug 10 05:20:46 PM PDT 24
Peak memory 732616 kb
Host smart-e776bcc7-448c-4afa-b2ad-3d480ed6d291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81353277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.81353277
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3715796081
Short name T19
Test name
Test status
Simulation time 5274296922 ps
CPU time 138.21 seconds
Started Aug 10 05:03:57 PM PDT 24
Finished Aug 10 05:06:16 PM PDT 24
Peak memory 199924 kb
Host smart-726a8c17-db31-463c-b05a-8cf92b67c84d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715796081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3715796081
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2536021964
Short name T394
Test name
Test status
Simulation time 13998833873 ps
CPU time 151.35 seconds
Started Aug 10 05:04:04 PM PDT 24
Finished Aug 10 05:06:36 PM PDT 24
Peak memory 199888 kb
Host smart-92bdee05-349d-4105-bc5c-bade726a179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536021964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2536021964
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1078384797
Short name T501
Test name
Test status
Simulation time 219279473 ps
CPU time 11.17 seconds
Started Aug 10 05:03:56 PM PDT 24
Finished Aug 10 05:04:07 PM PDT 24
Peak memory 199764 kb
Host smart-fbf4a273-a9ee-4975-811b-6e3fc39de2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078384797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1078384797
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1110110317
Short name T72
Test name
Test status
Simulation time 76816062972 ps
CPU time 1040.99 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:21:29 PM PDT 24
Peak memory 246112 kb
Host smart-d08bcfd2-c248-4ef4-bc11-31adccded894
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110110317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1110110317
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3897712268
Short name T362
Test name
Test status
Simulation time 2249003096 ps
CPU time 105.29 seconds
Started Aug 10 05:04:04 PM PDT 24
Finished Aug 10 05:05:50 PM PDT 24
Peak memory 199824 kb
Host smart-e2fcc2aa-030a-49fa-81dc-8d2291b7213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897712268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3897712268
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3321540525
Short name T515
Test name
Test status
Simulation time 38570883 ps
CPU time 0.6 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 196612 kb
Host smart-3db746db-76da-41e6-9d96-c2158b732e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321540525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3321540525
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3594496656
Short name T475
Test name
Test status
Simulation time 738219738 ps
CPU time 45.3 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:04:07 PM PDT 24
Peak memory 199788 kb
Host smart-4f9e578c-8c1b-4d72-982a-d851440c5118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594496656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3594496656
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3713643368
Short name T502
Test name
Test status
Simulation time 998114824 ps
CPU time 55.14 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:04:19 PM PDT 24
Peak memory 199912 kb
Host smart-4a8db7bb-0302-47d8-88c5-d22454ffb1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713643368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3713643368
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3903457088
Short name T452
Test name
Test status
Simulation time 6499247558 ps
CPU time 1324.8 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:25:41 PM PDT 24
Peak memory 758536 kb
Host smart-1b794816-dfd2-4a54-819a-9e86048f3977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903457088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3903457088
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2670271842
Short name T371
Test name
Test status
Simulation time 7009551805 ps
CPU time 84.52 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:04:46 PM PDT 24
Peak memory 199796 kb
Host smart-e440c7eb-01e9-46f8-b19d-c28fa25cf8e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670271842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2670271842
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3588820301
Short name T232
Test name
Test status
Simulation time 145444749320 ps
CPU time 131.95 seconds
Started Aug 10 05:03:18 PM PDT 24
Finished Aug 10 05:05:30 PM PDT 24
Peak memory 199980 kb
Host smart-3e423e02-5c83-473c-8edb-39a61e3a389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588820301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3588820301
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3322940071
Short name T51
Test name
Test status
Simulation time 81955830 ps
CPU time 1.1 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:03:25 PM PDT 24
Peak memory 219628 kb
Host smart-7095b530-529f-476c-8209-a22f1c8fc322
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322940071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3322940071
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3569713784
Short name T311
Test name
Test status
Simulation time 1938056170 ps
CPU time 12.07 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:03:32 PM PDT 24
Peak memory 199744 kb
Host smart-e2c0240a-294a-4e59-bc04-a84156ebcb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569713784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3569713784
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3296812882
Short name T28
Test name
Test status
Simulation time 103551629908 ps
CPU time 3617.85 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 06:03:39 PM PDT 24
Peak memory 837668 kb
Host smart-141ac890-2b18-419c-8db6-ba1fe1c5857b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296812882 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3296812882
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.149358702
Short name T10
Test name
Test status
Simulation time 28674746278 ps
CPU time 341.92 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:09:05 PM PDT 24
Peak memory 363296 kb
Host smart-63bf455b-efb5-4d68-b145-abc3b355967a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149358702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.149358702
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1341313026
Short name T429
Test name
Test status
Simulation time 1607046925 ps
CPU time 66.5 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:04:29 PM PDT 24
Peak memory 199816 kb
Host smart-6203987d-9234-47b3-b250-8853dc78eefc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1341313026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1341313026
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.113673750
Short name T281
Test name
Test status
Simulation time 7305109929 ps
CPU time 60.2 seconds
Started Aug 10 05:03:18 PM PDT 24
Finished Aug 10 05:04:19 PM PDT 24
Peak memory 199812 kb
Host smart-a70ba8c5-56df-4e46-bd35-ccd489ff1ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=113673750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.113673750
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.204554948
Short name T301
Test name
Test status
Simulation time 2059017019 ps
CPU time 66.74 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:04:26 PM PDT 24
Peak memory 199756 kb
Host smart-b3f4eb5b-4014-4853-b712-d453f22bbc2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=204554948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.204554948
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.4148477613
Short name T149
Test name
Test status
Simulation time 70365385211 ps
CPU time 595.26 seconds
Started Aug 10 05:03:20 PM PDT 24
Finished Aug 10 05:13:15 PM PDT 24
Peak memory 199796 kb
Host smart-0c252d3d-28cb-4878-aea5-24e3c742bd9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4148477613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.4148477613
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2058072372
Short name T163
Test name
Test status
Simulation time 86020229532 ps
CPU time 2289.66 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:41:29 PM PDT 24
Peak memory 215792 kb
Host smart-3f91627a-f0c7-483e-8972-2245093bb796
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2058072372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2058072372
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1388811734
Short name T58
Test name
Test status
Simulation time 137830508551 ps
CPU time 2308.14 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:41:47 PM PDT 24
Peak memory 216136 kb
Host smart-e8efb7da-8a5a-4e6f-9974-e57375eceb74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1388811734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1388811734
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1699024251
Short name T146
Test name
Test status
Simulation time 8037774892 ps
CPU time 31.96 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:03:54 PM PDT 24
Peak memory 199788 kb
Host smart-30072879-f139-4877-89ed-6303d382cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699024251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1699024251
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3139246875
Short name T181
Test name
Test status
Simulation time 43992211 ps
CPU time 0.59 seconds
Started Aug 10 05:03:58 PM PDT 24
Finished Aug 10 05:03:58 PM PDT 24
Peak memory 195896 kb
Host smart-15642454-149d-43a9-9f72-92e27efb2a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139246875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3139246875
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.874388038
Short name T164
Test name
Test status
Simulation time 2449391106 ps
CPU time 71.97 seconds
Started Aug 10 05:04:06 PM PDT 24
Finished Aug 10 05:05:18 PM PDT 24
Peak memory 199808 kb
Host smart-d4af7c98-cc6f-4227-8e5a-ea49746b12d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874388038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.874388038
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1270278563
Short name T325
Test name
Test status
Simulation time 4884271962 ps
CPU time 50.54 seconds
Started Aug 10 05:04:07 PM PDT 24
Finished Aug 10 05:04:58 PM PDT 24
Peak memory 199896 kb
Host smart-4e15cfc1-5817-42c7-aabc-7dad8a487a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270278563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1270278563
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4159322643
Short name T269
Test name
Test status
Simulation time 1449745209 ps
CPU time 262.1 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:08:27 PM PDT 24
Peak memory 662884 kb
Host smart-d4a42087-4dcd-4d6a-ad9b-eebf37e87e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159322643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4159322643
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.464011284
Short name T360
Test name
Test status
Simulation time 20206842699 ps
CPU time 171.41 seconds
Started Aug 10 05:04:00 PM PDT 24
Finished Aug 10 05:06:51 PM PDT 24
Peak memory 199756 kb
Host smart-f03bcd74-84be-417a-9c95-daf997f198e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464011284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.464011284
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3048837665
Short name T167
Test name
Test status
Simulation time 8180789958 ps
CPU time 120.12 seconds
Started Aug 10 05:04:01 PM PDT 24
Finished Aug 10 05:06:01 PM PDT 24
Peak memory 199848 kb
Host smart-4b072004-f470-48f0-829f-f26f89b33960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048837665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3048837665
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2427656778
Short name T387
Test name
Test status
Simulation time 75307062 ps
CPU time 3.92 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:04:12 PM PDT 24
Peak memory 199844 kb
Host smart-8711db47-fe9e-4208-8806-3a711c4624ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427656778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2427656778
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.941190268
Short name T78
Test name
Test status
Simulation time 434501536982 ps
CPU time 1602.36 seconds
Started Aug 10 05:04:00 PM PDT 24
Finished Aug 10 05:30:42 PM PDT 24
Peak memory 643716 kb
Host smart-8a54b379-b0ba-4512-b575-dc3ba34f9bf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941190268 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.941190268
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.932104699
Short name T87
Test name
Test status
Simulation time 29599158629 ps
CPU time 102.97 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:05:51 PM PDT 24
Peak memory 199948 kb
Host smart-a05ad623-e8c7-459a-a51d-93f394f9b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932104699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.932104699
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2332082693
Short name T513
Test name
Test status
Simulation time 15161282 ps
CPU time 0.57 seconds
Started Aug 10 05:03:58 PM PDT 24
Finished Aug 10 05:03:58 PM PDT 24
Peak memory 195920 kb
Host smart-6a2835f7-1c34-4fa6-8f6c-b8369d6ee8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332082693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2332082693
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1853038596
Short name T482
Test name
Test status
Simulation time 2049841308 ps
CPU time 17.31 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:04:27 PM PDT 24
Peak memory 199756 kb
Host smart-21c03be3-d3fe-4aef-ae65-766856e4a88f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853038596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1853038596
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.530534086
Short name T277
Test name
Test status
Simulation time 836197186 ps
CPU time 45.68 seconds
Started Aug 10 05:04:06 PM PDT 24
Finished Aug 10 05:04:52 PM PDT 24
Peak memory 199772 kb
Host smart-388fea6e-a01b-45f1-8147-a370eaae0042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530534086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.530534086
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2985943632
Short name T266
Test name
Test status
Simulation time 17832683190 ps
CPU time 645.09 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:14:56 PM PDT 24
Peak memory 516140 kb
Host smart-04b832e4-9ccd-4180-a01c-e1db134ad211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985943632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2985943632
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3741006447
Short name T456
Test name
Test status
Simulation time 28527683584 ps
CPU time 76.53 seconds
Started Aug 10 05:04:07 PM PDT 24
Finished Aug 10 05:05:23 PM PDT 24
Peak memory 199800 kb
Host smart-391c280f-ab01-43e2-842e-dc723426d9ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741006447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3741006447
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2906766627
Short name T179
Test name
Test status
Simulation time 2154875088 ps
CPU time 106.08 seconds
Started Aug 10 05:03:57 PM PDT 24
Finished Aug 10 05:05:43 PM PDT 24
Peak memory 199800 kb
Host smart-16938f62-7cd5-4b37-a433-7b4f74af1da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906766627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2906766627
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2085848544
Short name T386
Test name
Test status
Simulation time 8795074131 ps
CPU time 7.49 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:04:13 PM PDT 24
Peak memory 199868 kb
Host smart-371c04dd-5dfc-4d9b-8ae8-39e67ac3a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085848544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2085848544
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.219600210
Short name T434
Test name
Test status
Simulation time 14819084994 ps
CPU time 48.26 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:04:58 PM PDT 24
Peak memory 199744 kb
Host smart-8c4cd673-443e-4a34-90d8-03dc65915aa1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219600210 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.219600210
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3271476551
Short name T369
Test name
Test status
Simulation time 9475162020 ps
CPU time 120.54 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:06:11 PM PDT 24
Peak memory 199764 kb
Host smart-2c45fcb1-f3e8-42a0-b004-bd99f20ca83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271476551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3271476551
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2793812037
Short name T177
Test name
Test status
Simulation time 29430349 ps
CPU time 0.57 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:04:09 PM PDT 24
Peak memory 195608 kb
Host smart-9611c3a5-a3d1-4369-87e2-60028f8aa2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793812037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2793812037
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2208399045
Short name T160
Test name
Test status
Simulation time 4812040666 ps
CPU time 70.42 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:05:21 PM PDT 24
Peak memory 199720 kb
Host smart-8dc7c425-4bc3-4116-a99a-7b55d58b6f80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208399045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2208399045
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.145607580
Short name T297
Test name
Test status
Simulation time 5305393181 ps
CPU time 66.45 seconds
Started Aug 10 05:04:06 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 199868 kb
Host smart-f5d0e3f2-0874-464a-9427-25c7025d5167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145607580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.145607580
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1567607536
Short name T141
Test name
Test status
Simulation time 24042689278 ps
CPU time 1077.17 seconds
Started Aug 10 05:03:58 PM PDT 24
Finished Aug 10 05:21:55 PM PDT 24
Peak memory 696952 kb
Host smart-89707452-2784-4282-b996-f0119957d9b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567607536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1567607536
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1652640952
Short name T26
Test name
Test status
Simulation time 5124018481 ps
CPU time 69.44 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:05:18 PM PDT 24
Peak memory 199876 kb
Host smart-86e685ee-a50a-48f2-850e-8d7f2739f2cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652640952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1652640952
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.16774544
Short name T260
Test name
Test status
Simulation time 7654891215 ps
CPU time 169.98 seconds
Started Aug 10 05:04:04 PM PDT 24
Finished Aug 10 05:06:54 PM PDT 24
Peak memory 199744 kb
Host smart-71ad664d-dcb3-4f78-bf7d-a2446d2194a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16774544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.16774544
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3226812937
Short name T322
Test name
Test status
Simulation time 1391299245 ps
CPU time 11.48 seconds
Started Aug 10 05:04:02 PM PDT 24
Finished Aug 10 05:04:13 PM PDT 24
Peak memory 199844 kb
Host smart-30ab7e8a-8ea1-4f36-ba50-aed37bd6b0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226812937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3226812937
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.259264302
Short name T76
Test name
Test status
Simulation time 742872907376 ps
CPU time 670.74 seconds
Started Aug 10 05:04:07 PM PDT 24
Finished Aug 10 05:15:18 PM PDT 24
Peak memory 216236 kb
Host smart-678b6cf4-d34b-4236-a781-4c4d8c9a9ad3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259264302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.259264302
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1960974340
Short name T7
Test name
Test status
Simulation time 13116267721 ps
CPU time 83.25 seconds
Started Aug 10 05:04:01 PM PDT 24
Finished Aug 10 05:05:25 PM PDT 24
Peak memory 199888 kb
Host smart-0fd19023-a7b8-4c6d-b110-ac85238fd48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960974340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1960974340
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4151787482
Short name T3
Test name
Test status
Simulation time 21902861 ps
CPU time 0.59 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:04:10 PM PDT 24
Peak memory 194952 kb
Host smart-71bf50cd-4e4d-4b60-b06c-3308ef9d0d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151787482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4151787482
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4267925205
Short name T14
Test name
Test status
Simulation time 2674522236 ps
CPU time 49.02 seconds
Started Aug 10 05:04:04 PM PDT 24
Finished Aug 10 05:04:53 PM PDT 24
Peak memory 199820 kb
Host smart-686f2969-8f63-4820-810a-475cedab60e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267925205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4267925205
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2261224220
Short name T210
Test name
Test status
Simulation time 12041259337 ps
CPU time 49.06 seconds
Started Aug 10 05:03:59 PM PDT 24
Finished Aug 10 05:04:48 PM PDT 24
Peak memory 199988 kb
Host smart-bd257115-4b37-480b-8735-4d41aba8b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261224220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2261224220
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1545281637
Short name T366
Test name
Test status
Simulation time 4326148325 ps
CPU time 626.32 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:14:32 PM PDT 24
Peak memory 710240 kb
Host smart-36a267c3-f820-4917-8737-14839636cc16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545281637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1545281637
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1330949607
Short name T142
Test name
Test status
Simulation time 4230090397 ps
CPU time 79.04 seconds
Started Aug 10 05:03:58 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 199936 kb
Host smart-92f8bff7-ab53-40f4-89c9-2dd449f93554
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330949607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1330949607
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2028549420
Short name T407
Test name
Test status
Simulation time 1715659759 ps
CPU time 14.88 seconds
Started Aug 10 05:03:59 PM PDT 24
Finished Aug 10 05:04:14 PM PDT 24
Peak memory 199700 kb
Host smart-d8f2d0e8-c6f6-4319-b1c1-b3c068965070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028549420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2028549420
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3551675907
Short name T253
Test name
Test status
Simulation time 403469926 ps
CPU time 4.6 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:04:15 PM PDT 24
Peak memory 199684 kb
Host smart-a624fa21-d1a4-46a4-b2a9-f9c9aa85000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551675907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3551675907
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2349546172
Short name T88
Test name
Test status
Simulation time 220188034518 ps
CPU time 5341.45 seconds
Started Aug 10 05:04:00 PM PDT 24
Finished Aug 10 06:33:02 PM PDT 24
Peak memory 824204 kb
Host smart-515ffeda-0be6-45cc-b05f-b3d12810799a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349546172 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2349546172
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3790195534
Short name T410
Test name
Test status
Simulation time 874942453 ps
CPU time 35.72 seconds
Started Aug 10 05:04:05 PM PDT 24
Finished Aug 10 05:04:41 PM PDT 24
Peak memory 199800 kb
Host smart-13337132-f011-4ae0-b9b9-e6957acf52d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790195534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3790195534
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3305667168
Short name T286
Test name
Test status
Simulation time 52826440 ps
CPU time 0.6 seconds
Started Aug 10 05:04:15 PM PDT 24
Finished Aug 10 05:04:16 PM PDT 24
Peak memory 195772 kb
Host smart-a6f5975b-ab3f-4acf-9cf5-621ae636b6ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305667168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3305667168
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.621811083
Short name T499
Test name
Test status
Simulation time 2633616882 ps
CPU time 80.05 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:05:31 PM PDT 24
Peak memory 199816 kb
Host smart-79ed9855-0a44-4801-bdb0-72e301fc1f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621811083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.621811083
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3543499685
Short name T416
Test name
Test status
Simulation time 2070131022 ps
CPU time 26.86 seconds
Started Aug 10 05:04:11 PM PDT 24
Finished Aug 10 05:04:38 PM PDT 24
Peak memory 199948 kb
Host smart-018987e2-1d18-465b-8c73-30576f343922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543499685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3543499685
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1394383718
Short name T148
Test name
Test status
Simulation time 204420834 ps
CPU time 20.15 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:04:30 PM PDT 24
Peak memory 241144 kb
Host smart-9733a80e-a569-4be2-86c5-cf99b5485986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394383718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1394383718
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1245652525
Short name T138
Test name
Test status
Simulation time 31297818029 ps
CPU time 107.55 seconds
Started Aug 10 05:04:15 PM PDT 24
Finished Aug 10 05:06:03 PM PDT 24
Peak memory 199740 kb
Host smart-a747f98e-4206-4e5b-8e1a-901e56c15789
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245652525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1245652525
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.885753096
Short name T385
Test name
Test status
Simulation time 12980439100 ps
CPU time 78.28 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:05:28 PM PDT 24
Peak memory 199788 kb
Host smart-4f7118d0-a088-4cc8-9a52-970edc0143cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885753096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.885753096
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2501974059
Short name T382
Test name
Test status
Simulation time 1167641578 ps
CPU time 5.2 seconds
Started Aug 10 05:04:08 PM PDT 24
Finished Aug 10 05:04:14 PM PDT 24
Peak memory 199720 kb
Host smart-0ef32478-d48b-4b14-b5c9-197db1897a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501974059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2501974059
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3843851747
Short name T173
Test name
Test status
Simulation time 4050322559 ps
CPU time 92.96 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:05:42 PM PDT 24
Peak memory 199816 kb
Host smart-70607c4e-f0d7-4515-9ba9-eb478312160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843851747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3843851747
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1534866221
Short name T144
Test name
Test status
Simulation time 108142175 ps
CPU time 0.58 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:04:26 PM PDT 24
Peak memory 196544 kb
Host smart-3b4e4fbb-c044-4406-8e29-8c53bd1ddaaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534866221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1534866221
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2068599170
Short name T32
Test name
Test status
Simulation time 818279656 ps
CPU time 47.38 seconds
Started Aug 10 05:04:13 PM PDT 24
Finished Aug 10 05:05:00 PM PDT 24
Peak memory 199760 kb
Host smart-792b5930-25d1-4e4c-a1f3-f5477067669e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068599170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2068599170
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3597457959
Short name T225
Test name
Test status
Simulation time 2202784128 ps
CPU time 31.8 seconds
Started Aug 10 05:04:10 PM PDT 24
Finished Aug 10 05:04:42 PM PDT 24
Peak memory 199888 kb
Host smart-962774cb-f5c6-44ac-8df8-996b75173c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597457959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3597457959
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3418306267
Short name T510
Test name
Test status
Simulation time 1344352138 ps
CPU time 203.01 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:07:32 PM PDT 24
Peak memory 400840 kb
Host smart-51910a36-7411-4fca-bdcc-54689bb8659c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418306267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3418306267
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3430518790
Short name T198
Test name
Test status
Simulation time 2498234609 ps
CPU time 149.16 seconds
Started Aug 10 05:04:12 PM PDT 24
Finished Aug 10 05:06:41 PM PDT 24
Peak memory 199892 kb
Host smart-e39dee4a-5ee4-44d3-9382-53a3ffdf1d1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430518790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3430518790
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3716264286
Short name T250
Test name
Test status
Simulation time 447226176 ps
CPU time 23.71 seconds
Started Aug 10 05:04:14 PM PDT 24
Finished Aug 10 05:04:38 PM PDT 24
Peak memory 199792 kb
Host smart-266c4a1f-0891-4b45-b11d-a5a2b514b98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716264286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3716264286
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3705109930
Short name T155
Test name
Test status
Simulation time 935145379 ps
CPU time 9.78 seconds
Started Aug 10 05:04:09 PM PDT 24
Finished Aug 10 05:04:19 PM PDT 24
Peak memory 199708 kb
Host smart-cbfbf972-c417-4a1c-b212-fcb0a31a458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705109930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3705109930
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.454227868
Short name T272
Test name
Test status
Simulation time 17384561185 ps
CPU time 1270.51 seconds
Started Aug 10 05:04:30 PM PDT 24
Finished Aug 10 05:25:41 PM PDT 24
Peak memory 514672 kb
Host smart-ab364e4c-aad0-4118-aaa2-24dc65a2a7fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454227868 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.454227868
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1731347722
Short name T1
Test name
Test status
Simulation time 15786729612 ps
CPU time 105.19 seconds
Started Aug 10 05:04:24 PM PDT 24
Finished Aug 10 05:06:10 PM PDT 24
Peak memory 199932 kb
Host smart-9a44af12-bc2e-43e7-a87f-ff3379ea5518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731347722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1731347722
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2286654343
Short name T344
Test name
Test status
Simulation time 40051497 ps
CPU time 0.6 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:04:26 PM PDT 24
Peak memory 195832 kb
Host smart-99262b7f-9f09-48bd-93f7-4a6efcc18c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286654343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2286654343
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2130817679
Short name T396
Test name
Test status
Simulation time 876410099 ps
CPU time 51.84 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:05:19 PM PDT 24
Peak memory 200032 kb
Host smart-8b149f5d-d08f-4fc8-948d-5b351e698151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130817679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2130817679
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1933460638
Short name T521
Test name
Test status
Simulation time 16563529568 ps
CPU time 33.5 seconds
Started Aug 10 05:04:33 PM PDT 24
Finished Aug 10 05:05:06 PM PDT 24
Peak memory 199952 kb
Host smart-f6b5bded-5f81-4929-ae2e-3e5e75c59349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933460638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1933460638
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3666652886
Short name T442
Test name
Test status
Simulation time 3407199539 ps
CPU time 562.41 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:13:49 PM PDT 24
Peak memory 674632 kb
Host smart-23f4e456-ad98-4961-8488-4c87fb35c7d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666652886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3666652886
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1754622426
Short name T137
Test name
Test status
Simulation time 16645833721 ps
CPU time 181.27 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:07:29 PM PDT 24
Peak memory 199928 kb
Host smart-4a9ce03f-4fd9-440f-bd26-a1a380d19a21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754622426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1754622426
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3533531122
Short name T230
Test name
Test status
Simulation time 482539223 ps
CPU time 5.39 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:04:31 PM PDT 24
Peak memory 199712 kb
Host smart-61650128-63e6-4dde-8d4c-2e46df5f153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533531122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3533531122
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.210928509
Short name T465
Test name
Test status
Simulation time 1221601227 ps
CPU time 14.83 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:04:42 PM PDT 24
Peak memory 199836 kb
Host smart-278e8310-4cf3-486f-b7b3-5e1786a2ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210928509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.210928509
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2295939875
Short name T483
Test name
Test status
Simulation time 102445789560 ps
CPU time 2167.79 seconds
Started Aug 10 05:04:28 PM PDT 24
Finished Aug 10 05:40:36 PM PDT 24
Peak memory 773552 kb
Host smart-1183d3b5-da38-456c-bf80-5ec7d0ec5701
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295939875 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2295939875
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.107771760
Short name T435
Test name
Test status
Simulation time 6188437841 ps
CPU time 72.51 seconds
Started Aug 10 05:04:26 PM PDT 24
Finished Aug 10 05:05:39 PM PDT 24
Peak memory 199764 kb
Host smart-77216eaf-0bc2-4c9d-843f-a351fe0a0373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107771760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.107771760
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2947418496
Short name T216
Test name
Test status
Simulation time 21340305 ps
CPU time 0.59 seconds
Started Aug 10 05:04:28 PM PDT 24
Finished Aug 10 05:04:28 PM PDT 24
Peak memory 195948 kb
Host smart-e144bf17-87e2-41a9-80e9-01c08fc2b31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947418496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2947418496
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.873765427
Short name T224
Test name
Test status
Simulation time 271253816 ps
CPU time 15.49 seconds
Started Aug 10 05:04:24 PM PDT 24
Finished Aug 10 05:04:40 PM PDT 24
Peak memory 199840 kb
Host smart-b62605c0-fdf7-4f87-ae35-45cab80b0e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873765427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.873765427
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2507133566
Short name T127
Test name
Test status
Simulation time 4148761472 ps
CPU time 59.12 seconds
Started Aug 10 05:04:28 PM PDT 24
Finished Aug 10 05:05:27 PM PDT 24
Peak memory 199836 kb
Host smart-3ba12900-31c6-4899-b280-97cea69506e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507133566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2507133566
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4225211165
Short name T223
Test name
Test status
Simulation time 9078652615 ps
CPU time 859.02 seconds
Started Aug 10 05:04:26 PM PDT 24
Finished Aug 10 05:18:45 PM PDT 24
Peak memory 722936 kb
Host smart-1ebd27b2-2c94-4366-b96a-adc0cb88d371
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225211165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4225211165
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.902275482
Short name T454
Test name
Test status
Simulation time 2592947480 ps
CPU time 144.81 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:06:52 PM PDT 24
Peak memory 199856 kb
Host smart-993794b8-345c-40aa-be4e-93e3eda4e976
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902275482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.902275482
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3509507834
Short name T421
Test name
Test status
Simulation time 35054259499 ps
CPU time 152.98 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:07:01 PM PDT 24
Peak memory 216120 kb
Host smart-81159b5a-1412-44af-b923-818eb9058549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509507834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3509507834
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.825307364
Short name T488
Test name
Test status
Simulation time 589539037 ps
CPU time 8.12 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:04:33 PM PDT 24
Peak memory 199736 kb
Host smart-049d7fe5-1748-4e47-9d7f-fbefb2a0bdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825307364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.825307364
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1287747536
Short name T129
Test name
Test status
Simulation time 19252589699 ps
CPU time 1668.33 seconds
Started Aug 10 05:04:24 PM PDT 24
Finished Aug 10 05:32:13 PM PDT 24
Peak memory 749380 kb
Host smart-9cbfa5e6-8648-483a-9d99-e6f4fe57b76f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287747536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1287747536
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2229462520
Short name T304
Test name
Test status
Simulation time 94055387770 ps
CPU time 106.22 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:06:11 PM PDT 24
Peak memory 199892 kb
Host smart-8fa9dca4-5ea8-4fde-9c61-7730158cea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229462520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2229462520
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.501259355
Short name T459
Test name
Test status
Simulation time 65508956 ps
CPU time 0.65 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:04:27 PM PDT 24
Peak memory 195984 kb
Host smart-c036c2bf-0867-44b5-bbae-5cfbb236b78a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501259355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.501259355
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3807486905
Short name T33
Test name
Test status
Simulation time 5586013231 ps
CPU time 75.2 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:05:43 PM PDT 24
Peak memory 216148 kb
Host smart-904d092b-8d2e-4085-83b6-e7ba06f2cfc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807486905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3807486905
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3677845712
Short name T350
Test name
Test status
Simulation time 1981282573 ps
CPU time 6.16 seconds
Started Aug 10 05:04:26 PM PDT 24
Finished Aug 10 05:04:33 PM PDT 24
Peak memory 199852 kb
Host smart-fc1d1585-1e18-4c02-a428-21b5bfa72568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677845712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3677845712
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1799001382
Short name T255
Test name
Test status
Simulation time 3827758395 ps
CPU time 728.46 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:16:33 PM PDT 24
Peak memory 499040 kb
Host smart-280e5ba2-45dc-4aad-b33b-f5afad3e9761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799001382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1799001382
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1151132426
Short name T461
Test name
Test status
Simulation time 47246718 ps
CPU time 1.17 seconds
Started Aug 10 05:04:26 PM PDT 24
Finished Aug 10 05:04:27 PM PDT 24
Peak memory 199372 kb
Host smart-ce346ccb-ccf3-4127-a31e-4e07f4bcdbaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151132426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1151132426
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2440400381
Short name T39
Test name
Test status
Simulation time 4573124359 ps
CPU time 125.28 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:06:32 PM PDT 24
Peak memory 199972 kb
Host smart-1a8d9916-6485-44e5-b20f-50cf056d089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440400381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2440400381
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.414768457
Short name T176
Test name
Test status
Simulation time 980619333 ps
CPU time 4.24 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:04:32 PM PDT 24
Peak memory 199852 kb
Host smart-2ea6991c-e82c-4a1c-8d93-7aee9b037d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414768457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.414768457
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3549384663
Short name T128
Test name
Test status
Simulation time 22648909710 ps
CPU time 2033.24 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:38:20 PM PDT 24
Peak memory 799652 kb
Host smart-0c98a345-d99a-45ed-9509-aaaea95ab8a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549384663 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3549384663
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3632483033
Short name T300
Test name
Test status
Simulation time 8120385375 ps
CPU time 100.56 seconds
Started Aug 10 05:04:27 PM PDT 24
Finished Aug 10 05:06:08 PM PDT 24
Peak memory 200088 kb
Host smart-c02ff8a2-b682-49ba-975d-d48dc8d4e3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632483033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3632483033
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.640775278
Short name T231
Test name
Test status
Simulation time 11676734 ps
CPU time 0.62 seconds
Started Aug 10 05:04:41 PM PDT 24
Finished Aug 10 05:04:42 PM PDT 24
Peak memory 196480 kb
Host smart-5130ee70-baa1-4176-bfed-d1d60fc8ce13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640775278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.640775278
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2720784907
Short name T178
Test name
Test status
Simulation time 4294824998 ps
CPU time 61 seconds
Started Aug 10 05:04:23 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 199816 kb
Host smart-0279d26d-235b-433c-908e-a5d3dc0d0456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720784907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2720784907
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.27468825
Short name T23
Test name
Test status
Simulation time 12431938922 ps
CPU time 47.72 seconds
Started Aug 10 05:04:42 PM PDT 24
Finished Aug 10 05:05:30 PM PDT 24
Peak memory 199800 kb
Host smart-a9469b28-8f02-49e4-bf0d-d43d08358eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27468825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.27468825
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2019823406
Short name T418
Test name
Test status
Simulation time 6246800746 ps
CPU time 230.5 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:08:16 PM PDT 24
Peak memory 594880 kb
Host smart-5110b100-e76b-4e31-b518-240a74af5053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019823406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2019823406
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3997891049
Short name T56
Test name
Test status
Simulation time 188027685 ps
CPU time 1.32 seconds
Started Aug 10 05:04:42 PM PDT 24
Finished Aug 10 05:04:44 PM PDT 24
Peak memory 199680 kb
Host smart-88479a60-4aa4-4bc8-99fd-a6b465866244
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997891049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3997891049
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3536489239
Short name T424
Test name
Test status
Simulation time 4566699026 ps
CPU time 123.78 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:06:29 PM PDT 24
Peak memory 199892 kb
Host smart-e0a156f3-219d-488a-a460-5e431a3fa583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536489239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3536489239
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2463489727
Short name T247
Test name
Test status
Simulation time 1328839267 ps
CPU time 8.41 seconds
Started Aug 10 05:04:25 PM PDT 24
Finished Aug 10 05:04:34 PM PDT 24
Peak memory 199776 kb
Host smart-e9552a58-9e3f-4101-83b1-4e25adee5220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463489727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2463489727
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3646313254
Short name T524
Test name
Test status
Simulation time 135986359482 ps
CPU time 1574.48 seconds
Started Aug 10 05:04:45 PM PDT 24
Finished Aug 10 05:31:00 PM PDT 24
Peak memory 727408 kb
Host smart-818f14f4-db58-4c47-b2ba-1e69ee79c206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646313254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3646313254
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.323538324
Short name T79
Test name
Test status
Simulation time 31086225309 ps
CPU time 133.16 seconds
Started Aug 10 05:04:45 PM PDT 24
Finished Aug 10 05:06:58 PM PDT 24
Peak memory 199824 kb
Host smart-c3f07d75-c246-4946-b2e9-da9d43bb42ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323538324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.323538324
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2484457
Short name T245
Test name
Test status
Simulation time 44922934 ps
CPU time 0.58 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 195924 kb
Host smart-77c10036-6cbd-44f1-8279-1d401a166099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2484457
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4271552918
Short name T131
Test name
Test status
Simulation time 974898813 ps
CPU time 58.96 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:04:21 PM PDT 24
Peak memory 199724 kb
Host smart-4b304cd7-d824-4835-8b85-68d790358187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271552918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4271552918
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.762811909
Short name T143
Test name
Test status
Simulation time 3401986843 ps
CPU time 64.35 seconds
Started Aug 10 05:03:20 PM PDT 24
Finished Aug 10 05:04:25 PM PDT 24
Peak memory 199768 kb
Host smart-19d409df-53a0-460d-ae82-6fdb6d3c9a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762811909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.762811909
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1980775893
Short name T414
Test name
Test status
Simulation time 657715072 ps
CPU time 116.62 seconds
Started Aug 10 05:03:20 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 580784 kb
Host smart-28305538-fad8-4249-92e0-0a86744b583b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980775893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1980775893
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2072258702
Short name T491
Test name
Test status
Simulation time 498492813 ps
CPU time 26.16 seconds
Started Aug 10 05:03:17 PM PDT 24
Finished Aug 10 05:03:44 PM PDT 24
Peak memory 199692 kb
Host smart-d2dbaaee-5cd0-4588-8023-223757a9da51
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072258702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2072258702
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.165657046
Short name T135
Test name
Test status
Simulation time 4953764189 ps
CPU time 136.44 seconds
Started Aug 10 05:03:18 PM PDT 24
Finished Aug 10 05:05:35 PM PDT 24
Peak memory 199936 kb
Host smart-f5c06af0-05ea-4315-8093-68c33913a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165657046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.165657046
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3659988665
Short name T53
Test name
Test status
Simulation time 95974171 ps
CPU time 1.04 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:03:23 PM PDT 24
Peak memory 219400 kb
Host smart-6249801f-538f-4253-a287-a03dd7036705
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659988665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3659988665
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.104246299
Short name T80
Test name
Test status
Simulation time 5082253652 ps
CPU time 13.12 seconds
Started Aug 10 05:03:23 PM PDT 24
Finished Aug 10 05:03:36 PM PDT 24
Peak memory 199796 kb
Host smart-321c5c2e-8e42-4374-826f-1f1c59281920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104246299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.104246299
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3265446611
Short name T377
Test name
Test status
Simulation time 87452399925 ps
CPU time 2030.45 seconds
Started Aug 10 05:03:19 PM PDT 24
Finished Aug 10 05:37:10 PM PDT 24
Peak memory 768560 kb
Host smart-925ad363-5a4f-4cee-a333-8f69f49fe2ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265446611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3265446611
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2412170758
Short name T60
Test name
Test status
Simulation time 405669543621 ps
CPU time 4748.1 seconds
Started Aug 10 05:03:24 PM PDT 24
Finished Aug 10 06:22:32 PM PDT 24
Peak memory 842984 kb
Host smart-6cf7613c-c796-41b6-b1f3-e4f532342966
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412170758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2412170758
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3965580230
Short name T212
Test name
Test status
Simulation time 25839587584 ps
CPU time 76.99 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:04:38 PM PDT 24
Peak memory 199924 kb
Host smart-a24b4e26-2702-4a81-922b-a9dc7588cbd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3965580230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3965580230
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3979438453
Short name T397
Test name
Test status
Simulation time 27175089396 ps
CPU time 103.39 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:05:04 PM PDT 24
Peak memory 199744 kb
Host smart-1a148959-ead3-4eee-bb7f-14bfd88c4980
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3979438453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3979438453
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1667835385
Short name T375
Test name
Test status
Simulation time 5097729107 ps
CPU time 73.27 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:04:34 PM PDT 24
Peak memory 199908 kb
Host smart-985e3617-7565-41e0-80fe-fee7c3e3044c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1667835385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1667835385
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1625026217
Short name T162
Test name
Test status
Simulation time 72636823234 ps
CPU time 624.88 seconds
Started Aug 10 05:03:16 PM PDT 24
Finished Aug 10 05:13:42 PM PDT 24
Peak memory 199744 kb
Host smart-3c9447d2-42df-4adb-840b-1c85addd1272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1625026217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1625026217
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3381904326
Short name T121
Test name
Test status
Simulation time 132043989060 ps
CPU time 2301.18 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:41:57 PM PDT 24
Peak memory 215544 kb
Host smart-772a79b9-f7e4-48df-b338-bbb75fc7aca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3381904326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3381904326
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2011745932
Short name T288
Test name
Test status
Simulation time 40721332461 ps
CPU time 2385.49 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:43:07 PM PDT 24
Peak memory 215248 kb
Host smart-1ea6969c-7420-4488-b280-af588963e595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2011745932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2011745932
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1806996718
Short name T355
Test name
Test status
Simulation time 1249688524 ps
CPU time 38.4 seconds
Started Aug 10 05:03:22 PM PDT 24
Finished Aug 10 05:04:01 PM PDT 24
Peak memory 199720 kb
Host smart-4c3d70d0-ebe8-40bc-a506-02121370eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806996718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1806996718
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3383579015
Short name T221
Test name
Test status
Simulation time 12441917 ps
CPU time 0.59 seconds
Started Aug 10 05:04:45 PM PDT 24
Finished Aug 10 05:04:46 PM PDT 24
Peak memory 195784 kb
Host smart-c801a3bf-c40c-4bc8-a9a4-4ad313a1c1fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383579015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3383579015
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2145184128
Short name T332
Test name
Test status
Simulation time 2290336764 ps
CPU time 34.72 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:05:19 PM PDT 24
Peak memory 199868 kb
Host smart-e249c8fe-d6e7-4fac-9b35-aaf9f7e84327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145184128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2145184128
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.816495272
Short name T417
Test name
Test status
Simulation time 3649189494 ps
CPU time 46.64 seconds
Started Aug 10 05:04:43 PM PDT 24
Finished Aug 10 05:05:30 PM PDT 24
Peak memory 199772 kb
Host smart-2123193c-9afd-4440-991e-d83e5c689eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816495272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.816495272
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1020418409
Short name T244
Test name
Test status
Simulation time 14534746591 ps
CPU time 1277.09 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:26:04 PM PDT 24
Peak memory 736216 kb
Host smart-302c2f19-a92e-41b4-bb64-28f4c7c947db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020418409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1020418409
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1005094105
Short name T38
Test name
Test status
Simulation time 24900858654 ps
CPU time 103.7 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:06:28 PM PDT 24
Peak memory 199812 kb
Host smart-37480c44-dd32-426e-9680-7550e54d6f05
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005094105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1005094105
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2278084840
Short name T40
Test name
Test status
Simulation time 2175176925 ps
CPU time 67.25 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:05:51 PM PDT 24
Peak memory 200072 kb
Host smart-c773a20d-27c3-467b-b3f4-6f090c0fb1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278084840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2278084840
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1469174724
Short name T35
Test name
Test status
Simulation time 36712991 ps
CPU time 1.11 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:04:45 PM PDT 24
Peak memory 199592 kb
Host smart-c7c26309-4b3d-477a-9715-aa944ccbe3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469174724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1469174724
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4108346087
Short name T484
Test name
Test status
Simulation time 45395027846 ps
CPU time 582.11 seconds
Started Aug 10 05:04:43 PM PDT 24
Finished Aug 10 05:14:25 PM PDT 24
Peak memory 199816 kb
Host smart-3130368c-2db5-4de1-bcf6-091f0f523725
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108346087 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4108346087
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.945822919
Short name T165
Test name
Test status
Simulation time 872966706 ps
CPU time 13.12 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:04:58 PM PDT 24
Peak memory 199724 kb
Host smart-ba1aa953-4852-4a2e-ace4-0d10c9104363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945822919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.945822919
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.520872598
Short name T139
Test name
Test status
Simulation time 13899085 ps
CPU time 0.57 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:04:46 PM PDT 24
Peak memory 194816 kb
Host smart-38f57e86-bf9e-48d1-a4f9-86304cc069d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520872598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.520872598
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3003444716
Short name T409
Test name
Test status
Simulation time 4096908471 ps
CPU time 30.03 seconds
Started Aug 10 05:04:45 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 199860 kb
Host smart-4530e56e-9a7a-4be1-b2cf-5a9d424df311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003444716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3003444716
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2358000405
Short name T315
Test name
Test status
Simulation time 5496239271 ps
CPU time 16.93 seconds
Started Aug 10 05:04:43 PM PDT 24
Finished Aug 10 05:05:01 PM PDT 24
Peak memory 199824 kb
Host smart-66e7126d-f5e4-4cab-9299-29fe184ec154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358000405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2358000405
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.969892379
Short name T264
Test name
Test status
Simulation time 8813370327 ps
CPU time 788.44 seconds
Started Aug 10 05:04:47 PM PDT 24
Finished Aug 10 05:17:55 PM PDT 24
Peak memory 733248 kb
Host smart-1eeb3dea-1904-4642-a3ef-824993a0ee3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969892379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.969892379
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1284930437
Short name T306
Test name
Test status
Simulation time 6945053789 ps
CPU time 93.95 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:06:21 PM PDT 24
Peak memory 199976 kb
Host smart-ae2d1cad-b769-45f5-b6ac-c241c03161f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284930437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1284930437
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.504890363
Short name T197
Test name
Test status
Simulation time 766817512 ps
CPU time 45.58 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:05:29 PM PDT 24
Peak memory 199836 kb
Host smart-37d5e774-83ed-477f-b8e1-62afeccefbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504890363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.504890363
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.667128203
Short name T59
Test name
Test status
Simulation time 430136919 ps
CPU time 12.75 seconds
Started Aug 10 05:04:45 PM PDT 24
Finished Aug 10 05:04:58 PM PDT 24
Peak memory 199860 kb
Host smart-745bcd6d-6a8f-457f-84e2-538e89a06a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667128203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.667128203
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3820934461
Short name T73
Test name
Test status
Simulation time 356208306541 ps
CPU time 1177.71 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 569988 kb
Host smart-23ffc45e-890e-4b92-8233-91c686b23183
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820934461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3820934461
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1850953870
Short name T83
Test name
Test status
Simulation time 50290502414 ps
CPU time 144.85 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:07:11 PM PDT 24
Peak memory 199948 kb
Host smart-b9d3e03a-bbf7-4cf8-999c-7e6e85828a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850953870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1850953870
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.106577437
Short name T327
Test name
Test status
Simulation time 15470299 ps
CPU time 0.61 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:04:46 PM PDT 24
Peak memory 195524 kb
Host smart-bae697c7-da62-49ae-a5c9-7b9709ea608c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106577437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.106577437
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3705969372
Short name T368
Test name
Test status
Simulation time 2956528761 ps
CPU time 89.27 seconds
Started Aug 10 05:04:45 PM PDT 24
Finished Aug 10 05:06:14 PM PDT 24
Peak memory 199868 kb
Host smart-1d6476a9-18ec-45b9-ae91-1bbe762cb6f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705969372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3705969372
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.478604496
Short name T473
Test name
Test status
Simulation time 422175438 ps
CPU time 1.97 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:04:48 PM PDT 24
Peak memory 199804 kb
Host smart-6470a14c-b6c2-4ab7-a6a9-df2058df840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478604496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.478604496
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2924993228
Short name T130
Test name
Test status
Simulation time 1741604728 ps
CPU time 258.82 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:09:05 PM PDT 24
Peak memory 588340 kb
Host smart-ae37d200-ed42-4b49-a470-9575eb0e0927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924993228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2924993228
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2684310830
Short name T367
Test name
Test status
Simulation time 19613391709 ps
CPU time 185.22 seconds
Started Aug 10 05:04:47 PM PDT 24
Finished Aug 10 05:07:52 PM PDT 24
Peak memory 199812 kb
Host smart-90c65b47-d937-4f64-bafd-3d20fa3ed4b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684310830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2684310830
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3018623609
Short name T274
Test name
Test status
Simulation time 3734342015 ps
CPU time 102.08 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:06:29 PM PDT 24
Peak memory 199892 kb
Host smart-58687f75-2870-4e6a-af42-d8f10883fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018623609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3018623609
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.262332126
Short name T194
Test name
Test status
Simulation time 480597022 ps
CPU time 6.18 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:04:52 PM PDT 24
Peak memory 199796 kb
Host smart-73756fd1-7367-499b-8437-28bf7cafa8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262332126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.262332126
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.230410101
Short name T345
Test name
Test status
Simulation time 5378703947 ps
CPU time 66.18 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:05:53 PM PDT 24
Peak memory 199840 kb
Host smart-1e340014-b225-47bd-b7e2-664e1d9ae329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230410101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.230410101
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2537420679
Short name T15
Test name
Test status
Simulation time 26057919 ps
CPU time 0.59 seconds
Started Aug 10 05:04:47 PM PDT 24
Finished Aug 10 05:04:48 PM PDT 24
Peak memory 194832 kb
Host smart-c5237591-8662-40f7-8b56-c3451e3a684a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537420679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2537420679
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1304729382
Short name T238
Test name
Test status
Simulation time 78462720 ps
CPU time 4.64 seconds
Started Aug 10 05:04:50 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 199544 kb
Host smart-a305b259-5732-4adc-b1f6-e20415a17bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304729382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1304729382
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3895413521
Short name T125
Test name
Test status
Simulation time 3050769823 ps
CPU time 41.29 seconds
Started Aug 10 05:04:48 PM PDT 24
Finished Aug 10 05:05:29 PM PDT 24
Peak memory 199920 kb
Host smart-aa6d443c-ce8b-4335-8d90-778329490c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895413521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3895413521
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2624167043
Short name T517
Test name
Test status
Simulation time 3101177805 ps
CPU time 544.37 seconds
Started Aug 10 05:04:44 PM PDT 24
Finished Aug 10 05:13:49 PM PDT 24
Peak memory 464188 kb
Host smart-6f49f770-3f34-4901-8c46-4dbd7f039081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624167043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2624167043
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.8110634
Short name T406
Test name
Test status
Simulation time 67423932363 ps
CPU time 125.6 seconds
Started Aug 10 05:04:49 PM PDT 24
Finished Aug 10 05:06:55 PM PDT 24
Peak memory 199756 kb
Host smart-c24b127d-4a57-4904-a006-90cd9c849e25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8110634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.8110634
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1578387151
Short name T45
Test name
Test status
Simulation time 85771978 ps
CPU time 4.7 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:04:51 PM PDT 24
Peak memory 199844 kb
Host smart-b2046c5b-eba5-4351-9349-420338aa89a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578387151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1578387151
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.67421637
Short name T357
Test name
Test status
Simulation time 2973138886 ps
CPU time 13.98 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:05:01 PM PDT 24
Peak memory 199844 kb
Host smart-85d553fa-f07e-40d3-b650-9a8cad3d422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67421637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.67421637
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1292680843
Short name T337
Test name
Test status
Simulation time 137810370828 ps
CPU time 2846.85 seconds
Started Aug 10 05:04:46 PM PDT 24
Finished Aug 10 05:52:13 PM PDT 24
Peak memory 796384 kb
Host smart-122ea4ed-6705-4962-8927-4a44cd647374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292680843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1292680843
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1818140940
Short name T110
Test name
Test status
Simulation time 12580009315 ps
CPU time 112.92 seconds
Started Aug 10 05:04:47 PM PDT 24
Finished Aug 10 05:06:40 PM PDT 24
Peak memory 199748 kb
Host smart-3a588aa3-3c6f-4fc7-b3c0-77afa5544106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818140940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1818140940
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.259954665
Short name T361
Test name
Test status
Simulation time 50404908 ps
CPU time 0.59 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:04:55 PM PDT 24
Peak memory 195900 kb
Host smart-81e97380-c43e-4b2b-abbc-bd0c1f872fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259954665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.259954665
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2607994163
Short name T403
Test name
Test status
Simulation time 3176112531 ps
CPU time 92.24 seconds
Started Aug 10 05:04:48 PM PDT 24
Finished Aug 10 05:06:21 PM PDT 24
Peak memory 199928 kb
Host smart-333a6464-192b-4944-97e7-41281410dc6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607994163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2607994163
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.298876287
Short name T237
Test name
Test status
Simulation time 7142028323 ps
CPU time 36.5 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:05:29 PM PDT 24
Peak memory 199852 kb
Host smart-ca2a0488-52f2-4c99-af95-bcfd7829ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298876287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.298876287
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2651744307
Short name T202
Test name
Test status
Simulation time 22792479166 ps
CPU time 1071.34 seconds
Started Aug 10 05:04:50 PM PDT 24
Finished Aug 10 05:22:42 PM PDT 24
Peak memory 738988 kb
Host smart-e684798b-8d9a-4a0d-a507-6de075b7afe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651744307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2651744307
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.4062150858
Short name T413
Test name
Test status
Simulation time 4172415703 ps
CPU time 235.65 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:08:49 PM PDT 24
Peak memory 199980 kb
Host smart-1affc22d-8f80-4981-b9ab-7dd3c2039bae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062150858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.4062150858
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1270605542
Short name T243
Test name
Test status
Simulation time 16393578732 ps
CPU time 146.53 seconds
Started Aug 10 05:04:49 PM PDT 24
Finished Aug 10 05:07:15 PM PDT 24
Peak memory 199892 kb
Host smart-4da6b7cb-b83e-42f1-893e-5329c5a53f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270605542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1270605542
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2638443351
Short name T120
Test name
Test status
Simulation time 268115217 ps
CPU time 6.05 seconds
Started Aug 10 05:04:47 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 199900 kb
Host smart-5b825016-b04d-4f77-ba8b-1f277b51ee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638443351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2638443351
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3451317992
Short name T180
Test name
Test status
Simulation time 132930417248 ps
CPU time 2295.32 seconds
Started Aug 10 05:04:50 PM PDT 24
Finished Aug 10 05:43:06 PM PDT 24
Peak memory 784448 kb
Host smart-af27ad81-06b0-4948-b8d5-e731412afad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451317992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3451317992
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.956957190
Short name T273
Test name
Test status
Simulation time 16978768363 ps
CPU time 128.62 seconds
Started Aug 10 05:04:50 PM PDT 24
Finished Aug 10 05:06:59 PM PDT 24
Peak memory 199876 kb
Host smart-85d81fbd-1d5a-4433-a595-3973ad67a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956957190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.956957190
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1959955754
Short name T354
Test name
Test status
Simulation time 52813870 ps
CPU time 0.6 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:04:52 PM PDT 24
Peak memory 194908 kb
Host smart-ee4ed908-7010-4837-8006-143b2643cb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959955754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1959955754
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4046609511
Short name T348
Test name
Test status
Simulation time 325806400 ps
CPU time 18.69 seconds
Started Aug 10 05:04:51 PM PDT 24
Finished Aug 10 05:05:10 PM PDT 24
Peak memory 199672 kb
Host smart-82b610e7-8ae1-43cb-8970-a9f2252bb3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046609511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4046609511
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1053450492
Short name T462
Test name
Test status
Simulation time 3177106038 ps
CPU time 55.34 seconds
Started Aug 10 05:04:55 PM PDT 24
Finished Aug 10 05:05:50 PM PDT 24
Peak memory 199980 kb
Host smart-b5cdb366-9b54-4563-8529-92f22309ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053450492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1053450492
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1693078054
Short name T308
Test name
Test status
Simulation time 2199086204 ps
CPU time 404.28 seconds
Started Aug 10 05:04:51 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 623268 kb
Host smart-18ca077f-a632-4df0-b578-ae30b367cfb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693078054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1693078054
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1362285096
Short name T145
Test name
Test status
Simulation time 1307238820 ps
CPU time 19.47 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 199740 kb
Host smart-218a3a46-07ae-4326-9b0f-19108ff736d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362285096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1362285096
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3671373335
Short name T171
Test name
Test status
Simulation time 8852714191 ps
CPU time 126.87 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:06:59 PM PDT 24
Peak memory 199856 kb
Host smart-2940d1f3-469c-413f-92ff-1a61c4556abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671373335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3671373335
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4151160229
Short name T466
Test name
Test status
Simulation time 14804304 ps
CPU time 0.84 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 198420 kb
Host smart-a791404f-7c85-4117-84a7-19c6cd23e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151160229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4151160229
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.734936971
Short name T305
Test name
Test status
Simulation time 40594557414 ps
CPU time 573 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:14:27 PM PDT 24
Peak memory 216164 kb
Host smart-65004fcc-7bb0-4b53-8bb0-852bbc8ce1b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734936971 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.734936971
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.184138713
Short name T196
Test name
Test status
Simulation time 2178450020 ps
CPU time 40.34 seconds
Started Aug 10 05:04:50 PM PDT 24
Finished Aug 10 05:05:31 PM PDT 24
Peak memory 199812 kb
Host smart-22f5d4f4-6a31-4dcb-977b-c1f70d45d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184138713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.184138713
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2423821673
Short name T431
Test name
Test status
Simulation time 15141750 ps
CPU time 0.62 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 195792 kb
Host smart-c961f002-543c-4621-84c2-e26fbb2b5f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423821673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2423821673
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1212433483
Short name T214
Test name
Test status
Simulation time 2516503243 ps
CPU time 71.48 seconds
Started Aug 10 05:04:57 PM PDT 24
Finished Aug 10 05:06:08 PM PDT 24
Peak memory 199828 kb
Host smart-89274988-7bfa-481c-bfd5-57c9f713bed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212433483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1212433483
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1664491901
Short name T433
Test name
Test status
Simulation time 1020539144 ps
CPU time 13.43 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:05:06 PM PDT 24
Peak memory 199896 kb
Host smart-597b0e66-a837-4d64-94c3-a22891a9f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664491901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1664491901
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3179208529
Short name T328
Test name
Test status
Simulation time 30084140983 ps
CPU time 1094.1 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:23:07 PM PDT 24
Peak memory 776496 kb
Host smart-4402a943-b95a-4519-abe6-543eedf7f577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179208529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3179208529
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.225897966
Short name T166
Test name
Test status
Simulation time 16310998199 ps
CPU time 203.1 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:08:15 PM PDT 24
Peak memory 199708 kb
Host smart-3916c5c7-9edf-4065-a3ac-11a9348a303f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225897966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.225897966
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2330754653
Short name T190
Test name
Test status
Simulation time 10572776439 ps
CPU time 79.13 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:06:14 PM PDT 24
Peak memory 208092 kb
Host smart-59b8b2e1-df7f-425f-bdf1-7a7220a77cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330754653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2330754653
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3473931078
Short name T69
Test name
Test status
Simulation time 17019374511 ps
CPU time 10.64 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:05:05 PM PDT 24
Peak memory 199928 kb
Host smart-4099c59a-2479-42c2-81c7-c56034f1cad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473931078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3473931078
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1797776715
Short name T81
Test name
Test status
Simulation time 34673164957 ps
CPU time 1510.9 seconds
Started Aug 10 05:04:57 PM PDT 24
Finished Aug 10 05:30:08 PM PDT 24
Peak memory 690248 kb
Host smart-4300dd57-8acf-46a8-9a58-1a989989cf25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797776715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1797776715
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4284923472
Short name T504
Test name
Test status
Simulation time 7194383830 ps
CPU time 69.64 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:06:03 PM PDT 24
Peak memory 199800 kb
Host smart-7a4ee0c8-46e4-4eeb-a0fc-734aa64ca35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284923472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4284923472
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2366667971
Short name T352
Test name
Test status
Simulation time 16357382 ps
CPU time 0.58 seconds
Started Aug 10 05:04:55 PM PDT 24
Finished Aug 10 05:04:56 PM PDT 24
Peak memory 195820 kb
Host smart-5e7b17aa-25c5-447e-b12e-2a0aaa8df643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366667971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2366667971
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2871480654
Short name T411
Test name
Test status
Simulation time 348342046 ps
CPU time 19.23 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:05:12 PM PDT 24
Peak memory 199456 kb
Host smart-a3990ab9-082e-4fd3-b969-a8e0c24b183c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871480654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2871480654
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1556836662
Short name T314
Test name
Test status
Simulation time 5451430526 ps
CPU time 33.65 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:05:25 PM PDT 24
Peak memory 199908 kb
Host smart-3a656953-1b8f-4d84-a059-1854482529c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556836662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1556836662
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2093130440
Short name T299
Test name
Test status
Simulation time 31213648273 ps
CPU time 1661.9 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:32:34 PM PDT 24
Peak memory 765944 kb
Host smart-953d341d-e198-4475-894b-f7a3d2d8a0c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093130440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2093130440
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3971820659
Short name T42
Test name
Test status
Simulation time 6889375665 ps
CPU time 94 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:06:27 PM PDT 24
Peak memory 199908 kb
Host smart-5e4ae760-0c3e-4517-9485-605d83587a4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971820659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3971820659
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3660388627
Short name T140
Test name
Test status
Simulation time 15789604309 ps
CPU time 56.93 seconds
Started Aug 10 05:04:55 PM PDT 24
Finished Aug 10 05:05:52 PM PDT 24
Peak memory 199840 kb
Host smart-63232173-963e-4bee-a813-00a4e679d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660388627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3660388627
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1354132530
Short name T395
Test name
Test status
Simulation time 481609905 ps
CPU time 11.33 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:05:05 PM PDT 24
Peak memory 199756 kb
Host smart-2198189a-ff84-43e4-9403-68efd4e06e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354132530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1354132530
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1297342081
Short name T61
Test name
Test status
Simulation time 35824341374 ps
CPU time 1191.54 seconds
Started Aug 10 05:04:55 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 743776 kb
Host smart-e10fdbe2-0aa7-493e-9944-34e2a6abf5c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297342081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1297342081
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3317403421
Short name T175
Test name
Test status
Simulation time 7929828495 ps
CPU time 151.63 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:07:25 PM PDT 24
Peak memory 199788 kb
Host smart-42059baa-f642-4d9e-9868-06a7a12d78d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317403421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3317403421
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3529064449
Short name T392
Test name
Test status
Simulation time 11449989 ps
CPU time 0.6 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:04:54 PM PDT 24
Peak memory 195520 kb
Host smart-4a55eda4-c3e8-4751-91f6-9753289c44ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529064449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3529064449
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.928425512
Short name T384
Test name
Test status
Simulation time 287760174 ps
CPU time 17.28 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:05:11 PM PDT 24
Peak memory 199908 kb
Host smart-677bc781-2122-4bce-8381-57883a307021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928425512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.928425512
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.453585922
Short name T464
Test name
Test status
Simulation time 6070319915 ps
CPU time 54.7 seconds
Started Aug 10 05:04:55 PM PDT 24
Finished Aug 10 05:05:50 PM PDT 24
Peak memory 199812 kb
Host smart-52d48172-7ac7-495a-baa8-7b73413d3ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453585922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.453585922
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2678212201
Short name T193
Test name
Test status
Simulation time 9317622443 ps
CPU time 1095.61 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:23:08 PM PDT 24
Peak memory 719560 kb
Host smart-d10f56c6-11ce-4d38-be1e-53954248d92b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678212201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2678212201
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1416165852
Short name T157
Test name
Test status
Simulation time 716711625 ps
CPU time 40.34 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:05:34 PM PDT 24
Peak memory 199676 kb
Host smart-d3654d32-4eff-46e7-a9fd-90b0f4c67c56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416165852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1416165852
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2968671617
Short name T204
Test name
Test status
Simulation time 2552704174 ps
CPU time 108.2 seconds
Started Aug 10 05:04:52 PM PDT 24
Finished Aug 10 05:06:40 PM PDT 24
Peak memory 199888 kb
Host smart-9e2a92f6-8607-4a3f-a957-0a91349f1bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968671617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2968671617
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.671405049
Short name T112
Test name
Test status
Simulation time 440482075 ps
CPU time 3.26 seconds
Started Aug 10 05:04:56 PM PDT 24
Finished Aug 10 05:05:00 PM PDT 24
Peak memory 199828 kb
Host smart-486b2928-d166-4941-b469-69cc8e1eaa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671405049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.671405049
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2889764919
Short name T200
Test name
Test status
Simulation time 16254433874 ps
CPU time 757.67 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:17:31 PM PDT 24
Peak memory 470188 kb
Host smart-7fce2ec3-bcc5-48e2-800d-7f1ffe44937f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889764919 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2889764919
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3624016309
Short name T235
Test name
Test status
Simulation time 100242306240 ps
CPU time 114.7 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:06:49 PM PDT 24
Peak memory 199860 kb
Host smart-fc3773c0-0ad5-46b2-9257-f57fbd9faa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624016309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3624016309
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4186131084
Short name T312
Test name
Test status
Simulation time 44442713 ps
CPU time 0.62 seconds
Started Aug 10 05:05:03 PM PDT 24
Finished Aug 10 05:05:04 PM PDT 24
Peak memory 196584 kb
Host smart-ea9615bb-82e0-479e-bc36-0d642c8d9d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186131084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4186131084
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3472641547
Short name T211
Test name
Test status
Simulation time 3730459381 ps
CPU time 63.23 seconds
Started Aug 10 05:04:56 PM PDT 24
Finished Aug 10 05:05:59 PM PDT 24
Peak memory 199768 kb
Host smart-c25c7647-7027-4024-b8e3-086d6ed1a268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472641547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3472641547
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2065778518
Short name T511
Test name
Test status
Simulation time 1121871525 ps
CPU time 16.89 seconds
Started Aug 10 05:04:57 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 199784 kb
Host smart-3de00cf4-5f45-4dbb-9b40-6858d2bfbbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065778518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2065778518
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.521027062
Short name T481
Test name
Test status
Simulation time 4641791105 ps
CPU time 818.69 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:18:33 PM PDT 24
Peak memory 679796 kb
Host smart-8de7f594-6dea-4de0-9016-5f1333eabe8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521027062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.521027062
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1316895197
Short name T159
Test name
Test status
Simulation time 9268203571 ps
CPU time 124.52 seconds
Started Aug 10 05:04:57 PM PDT 24
Finished Aug 10 05:07:01 PM PDT 24
Peak memory 199828 kb
Host smart-aaa5fb87-8cb3-4d95-b122-fa6765df048e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316895197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1316895197
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.251711707
Short name T41
Test name
Test status
Simulation time 8664829153 ps
CPU time 128.04 seconds
Started Aug 10 05:04:54 PM PDT 24
Finished Aug 10 05:07:03 PM PDT 24
Peak memory 208128 kb
Host smart-88234837-b029-4a06-8193-e96c557c99f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251711707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.251711707
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4256902850
Short name T291
Test name
Test status
Simulation time 323700768 ps
CPU time 5.74 seconds
Started Aug 10 05:04:55 PM PDT 24
Finished Aug 10 05:05:00 PM PDT 24
Peak memory 199812 kb
Host smart-f96bc9db-7aba-455b-82ad-280365f3b9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256902850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4256902850
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2046452931
Short name T341
Test name
Test status
Simulation time 80031788805 ps
CPU time 1449.64 seconds
Started Aug 10 05:05:06 PM PDT 24
Finished Aug 10 05:29:16 PM PDT 24
Peak memory 719324 kb
Host smart-a5422ae5-7a7f-4ec0-b7b2-fd51fa620c30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046452931 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2046452931
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1230808109
Short name T246
Test name
Test status
Simulation time 2779443877 ps
CPU time 33.42 seconds
Started Aug 10 05:04:53 PM PDT 24
Finished Aug 10 05:05:27 PM PDT 24
Peak memory 199908 kb
Host smart-44823fab-2898-4bdc-ac66-c9286c6852c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230808109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1230808109
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.973344818
Short name T326
Test name
Test status
Simulation time 39370786 ps
CPU time 0.6 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:03:35 PM PDT 24
Peak memory 195868 kb
Host smart-38474d24-14d9-4bb9-ab71-71fda9cd0d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973344818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.973344818
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.755229254
Short name T82
Test name
Test status
Simulation time 716773376 ps
CPU time 38.43 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:04:13 PM PDT 24
Peak memory 199708 kb
Host smart-dd0ca74a-08e4-4db2-91a3-7a4dc36efbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755229254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.755229254
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2853865766
Short name T522
Test name
Test status
Simulation time 1737457634 ps
CPU time 30.64 seconds
Started Aug 10 05:03:32 PM PDT 24
Finished Aug 10 05:04:03 PM PDT 24
Peak memory 199756 kb
Host smart-359b835a-f596-4cd4-b9d1-aec96ec66ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853865766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2853865766
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1629644590
Short name T474
Test name
Test status
Simulation time 14769540506 ps
CPU time 495.63 seconds
Started Aug 10 05:03:41 PM PDT 24
Finished Aug 10 05:11:57 PM PDT 24
Peak memory 498976 kb
Host smart-e4c0533b-9cde-4121-8dec-699232357959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1629644590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1629644590
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3718978786
Short name T391
Test name
Test status
Simulation time 3442425028 ps
CPU time 189.09 seconds
Started Aug 10 05:03:32 PM PDT 24
Finished Aug 10 05:06:41 PM PDT 24
Peak memory 199948 kb
Host smart-67abd0ff-b4dc-4012-a309-c2389d0079de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718978786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3718978786
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3963994238
Short name T347
Test name
Test status
Simulation time 3465362020 ps
CPU time 96.09 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 199916 kb
Host smart-4656a45f-8f27-401c-bf98-087378309087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963994238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3963994238
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.156462490
Short name T275
Test name
Test status
Simulation time 2533996025 ps
CPU time 15.47 seconds
Started Aug 10 05:03:21 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 200036 kb
Host smart-7079f5ee-7638-4d3d-83a4-4046aae08abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156462490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.156462490
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3637275860
Short name T66
Test name
Test status
Simulation time 35159090526 ps
CPU time 2484.43 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:44:59 PM PDT 24
Peak memory 723452 kb
Host smart-850153f7-6926-42bb-86b1-9bb4a08f95c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637275860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3637275860
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4180400602
Short name T241
Test name
Test status
Simulation time 8822922698 ps
CPU time 103.87 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:05:24 PM PDT 24
Peak memory 199992 kb
Host smart-33628a5a-6c1f-4660-9114-6532dc2c8ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180400602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4180400602
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2107874458
Short name T388
Test name
Test status
Simulation time 30891314 ps
CPU time 0.57 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:03:35 PM PDT 24
Peak memory 194608 kb
Host smart-8164e6fc-f7c6-4fe5-9901-ff28a60780b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107874458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2107874458
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3504519107
Short name T24
Test name
Test status
Simulation time 6422938573 ps
CPU time 86.11 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:05:04 PM PDT 24
Peak memory 199788 kb
Host smart-7d63623f-6305-425f-9011-39a7edf42a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504519107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3504519107
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1037506579
Short name T428
Test name
Test status
Simulation time 4905480424 ps
CPU time 66.05 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:04:43 PM PDT 24
Peak memory 208124 kb
Host smart-82b4405e-6569-44f3-8ffc-18a4e8cf62ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037506579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1037506579
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1965462948
Short name T346
Test name
Test status
Simulation time 6808221703 ps
CPU time 385.78 seconds
Started Aug 10 05:03:32 PM PDT 24
Finished Aug 10 05:09:58 PM PDT 24
Peak memory 682108 kb
Host smart-75f3efe2-f879-495d-ad73-7e85f16e869e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965462948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1965462948
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2953624461
Short name T188
Test name
Test status
Simulation time 5321623425 ps
CPU time 44.4 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:04:20 PM PDT 24
Peak memory 199776 kb
Host smart-ae6f2281-93ec-4e3e-8599-406dc9b980b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953624461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2953624461
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.488133078
Short name T505
Test name
Test status
Simulation time 4226045063 ps
CPU time 79.06 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:04:53 PM PDT 24
Peak memory 199748 kb
Host smart-d57a64b9-1e6c-47b7-8388-37b058949f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488133078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.488133078
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3249954420
Short name T293
Test name
Test status
Simulation time 86138853 ps
CPU time 1.65 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:38 PM PDT 24
Peak memory 199648 kb
Host smart-97594af7-893c-4674-9998-20c1949bad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249954420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3249954420
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1830524491
Short name T439
Test name
Test status
Simulation time 42707011517 ps
CPU time 955.2 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:19:31 PM PDT 24
Peak memory 712228 kb
Host smart-8dfc1aae-4afb-4f41-bf9b-2bd0b39ce353
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830524491 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1830524491
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3881954948
Short name T455
Test name
Test status
Simulation time 44310521162 ps
CPU time 51.69 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:04:27 PM PDT 24
Peak memory 199800 kb
Host smart-dccf0bf0-278d-48d9-9f39-7979299f3602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881954948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3881954948
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2549041758
Short name T401
Test name
Test status
Simulation time 29544349 ps
CPU time 0.62 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 195816 kb
Host smart-cc3c9c10-e9ae-42e5-bb83-5857909bf8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549041758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2549041758
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2724715665
Short name T427
Test name
Test status
Simulation time 261018143 ps
CPU time 14.88 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:51 PM PDT 24
Peak memory 199652 kb
Host smart-bd5d6a50-8752-4da3-8232-dc57fcc48c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724715665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2724715665
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.134570813
Short name T364
Test name
Test status
Simulation time 4097009342 ps
CPU time 59.28 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:04:38 PM PDT 24
Peak memory 199924 kb
Host smart-fe5bda91-eb3f-4ecc-aad8-e545b89f2145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134570813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.134570813
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2352678742
Short name T85
Test name
Test status
Simulation time 2551050520 ps
CPU time 503.23 seconds
Started Aug 10 05:03:39 PM PDT 24
Finished Aug 10 05:12:02 PM PDT 24
Peak memory 704240 kb
Host smart-3d29455f-6eda-4540-a96f-6f27cc0a690f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352678742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2352678742
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2762362340
Short name T334
Test name
Test status
Simulation time 1796441041 ps
CPU time 103.24 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 199716 kb
Host smart-3da8b43e-0476-45bb-add3-dc94e1a9a0d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762362340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2762362340
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1845218833
Short name T262
Test name
Test status
Simulation time 3626553647 ps
CPU time 49.09 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:04:26 PM PDT 24
Peak memory 199888 kb
Host smart-bc17ecdc-d31e-4571-badc-4e2202ad21c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845218833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1845218833
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2260024076
Short name T437
Test name
Test status
Simulation time 740775191 ps
CPU time 9.11 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:46 PM PDT 24
Peak memory 199956 kb
Host smart-8e328e59-ec0d-4b91-a836-8ed624323633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260024076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2260024076
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2794822005
Short name T44
Test name
Test status
Simulation time 35327232246 ps
CPU time 130.85 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:05:47 PM PDT 24
Peak memory 199940 kb
Host smart-a3bea33f-f243-4983-973d-b5b24d60e9c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794822005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2794822005
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1130096373
Short name T370
Test name
Test status
Simulation time 13699798569 ps
CPU time 60.6 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:04:37 PM PDT 24
Peak memory 200056 kb
Host smart-be733a5b-0b61-4874-a78f-a2f34de29c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130096373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1130096373
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4075499413
Short name T457
Test name
Test status
Simulation time 44982885 ps
CPU time 0.68 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:03:39 PM PDT 24
Peak memory 196636 kb
Host smart-767821d4-5c93-47dd-838b-d0dd67a4e1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075499413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4075499413
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1570510326
Short name T514
Test name
Test status
Simulation time 5519668777 ps
CPU time 54.96 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:04:33 PM PDT 24
Peak memory 199280 kb
Host smart-6d83e6a2-7a26-4f02-b9c6-fb547c01feb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570510326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1570510326
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1729983694
Short name T356
Test name
Test status
Simulation time 1100609947 ps
CPU time 15.98 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:03:53 PM PDT 24
Peak memory 199864 kb
Host smart-b511f82f-f959-44c8-873c-426e44650954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729983694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1729983694
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3319472429
Short name T270
Test name
Test status
Simulation time 5981212056 ps
CPU time 534.63 seconds
Started Aug 10 05:03:38 PM PDT 24
Finished Aug 10 05:12:32 PM PDT 24
Peak memory 688864 kb
Host smart-911c1cd8-51a1-4294-9140-a7a9446e81ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319472429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3319472429
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1233767377
Short name T500
Test name
Test status
Simulation time 10972212246 ps
CPU time 162.52 seconds
Started Aug 10 05:03:33 PM PDT 24
Finished Aug 10 05:06:16 PM PDT 24
Peak memory 199880 kb
Host smart-6d1f5b9d-b804-48fb-b41f-9cd7f348b561
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233767377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1233767377
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2497752262
Short name T284
Test name
Test status
Simulation time 134997799 ps
CPU time 7.29 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:03:41 PM PDT 24
Peak memory 199752 kb
Host smart-8fb15082-7d02-45c9-aec9-199d881c6c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497752262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2497752262
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4228658233
Short name T333
Test name
Test status
Simulation time 4583615394 ps
CPU time 13.58 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:03:48 PM PDT 24
Peak memory 199804 kb
Host smart-b4986bbf-6876-4809-91c3-bf9f4261b125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228658233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4228658233
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1629875106
Short name T252
Test name
Test status
Simulation time 69642163 ps
CPU time 0.66 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:38 PM PDT 24
Peak memory 195724 kb
Host smart-417d28e0-76de-4d25-888c-afecc407cf77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629875106 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1629875106
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.477387187
Short name T67
Test name
Test status
Simulation time 69792107681 ps
CPU time 1550.11 seconds
Started Aug 10 05:03:40 PM PDT 24
Finished Aug 10 05:29:30 PM PDT 24
Peak memory 632044 kb
Host smart-cd7f1704-4bee-4d80-a263-4b2095e79200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477387187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.477387187
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2159831394
Short name T201
Test name
Test status
Simulation time 6432531842 ps
CPU time 80.34 seconds
Started Aug 10 05:03:41 PM PDT 24
Finished Aug 10 05:05:01 PM PDT 24
Peak memory 199824 kb
Host smart-20731daa-1553-445e-853e-50d2257b4db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159831394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2159831394
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3993453515
Short name T37
Test name
Test status
Simulation time 14632247 ps
CPU time 0.6 seconds
Started Aug 10 05:03:41 PM PDT 24
Finished Aug 10 05:03:42 PM PDT 24
Peak memory 195892 kb
Host smart-192efe3a-ddbb-4a61-a186-5271cb730d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993453515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3993453515
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3782746633
Short name T298
Test name
Test status
Simulation time 1411768587 ps
CPU time 74.35 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:04:49 PM PDT 24
Peak memory 199784 kb
Host smart-96d1730d-6b45-4fcd-9a97-1118f998eab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782746633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3782746633
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4233198112
Short name T376
Test name
Test status
Simulation time 12175041148 ps
CPU time 53.68 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:04:31 PM PDT 24
Peak memory 199800 kb
Host smart-9fe42e23-a8fd-4bf6-9e70-08bf134d8afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233198112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4233198112
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.323341332
Short name T451
Test name
Test status
Simulation time 4449126813 ps
CPU time 844.83 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 710636 kb
Host smart-87c1460f-59d4-439b-ad78-6f4854f7e908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323341332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.323341332
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2583111162
Short name T476
Test name
Test status
Simulation time 2407112233 ps
CPU time 36.74 seconds
Started Aug 10 05:03:35 PM PDT 24
Finished Aug 10 05:04:12 PM PDT 24
Peak memory 199776 kb
Host smart-8aafcec6-db4f-4a85-a1c2-4f8cd9b2b160
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583111162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2583111162
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3815660317
Short name T2
Test name
Test status
Simulation time 21992253615 ps
CPU time 23.48 seconds
Started Aug 10 05:03:34 PM PDT 24
Finished Aug 10 05:03:57 PM PDT 24
Peak memory 199716 kb
Host smart-59ea4e66-b834-432b-93f8-845211db08a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815660317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3815660317
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3412514015
Short name T470
Test name
Test status
Simulation time 412747905 ps
CPU time 3.27 seconds
Started Aug 10 05:03:33 PM PDT 24
Finished Aug 10 05:03:37 PM PDT 24
Peak memory 199808 kb
Host smart-942615e3-b499-493c-850d-b2dfcba95043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412514015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3412514015
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.994934891
Short name T472
Test name
Test status
Simulation time 1522315386 ps
CPU time 20.68 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:03:58 PM PDT 24
Peak memory 199736 kb
Host smart-1fb65921-54a6-436b-9fb4-744b03b3a8ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994934891 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.994934891
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1020429826
Short name T65
Test name
Test status
Simulation time 52171957154 ps
CPU time 1283.71 seconds
Started Aug 10 05:03:36 PM PDT 24
Finished Aug 10 05:25:00 PM PDT 24
Peak memory 667192 kb
Host smart-45b5a87b-d5c1-4234-83dc-2419e619bef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020429826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1020429826
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2240396908
Short name T365
Test name
Test status
Simulation time 22510971899 ps
CPU time 97.73 seconds
Started Aug 10 05:03:37 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 199868 kb
Host smart-61043610-8a84-4db5-9cba-79a80112ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240396908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2240396908
Directory /workspace/9.hmac_wipe_secret/latest
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