Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17671424	1			T1	59576		T2	21935		T5	1660
all_values[1]	17671424	1			T1	59576		T2	21935		T5	1660
all_values[2]	17671424	1			T1	59576		T2	21935		T5	1660

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210086

1

T1

3

T2

2313

T7

2632

auto[1]

52804186

1

T1

178725

T2

63492

T5

4980

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45114934

1

T1

153770

T2

57339

T5

4281

auto[1]

7899338

1

T1

24958

T2

8466

T5

699

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62363	1			T1	3		T7	794		T23	21
all_values[0]	auto[0]	auto[1]	321	1			T7	2		T23	2		T22	2
all_values[0]	auto[1]	auto[0]	17589301	1			T1	59550		T2	21915		T5	1637
all_values[0]	auto[1]	auto[1]	19439	1			T1	23		T2	20		T5	23
all_values[1]	auto[0]	auto[0]	78628	1			T2	768		T7	1836		T17	5
all_values[1]	auto[0]	auto[1]	207	1			T11	4		T8	5		T114	3
all_values[1]	auto[1]	auto[0]	17592279	1			T1	59576		T2	21167		T5	1660
all_values[1]	auto[1]	auto[1]	310	1			T11	2		T8	7		T57	1
all_values[2]	auto[0]	auto[0]	40509	1			T2	991		T16	56		T51	938
all_values[2]	auto[0]	auto[1]	28058	1			T2	554		T11	26		T117	79
all_values[2]	auto[1]	auto[0]	9751854	1			T1	34641		T2	12498		T5	984
all_values[2]	auto[1]	auto[1]	7851003	1			T1	24935		T2	7892		T5	676