Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137542

1

T2

22

T5

22

T7

14

auto[1]

123572

1

T1

44

T2

24

T5

20

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	99035	1			T1	9		T2	19		T7	19
len_1026_2046	6258	1			T5	5		T15	19		T16	18
len_514_1022	3657	1			T2	3		T5	4		T15	3
len_2_510	5254	1			T1	1		T15	2		T16	6
len_2056	183	1			T11	2		T33	3		T129	3
len_2048	346	1			T1	1		T5	2		T15	1
len_2040	142	1			T23	2		T60	3		T11	2
len_1032	161	1			T23	3		T52	2		T60	3
len_1024	1947	1			T5	1		T16	4		T23	1
len_1016	158	1			T23	3		T60	1		T11	2
len_520	165	1			T5	2		T23	5		T60	2
len_512	899	1			T5	2		T15	1		T16	1
len_504	144	1			T23	2		T52	4		T130	1
len_8	893	1			T1	9		T6	13		T23	2
len_0	11315	1			T1	2		T2	1		T5	5

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

125

1

T51

2

T131

1

T132

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	54630	1			T2	10		T7	7		T15	102
auto[0]	len_1026_2046	3564	1			T5	3		T15	3		T16	11
auto[0]	len_514_1022	2312	1			T2	1		T5	2		T15	1
auto[0]	len_2_510	2393	1			T16	5		T4	3		T24	21
auto[0]	len_2056	86	1			T11	2		T33	1		T129	3
auto[0]	len_2048	200	1			T5	1		T16	1		T24	1
auto[0]	len_2040	74	1			T23	2		T33	1		T129	3
auto[0]	len_1032	107	1			T23	2		T52	2		T60	3
auto[0]	len_1024	337	1			T5	1		T16	3		T23	1
auto[0]	len_1016	95	1			T23	1		T60	1		T133	3
auto[0]	len_520	104	1			T5	1		T23	2		T60	2
auto[0]	len_512	339	1			T16	1		T23	2		T4	1
auto[0]	len_504	81	1			T52	2		T130	1		T8	1
auto[0]	len_8	17	1			T9	1		T134	1		T135	1
auto[0]	len_0	4432	1			T5	3		T17	2		T18	2
auto[1]	len_2050_plus	44405	1			T1	9		T2	9		T7	12
auto[1]	len_1026_2046	2694	1			T5	2		T15	16		T16	7
auto[1]	len_514_1022	1345	1			T2	2		T5	2		T15	2
auto[1]	len_2_510	2861	1			T1	1		T15	2		T16	1
auto[1]	len_2056	97	1			T33	2		T136	1		T115	1
auto[1]	len_2048	146	1			T1	1		T5	1		T15	1
auto[1]	len_2040	68	1			T60	3		T11	2		T137	2
auto[1]	len_1032	54	1			T23	1		T33	1		T137	1
auto[1]	len_1024	1610	1			T16	1		T4	4		T24	1
auto[1]	len_1016	63	1			T23	2		T11	2		T33	2
auto[1]	len_520	61	1			T5	1		T23	3		T33	3
auto[1]	len_512	560	1			T5	2		T15	1		T23	1
auto[1]	len_504	63	1			T23	2		T52	2		T138	3
auto[1]	len_8	876	1			T1	9		T6	13		T23	2
auto[1]	len_0	6883	1			T1	2		T2	1		T5	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

75

1

T51

2

T138

2

T71

1

auto[1]

len_upper

50

1

T131

1

T132

2

T117

1