Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4369020

1

T1

17330

T2

4237

T5

533

auto[1]

2756986

1

T1

12158

T2

6652

T5

281

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2608867

1

T1

16741

T2

4582

T5

276

auto[1]

4517139

1

T1

12747

T2

6307

T5

538

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3346159

1

T2

6594

T5

420

T7

2607

auto[1]

3779847

1

T1

29488

T2

4295

T5

394

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4420432

1

T1

13326

T2

6037

T5

466

auto[1]

2705574

1

T1

16162

T2

4852

T5

348

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6379122	1			T1	25910		T2	10593		T5	797
fifo_depth[1]	119830	1			T1	601		T2	179		T5	10
fifo_depth[2]	93664	1			T1	583		T2	82		T5	3
fifo_depth[3]	74884	1			T1	591		T2	32		T5	3
fifo_depth[4]	67223	1			T1	550		T2	2		T15	30
fifo_depth[5]	52159	1			T1	481		T2	1		T5	1
fifo_depth[6]	42201	1			T1	342		T15	2		T16	17
fifo_depth[7]	27320	1			T1	206		T15	2		T16	7

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

746884

1

T1

3578

T2

296

T5

17

auto[1]

6379122

1

T1

25910

T2

10593

T5

797

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7112972

1

T1

29488

T2

10889

T5

814

auto[1]

13034

1

T26

180

T27

372

T9

354

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

40262

1

T2

11

T17

20

T23

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25575

1

T5

1

T15

26

T16

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

28591

1

T2

28

T7

27

T15

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

41016

1

T2

18

T17

7

T18

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

150875

1

T2

55

T5

2

T15

27

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

38059

1

T7

27

T16

57

T17

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29866

1

T2

64

T5

3

T17

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33252

1

T2

45

T16

19

T23

33

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38479

1

T1

605

T15

7

T18

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

40827

1

T1

333

T2

16

T5

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49002

1

T1

759

T17

12

T18

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

45682

1

T1

566

T7

24

T16

38

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42056

1

T1

1029

T2

2

T5

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

51165

1

T1

286

T7

1

T16

46

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44347

1

T15

6

T16

12

T6

1286

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47830

1

T2

57

T6

90

T23

61

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

192169

1

T2

1780

T5

15

T7

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

174400

1

T5

44

T15

113

T16

179

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

167655

1

T2

240

T5

17

T7

433

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

165139

1

T2

437

T5

29

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1714452

1

T2

781

T5

105

T7

1313

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

167027

1

T5

56

T7

802

T16

151

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

198837

1

T2

1916

T5

40

T15

74

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

178984

1

T2

1219

T5

108

T7

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

342192

1

T1

4705

T5

59

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

391428

1

T1

3769

T2

551

T5

57

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

430822

1

T1

1667

T2

1115

T5

53

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

435628

1

T1

4337

T2

386

T7

373

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

504536

1

T1

2889

T2

45

T5

131

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

455518

1

T1

3714

T2

996

T5

52

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

446291

1

T1

1672

T5

31

T15

675

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

414044

1

T1

3157

T2

1127

T7

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

231634

1

T2

1791

T5

15

T7

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

199647

1

T5

45

T15

139

T16

180

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

195537

1

T2

268

T5

17

T7

460

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

205101

1

T2

455

T5

29

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1864853

1

T2

836

T5

107

T7

1313

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

204064

1

T5

56

T7

829

T16

208

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

228206

1

T2

1980

T5

43

T15

74

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

211567

1

T2

1264

T5

108

T7

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

379657

1

T1

5310

T5

59

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

431065

1

T1

4102

T2

567

T5

58

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

477799

1

T1

2426

T2

1115

T5

53

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

480066

1

T1

4903

T2

386

T7

397

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

546118

1

T1

3918

T2

47

T5

141

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

505930

1

T1

4000

T2

996

T5

52

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

490248

1

T1

1672

T5

31

T15

681

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

461480

1

T1

3157

T2

1184

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

797

1

T26

142

T27

22

T9

164

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

328

1

T9

16

T116

7

T139

88

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

709

1

T26

38

T116

70

T139

37

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1054

1

T27

10

T9

38

T139

71

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

474

1

T27

33

T9

6

T86

96

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1022

1

T9

4

T139

457

T140

40

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

497

1

T9

3

T21

2

T139

19

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

669

1

T139

260

T86

50

T141

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1014

1

T116

1

T139

467

T142

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1190

1

T139

66

T86

883

T140

30

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2025

1

T9

50

T139

249

T86

69

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1244

1

T116

1

T139

29

T141

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

474

1

T142

41

T13

4

T143

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

753

1

T27

70

T9

5

T139

72

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

390

1

T27

236

T9

18

T139

51

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

394

1

T27

1

T9

50

T139

2

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

192169

1

T2

1780

T5

15

T7

2

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

174400

1

T5

44

T15

113

T16

179

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

167655

1

T2

240

T5

17

T7

433

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

165139

1

T2

437

T5

29

T7

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1714452

1

T2

781

T5

105

T7

1313

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

167027

1

T5

56

T7

802

T16

151

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

198837

1

T2

1916

T5

40

T15

74

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

178984

1

T2

1219

T5

108

T7

2

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

342192

1

T1

4705

T5

59

T7

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

391428

1

T1

3769

T2

551

T5

57

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

430822

1

T1

1667

T2

1115

T5

53

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

435628

1

T1

4337

T2

386

T7

373

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

504536

1

T1

2889

T2

45

T5

131

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

455518

1

T1

3714

T2

996

T5

52

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

446291

1

T1

1672

T5

31

T15

675

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

414044

1

T1

3157

T2

1127

T7

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3895

1

T2

8

T17

10

T23

7

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3245

1

T15

4

T16

1

T17

5

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3548

1

T2

20

T7

21

T17

7

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3387

1

T2

10

T17

6

T18

6

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

44708

1

T2

31

T5

1

T16

3

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3411

1

T7

16

T16

6

T17

4

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3893

1

T2

39

T5

2

T17

4

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3989

1

T2

26

T23

30

T24

2

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5387

1

T1

90

T18

10

T23

122

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5452

1

T1

72

T2

9

T5

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6274

1

T1

126

T17

10

T18

5

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6475

1

T1

82

T7

17

T16

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7896

1

T1

172

T5

6

T7

7

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6880

1

T1

59

T7

1

T16

5

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5732

1

T6

201

T23

17

T4

22

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5658

1

T2

36

T6

11

T23

44

fifo_depth[2]

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2962

1

T2

3

T17

9

T24

45

fifo_depth[2]

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auto[0]

auto[0]

auto[1]

2685

1

T5

1

T15

8

T17

3

fifo_depth[2]

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auto[0]

auto[1]

auto[0]

2932

1

T2

7

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5

T16

1

fifo_depth[2]

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1

T2

7

T17

1

T18

1

fifo_depth[2]

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1

T2

17

T15

1

T16

58

fifo_depth[2]

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1

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10

T16

9

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3

fifo_depth[2]

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auto[0]

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1

T2

17

T23

13

T4

3

fifo_depth[2]

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1

T2

12

T16

1

T23

3

fifo_depth[2]

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auto[0]

auto[0]

4540

1

T1

82

T18

1

T23

22

fifo_depth[2]

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auto[0]

auto[1]

4696

1

T1

56

T2

5

T6

41

fifo_depth[2]

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auto[1]

auto[0]

5092

1

T1

124

T17

1

T18

1

fifo_depth[2]

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auto[0]

auto[1]

auto[1]

5755

1

T1

93

T7

4

T16

16

fifo_depth[2]

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auto[0]

auto[0]

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1

T1

178

T5

2

T18

9

fifo_depth[2]

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auto[1]

auto[0]

auto[1]

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1

T1

50

T16

2

T17

2

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

5052

1

T15

3

T16

5

T6

217

fifo_depth[2]

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auto[1]

auto[1]

5016

1

T2

14

T6

13

T23

14

fifo_depth[3]

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auto[0]

auto[0]

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1

T17

1

T23

1

T24

1

fifo_depth[3]

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auto[0]

auto[0]

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1

T15

2

T23

2

T11

2

fifo_depth[3]

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auto[0]

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1

T2

1

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1

T15

1

fifo_depth[3]

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auto[1]

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1

T2

1

T18

1

T4

1

fifo_depth[3]

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auto[0]

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1

T2

6

T5

1

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1

fifo_depth[3]

auto[0]

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auto[0]

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1

T7

1

T16

6

T24

1

fifo_depth[3]

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auto[1]

auto[0]

2220

1

T2

8

T5

1

T17

1

fifo_depth[3]

auto[0]

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auto[1]

auto[1]

2435

1

T2

7

T16

1

T51

4

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

3934

1

T1

107

T23

3

T51

1

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

4214

1

T1

63

T2

2

T6

36

fifo_depth[3]

auto[1]

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auto[1]

auto[0]

4442

1

T1

124

T17

1

T6

211

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

5022

1

T1

82

T7

3

T6

93

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

5009

1

T1

159

T2

1

T5

1

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

5293

1

T1

56

T16

2

T24

5

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

4299

1

T16

1

T6

185

T23

1

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

4306

1

T2

6

T6

11

T23

2

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

2307

1

T24

38

T51

1

T11

39

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

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1

T15

5

T11

1

T37

5

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

2242

1

T16

3

T4

2

T24

3

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2080

1

T23

1

T4

5

T51

1

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

16170

1

T15

16

T16

4

T4

11

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

2407

1

T16

17

T4

6

T24

24

fifo_depth[4]

auto[0]

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auto[1]

auto[0]

2164

1

T4

2

T51

1

T11

34

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

2254

1

T16

17

T35

9

T37

14

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

3908

1

T1

89

T15

6

T23

1

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

4188

1

T1

53

T6

34

T4

8

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

4256

1

T1

112

T6

161

T23

1

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

4841

1

T1

81

T16

16

T6

73

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

4518

1

T1

170

T2

1

T6

99

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

5274

1

T1

45

T16

18

T17

1

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4294

1

T15

3

T16

2

T6

199

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

4202

1

T2

1

T6

15

T23

1

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1820

1

T24

2

T11

27

T34

85

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1504

1

T15

3

T11

2

T34

2

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1577

1

T4

2

T24

2

T22

1

fifo_depth[5]

auto[0]

auto[0]

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auto[1]

1538

1

T11

22

T34

7

T35

14

fifo_depth[5]

auto[0]

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auto[0]

auto[0]

11281

1

T2

1

T15

1

T11

54

fifo_depth[5]

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auto[0]

auto[1]

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1

T16

2

T24

1

T11

12

fifo_depth[5]

auto[0]

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auto[0]

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1

T4

2

T11

22

T34

15

fifo_depth[5]

auto[0]

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auto[1]

1754

1

T35

5

T37

10

T133

3

fifo_depth[5]

auto[1]

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auto[0]

auto[0]

3327

1

T1

84

T4

2

T24

1

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[1]

3531

1

T1

46

T6

34

T11

8

fifo_depth[5]

auto[1]

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auto[1]

auto[0]

3440

1

T1

108

T6

129

T11

3

fifo_depth[5]

auto[1]

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auto[1]

auto[1]

4069

1

T1

75

T6

70

T4

2

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3615

1

T1

133

T5

1

T6

62

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

4281

1

T1

35

T16

2

T24

5

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[0]

3529

1

T6

164

T4

13

T51

1

fifo_depth[5]

auto[1]

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auto[1]

auto[1]

3419

1

T6

10

T4

1

T24

7

fifo_depth[6]

auto[0]

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auto[0]

auto[0]

1552

1

T24

27

T11

13

T34

69

fifo_depth[6]

auto[0]

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auto[0]

auto[1]

1307

1

T15

1

T11

1

T129

1

fifo_depth[6]

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auto[1]

auto[0]

1529

1

T16

1

T4

1

T24

4

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1290

1

T4

3

T11

12

T34

10

fifo_depth[6]

auto[0]

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auto[0]

auto[0]

7816

1

T15

1

T4

4

T11

30

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1664

1

T16

9

T4

3

T11

17

fifo_depth[6]

auto[0]

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auto[1]

auto[0]

1361

1

T4

1

T11

19

T34

9

fifo_depth[6]

auto[0]

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auto[1]

auto[1]

1464

1

T35

4

T37

10

T75

71

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

2682

1

T1

63

T24

7

T11

9

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2921

1

T1

25

T6

28

T4

5

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2781

1

T1

72

T6

95

T35

17

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

3239

1

T1

61

T16

3

T6

39

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

2859

1

T1

94

T6

51

T144

1

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

3789

1

T1

27

T16

1

T24

9

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

3063

1

T16

3

T6

157

T4

11

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

2884

1

T6

11

T4

1

T24

3

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

1056

1

T24

2

T11

9

T34

31

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

830

1

T15

2

T129

2

T145

3

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

763

1

T16

1

T11

6

T34

16

fifo_depth[7]

auto[0]

auto[0]

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auto[1]

870

1

T11

6

T34

3

T35

5

fifo_depth[7]

auto[0]

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auto[0]

auto[0]

4638

1

T11

20

T34

5

T37

2

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

1027

1

T16

2

T4

1

T24

1

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

819

1

T4

1

T11

9

T34

9

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

1029

1

T35

6

T37

3

T75

39

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

1882

1

T1

45

T11

2

T132

1

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

2027

1

T1

11

T6

20

T4

1

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1999

1

T1

40

T6

42

T11

1

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

2024

1

T1

39

T6

21

T4

2

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

1949

1

T1

60

T6

19

T146

26

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

2422

1

T1

11

T16

4

T24

1

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

2102

1

T6

100

T4

6

T147

15

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1883

1

T6

7

T4

1

T11

6