Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17671424	1			T1	59576		T2	21935		T5	1660
all_pins[1]	17671424	1			T1	59576		T2	21935		T5	1660
all_pins[2]	17671424	1			T1	59576		T2	21935		T5	1660

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45142681	1			T1	153767		T2	57891		T5	4280
values[0x1]	7871591	1			T1	24961		T2	7914		T5	700
transitions[0x0=>0x1]	7871409	1			T1	24961		T2	7914		T5	700
transitions[0x1=>0x0]	7871427	1			T1	24961		T2	7914		T5	700

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17651174	1			T1	59550		T2	21913		T5	1636
all_pins[0]	values[0x1]	20250	1			T1	26		T2	22		T5	24
all_pins[0]	transitions[0x0=>0x1]	20162	1			T1	26		T2	22		T5	24
all_pins[0]	transitions[0x1=>0x0]	7850933	1			T1	24935		T2	7892		T5	676
all_pins[1]	values[0x0]	17671086	1			T1	59576		T2	21935		T5	1660
all_pins[1]	values[0x1]	338	1			T11	2		T8	7		T57	1
all_pins[1]	transitions[0x0=>0x1]	290	1			T11	2		T8	4		T57	1
all_pins[1]	transitions[0x1=>0x0]	20202	1			T1	26		T2	22		T5	24
all_pins[2]	values[0x0]	9820421	1			T1	34641		T2	14043		T5	984
all_pins[2]	values[0x1]	7851003	1			T1	24935		T2	7892		T5	676
all_pins[2]	transitions[0x0=>0x1]	7850957	1			T1	24935		T2	7892		T5	676
all_pins[2]	transitions[0x1=>0x0]	292	1			T11	2		T8	7		T57	1