Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 898 1 T11 14 T8 22 T57 7
all_values[1] 898 1 T11 14 T8 22 T57 7
all_values[2] 898 1 T11 14 T8 22 T57 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1343 1 T11 17 T8 36 T57 10
auto[1] 1351 1 T11 25 T8 30 T57 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 955 1 T11 20 T8 19 T57 13
auto[1] 1739 1 T11 22 T8 47 T57 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1554 1 T11 28 T8 39 T57 14
auto[1] 1140 1 T11 14 T8 27 T57 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 165 1 T11 2 T8 4 T57 4
all_values[0] auto[0] auto[0] auto[1] 82 1 T11 1 T8 2 T115 3
all_values[0] auto[0] auto[1] auto[0] 162 1 T11 5 T8 4 T57 1
all_values[0] auto[0] auto[1] auto[1] 109 1 T11 1 T8 4 T114 1
all_values[0] auto[1] auto[0] auto[1] 187 1 T11 2 T8 3 T115 2
all_values[0] auto[1] auto[1] auto[1] 193 1 T11 3 T8 5 T57 2
all_values[1] auto[0] auto[0] auto[0] 149 1 T11 1 T8 4 T57 4
all_values[1] auto[0] auto[0] auto[1] 128 1 T11 1 T8 5 T57 1
all_values[1] auto[0] auto[1] auto[0] 141 1 T11 3 T57 1 T114 1
all_values[1] auto[0] auto[1] auto[1] 102 1 T11 3 T8 1 T115 3
all_values[1] auto[1] auto[0] auto[1] 204 1 T11 4 T8 5 T114 4
all_values[1] auto[1] auto[1] auto[1] 174 1 T11 2 T8 7 T57 1
all_values[2] auto[0] auto[0] auto[0] 160 1 T11 5 T8 4 T114 1
all_values[2] auto[0] auto[0] auto[1] 88 1 T8 5 T115 1 T9 2
all_values[2] auto[0] auto[1] auto[0] 178 1 T11 4 T8 3 T57 3
all_values[2] auto[0] auto[1] auto[1] 90 1 T11 2 T8 3 T114 1
all_values[2] auto[1] auto[0] auto[1] 180 1 T11 1 T8 4 T57 1
all_values[2] auto[1] auto[1] auto[1] 202 1 T11 2 T8 3 T57 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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