Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4175	1			T1	6		T2	6		T5	8
sha2_none	4073	1			T1	7		T2	5		T5	11
sha2_512	7508	1			T1	7		T2	4		T5	8
sha2_384	7360	1			T1	8		T2	8		T5	12
sha2_256	6141	1			T1	13		T2	5		T5	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18391

1

T1

23

T2

13

T5

27

auto[1]

11223

1

T1

18

T2

15

T5

16

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10970

1

T1

20

T2

12

T5

18

auto[1]

18644

1

T1

21

T2

16

T5

25

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15042

1

T1

41

T2

12

T5

20

disabled

14572

1

T2

16

T5

23

T7

9

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4566	1			T1	4		T2	5		T5	8
key_none	7755	1			T1	4		T2	2		T5	6
key_1024	4314	1			T1	5		T2	6		T5	8
key_512	3550	1			T1	6		T2	2		T5	4
key_384	3456	1			T1	10		T2	3		T5	7
key_256	2956	1			T1	4		T2	3		T5	4
key_128	2943	1			T1	8		T2	7		T5	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18632

1

T1

18

T2

17

T5

22

auto[1]

10982

1

T1

23

T2

11

T5

21

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29386

1

T1

41

T2

28

T5

43

disabled

228

1

T7

2

T23

1

T53

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1445

1

T1

6

T5

2

T7

2

enabled

auto[0]

auto[0]

auto[1]

1497

1

T1

5

T2

2

T5

3

enabled

auto[0]

auto[1]

auto[0]

1573

1

T1

5

T2

3

T5

3

enabled

auto[0]

auto[1]

auto[1]

1554

1

T1

4

T2

1

T7

3

enabled

auto[1]

auto[0]

auto[0]

4272

1

T1

5

T2

2

T5

6

enabled

auto[1]

auto[0]

auto[1]

1532

1

T1

7

T2

2

T5

4

enabled

auto[1]

auto[1]

auto[0]

1650

1

T1

2

T5

2

T15

5

enabled

auto[1]

auto[1]

auto[1]

1519

1

T1

7

T2

2

T16

2

disabled

auto[0]

auto[0]

auto[0]

1227

1

T2

4

T5

1

T7

1

disabled

auto[0]

auto[0]

auto[1]

1218

1

T5

4

T15

2

T16

2

disabled

auto[0]

auto[1]

auto[0]

1239

1

T2

1

T5

3

T7

1

disabled

auto[0]

auto[1]

auto[1]

1217

1

T2

1

T5

2

T17

3

disabled

auto[1]

auto[0]

auto[0]

6007

1

T2

3

T5

4

T7

2

disabled

auto[1]

auto[0]

auto[1]

1193

1

T5

3

T7

4

T16

3

disabled

auto[1]

auto[1]

auto[0]

1219

1

T2

4

T5

1

T15

1

disabled

auto[1]

auto[1]

auto[1]

1252

1

T2

3

T5

5

T7

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14949

1

T1

41

T2

12

T5

20

enabled

disabled

93

1

T7

1

T23

1

T53

1

disabled

disabled

135

1

T7

1

T11

5

T37

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14437

1

T2

16

T5

23

T7

8

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1116	1			T1	1		T2	2		T5	2
key_invalid	sha2_none	821	1			T2	2		T5	3		T15	1
key_invalid	sha2_512	834	1			T1	1		T2	1		T7	1
key_invalid	sha2_384	872	1			T5	3		T7	1		T16	2
key_invalid	sha2_256	839	1			T1	2		T7	1		T17	2
key_none	sha2_invalid	497	1			T5	2		T7	1		T16	1
key_none	sha2_none	575	1			T1	1		T5	2		T15	1
key_none	sha2_512	2509	1			T5	1		T16	4		T17	1
key_none	sha2_384	2524	1			T1	1		T2	1		T15	1
key_none	sha2_256	1602	1			T1	2		T2	1		T5	1
key_1024	sha2_invalid	543	1			T1	2		T2	1		T15	2
key_1024	sha2_none	572	1			T1	1		T2	1		T5	3
key_1024	sha2_512	1764	1			T2	2		T5	1		T7	1
key_1024	sha2_384	870	1			T1	1		T2	1		T5	3
key_512	sha2_invalid	458	1			T5	1		T16	1		T18	1
key_512	sha2_none	548	1			T1	2		T2	1		T5	1
key_512	sha2_512	529	1			T1	2		T5	1		T15	2
key_512	sha2_384	1210	1			T1	1		T5	1		T17	2
key_512	sha2_256	773	1			T1	1		T2	1		T7	1
key_384	sha2_invalid	553	1			T2	1		T5	3		T16	1
key_384	sha2_none	531	1			T1	3		T23	5		T4	5
key_384	sha2_512	659	1			T1	3		T5	1		T7	1
key_384	sha2_384	628	1			T1	1		T5	2		T16	2
key_384	sha2_256	1041	1			T1	3		T2	2		T5	1
key_256	sha2_invalid	488	1			T1	2		T7	1		T15	3
key_256	sha2_none	508	1			T18	1		T6	2		T23	9
key_256	sha2_512	601	1			T1	1		T2	1		T5	2
key_256	sha2_384	589	1			T2	2		T5	1		T15	2
key_256	sha2_256	716	1			T1	1		T7	1		T18	2
key_128	sha2_invalid	506	1			T1	1		T2	2		T17	2
key_128	sha2_none	504	1			T2	1		T5	2		T15	1
key_128	sha2_512	598	1			T5	2		T7	1		T16	1
key_128	sha2_384	654	1			T1	4		T2	4		T5	1
key_128	sha2_256	635	1			T1	3		T7	3		T17	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

516

1

T1

1

T2

1

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1116	1			T1	1		T2	2		T5	2
key_invalid	sha2_none	821	1			T2	2		T5	3		T15	1
key_invalid	sha2_512	834	1			T1	1		T2	1		T7	1
key_invalid	sha2_384	872	1			T5	3		T7	1		T16	2
key_invalid	sha2_256	839	1			T1	2		T7	1		T17	2
key_none	sha2_invalid	497	1			T5	2		T7	1		T16	1
key_none	sha2_none	575	1			T1	1		T5	2		T15	1
key_none	sha2_512	2509	1			T5	1		T16	4		T17	1
key_none	sha2_384	2524	1			T1	1		T2	1		T15	1
key_none	sha2_256	1602	1			T1	2		T2	1		T5	1
key_1024	sha2_invalid	543	1			T1	2		T2	1		T15	2
key_1024	sha2_none	572	1			T1	1		T2	1		T5	3
key_1024	sha2_512	1764	1			T2	2		T5	1		T7	1
key_1024	sha2_384	870	1			T1	1		T2	1		T5	3
key_1024	sha2_256	516	1			T1	1		T2	1		T5	1
key_512	sha2_invalid	458	1			T5	1		T16	1		T18	1
key_512	sha2_none	548	1			T1	2		T2	1		T5	1
key_512	sha2_512	529	1			T1	2		T5	1		T15	2
key_512	sha2_384	1210	1			T1	1		T5	1		T17	2
key_512	sha2_256	773	1			T1	1		T2	1		T7	1
key_384	sha2_invalid	553	1			T2	1		T5	3		T16	1
key_384	sha2_none	531	1			T1	3		T23	5		T4	5
key_384	sha2_512	659	1			T1	3		T5	1		T7	1
key_384	sha2_384	628	1			T1	1		T5	2		T16	2
key_384	sha2_256	1041	1			T1	3		T2	2		T5	1
key_256	sha2_invalid	488	1			T1	2		T7	1		T15	3
key_256	sha2_none	508	1			T18	1		T6	2		T23	9
key_256	sha2_512	601	1			T1	1		T2	1		T5	2
key_256	sha2_384	589	1			T2	2		T5	1		T15	2
key_256	sha2_256	716	1			T1	1		T7	1		T18	2
key_128	sha2_invalid	506	1			T1	1		T2	2		T17	2
key_128	sha2_none	504	1			T2	1		T5	2		T15	1
key_128	sha2_512	598	1			T5	2		T7	1		T16	1
key_128	sha2_384	654	1			T1	4		T2	4		T5	1
key_128	sha2_256	635	1			T1	3		T7	3		T17	1