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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.04 95.40 97.22 100.00 97.06 98.27 98.48 99.85


Total test records in report: 660
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T535 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.242546719 Aug 11 07:01:42 PM PDT 24 Aug 11 07:01:43 PM PDT 24 164467070 ps
T536 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2192675739 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:41 PM PDT 24 16769533 ps
T62 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.126082887 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:34 PM PDT 24 149584684 ps
T537 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.495254448 Aug 11 07:01:43 PM PDT 24 Aug 11 07:01:44 PM PDT 24 49796544 ps
T538 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3519067969 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:34 PM PDT 24 12065627 ps
T539 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2023252854 Aug 11 07:01:31 PM PDT 24 Aug 11 07:01:34 PM PDT 24 444262794 ps
T540 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1262500252 Aug 11 07:01:40 PM PDT 24 Aug 11 07:38:10 PM PDT 24 226180452338 ps
T90 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.805733810 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:30 PM PDT 24 16469073 ps
T541 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1078239028 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:24 PM PDT 24 155841608 ps
T542 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1526348324 Aug 11 07:01:11 PM PDT 24 Aug 11 07:01:13 PM PDT 24 199065353 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1872042601 Aug 11 07:01:12 PM PDT 24 Aug 11 07:01:15 PM PDT 24 833528127 ps
T543 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2260034530 Aug 11 07:01:44 PM PDT 24 Aug 11 07:01:45 PM PDT 24 12223254 ps
T544 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.486899859 Aug 11 07:01:24 PM PDT 24 Aug 11 07:01:28 PM PDT 24 74688934 ps
T545 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.37840183 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:30 PM PDT 24 273992602 ps
T546 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3543784868 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:29 PM PDT 24 32959218 ps
T63 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.878178156 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:31 PM PDT 24 223480113 ps
T547 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2738124352 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:29 PM PDT 24 29894895 ps
T118 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.205302357 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:36 PM PDT 24 617910989 ps
T105 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2007032767 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:43 PM PDT 24 37406056 ps
T548 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.646807463 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:22 PM PDT 24 24686667 ps
T106 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1586669900 Aug 11 07:01:31 PM PDT 24 Aug 11 07:01:32 PM PDT 24 173801837 ps
T549 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2410592386 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:46 PM PDT 24 101314309 ps
T550 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2995681865 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:40 PM PDT 24 48895028 ps
T551 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3427302864 Aug 11 07:01:27 PM PDT 24 Aug 11 07:01:30 PM PDT 24 125135091 ps
T552 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3724912407 Aug 11 07:01:22 PM PDT 24 Aug 11 07:01:25 PM PDT 24 224012257 ps
T107 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.97657545 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:30 PM PDT 24 358918510 ps
T108 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1183156248 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:34 PM PDT 24 21951559 ps
T553 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2533260509 Aug 11 07:01:12 PM PDT 24 Aug 11 07:01:12 PM PDT 24 16395593 ps
T554 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1190264969 Aug 11 07:01:45 PM PDT 24 Aug 11 07:01:46 PM PDT 24 18401503 ps
T555 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3021534662 Aug 11 07:01:25 PM PDT 24 Aug 11 07:01:28 PM PDT 24 288230558 ps
T92 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1641270166 Aug 11 07:01:24 PM PDT 24 Aug 11 07:01:25 PM PDT 24 103998559 ps
T556 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2699747181 Aug 11 07:01:32 PM PDT 24 Aug 11 07:01:33 PM PDT 24 69249620 ps
T557 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1807822488 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:20 PM PDT 24 19972350 ps
T93 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.433154363 Aug 11 07:01:36 PM PDT 24 Aug 11 07:01:37 PM PDT 24 65272210 ps
T558 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4112481822 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:41 PM PDT 24 100014141 ps
T109 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3079300807 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:30 PM PDT 24 177310296 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2102839753 Aug 11 07:01:26 PM PDT 24 Aug 11 07:01:26 PM PDT 24 30731826 ps
T560 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2630160666 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:40 PM PDT 24 25913680 ps
T561 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.410975078 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:41 PM PDT 24 1057042472 ps
T562 /workspace/coverage/cover_reg_top/7.hmac_intr_test.26635855 Aug 11 07:01:26 PM PDT 24 Aug 11 07:01:27 PM PDT 24 38999824 ps
T123 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.531794065 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:21 PM PDT 24 58542492 ps
T563 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2750069488 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:40 PM PDT 24 13866833 ps
T564 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3050212434 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:47 PM PDT 24 227635159 ps
T565 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2642409379 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:41 PM PDT 24 43546059 ps
T110 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2595745752 Aug 11 07:01:32 PM PDT 24 Aug 11 07:01:33 PM PDT 24 766526167 ps
T120 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2667128296 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:37 PM PDT 24 223813801 ps
T94 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3695136767 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:20 PM PDT 24 69235839 ps
T566 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3937517300 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:41 PM PDT 24 14325581 ps
T567 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1246405931 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:33 PM PDT 24 772396685 ps
T568 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3101213586 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:22 PM PDT 24 110066076 ps
T569 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3784196341 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:40 PM PDT 24 12419197 ps
T570 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2004558474 Aug 11 07:01:45 PM PDT 24 Aug 11 07:01:46 PM PDT 24 14718607 ps
T571 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.530679668 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:45 PM PDT 24 231445697 ps
T572 /workspace/coverage/cover_reg_top/33.hmac_intr_test.931681702 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:46 PM PDT 24 49549913 ps
T573 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2094199842 Aug 11 07:01:12 PM PDT 24 Aug 11 07:01:13 PM PDT 24 33219483 ps
T574 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2579242700 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:31 PM PDT 24 13952248 ps
T575 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.849198160 Aug 11 07:01:27 PM PDT 24 Aug 11 07:01:31 PM PDT 24 3568442484 ps
T127 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.137448888 Aug 11 07:01:10 PM PDT 24 Aug 11 07:01:13 PM PDT 24 105921063 ps
T576 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3035785994 Aug 11 07:01:31 PM PDT 24 Aug 11 07:01:32 PM PDT 24 103719962 ps
T95 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3203417645 Aug 11 07:01:27 PM PDT 24 Aug 11 07:01:28 PM PDT 24 16354364 ps
T577 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2707589408 Aug 11 07:01:32 PM PDT 24 Aug 11 07:01:34 PM PDT 24 79583435 ps
T578 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.347095627 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:31 PM PDT 24 115702228 ps
T579 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1441068515 Aug 11 07:01:47 PM PDT 24 Aug 11 07:01:48 PM PDT 24 11058446 ps
T580 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3105587715 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:31 PM PDT 24 35214488 ps
T581 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3670678659 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:28 PM PDT 24 14353638 ps
T124 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4231880054 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:32 PM PDT 24 451211924 ps
T582 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2680791872 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:29 PM PDT 24 133294465 ps
T583 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1436277541 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:46 PM PDT 24 15564656 ps
T584 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4225144907 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:41 PM PDT 24 12949298 ps
T119 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1985854182 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:31 PM PDT 24 588679171 ps
T585 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3013419110 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:42 PM PDT 24 80035733 ps
T586 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2270130269 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:32 PM PDT 24 41943461 ps
T587 /workspace/coverage/cover_reg_top/43.hmac_intr_test.304853940 Aug 11 07:01:44 PM PDT 24 Aug 11 07:01:45 PM PDT 24 31870742 ps
T96 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3850866845 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:35 PM PDT 24 499836494 ps
T588 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1662549020 Aug 11 07:01:45 PM PDT 24 Aug 11 07:01:46 PM PDT 24 25552210 ps
T97 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1575643842 Aug 11 07:01:26 PM PDT 24 Aug 11 07:01:32 PM PDT 24 635246945 ps
T589 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.583234827 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:39 PM PDT 24 19141599 ps
T590 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2822465111 Aug 11 07:01:34 PM PDT 24 Aug 11 07:01:36 PM PDT 24 90767681 ps
T103 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1721278948 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:40 PM PDT 24 57648076 ps
T591 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1189510053 Aug 11 07:01:11 PM PDT 24 Aug 11 07:01:12 PM PDT 24 75495752 ps
T592 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.98534084 Aug 11 07:01:31 PM PDT 24 Aug 11 07:01:32 PM PDT 24 142599019 ps
T593 /workspace/coverage/cover_reg_top/14.hmac_intr_test.652118923 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:31 PM PDT 24 20278003 ps
T594 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3125246785 Aug 11 07:01:47 PM PDT 24 Aug 11 07:01:48 PM PDT 24 124914005 ps
T595 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1782274898 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:22 PM PDT 24 153330988 ps
T596 /workspace/coverage/cover_reg_top/32.hmac_intr_test.511692568 Aug 11 07:01:49 PM PDT 24 Aug 11 07:01:49 PM PDT 24 16442673 ps
T98 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2746489708 Aug 11 07:01:22 PM PDT 24 Aug 11 07:01:26 PM PDT 24 116756609 ps
T597 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3087915458 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:43 PM PDT 24 234991591 ps
T598 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3427122468 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:43 PM PDT 24 50581308 ps
T599 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3404329489 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:41 PM PDT 24 11340642 ps
T600 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.790671447 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:21 PM PDT 24 413830148 ps
T601 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2074280906 Aug 11 07:01:23 PM PDT 24 Aug 11 07:01:25 PM PDT 24 45175802 ps
T602 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1840438451 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:47 PM PDT 24 24523249 ps
T100 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.889917756 Aug 11 07:01:14 PM PDT 24 Aug 11 07:01:24 PM PDT 24 208978567 ps
T99 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1172291597 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:21 PM PDT 24 96661182 ps
T603 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1629419430 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:33 PM PDT 24 164628961 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2880927256 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:30 PM PDT 24 280969813 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2315605968 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:21 PM PDT 24 149493291 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3581329462 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:34 PM PDT 24 1394116490 ps
T606 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.663008691 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:32 PM PDT 24 518514007 ps
T607 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3779838766 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:42 PM PDT 24 27360925 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2972438843 Aug 11 07:01:18 PM PDT 24 Aug 11 07:01:19 PM PDT 24 14588971 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1943745509 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:21 PM PDT 24 79744197 ps
T125 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3814132017 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:26 PM PDT 24 1172242224 ps
T610 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3427873086 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:31 PM PDT 24 127604441 ps
T611 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.362166714 Aug 11 07:01:32 PM PDT 24 Aug 11 07:01:35 PM PDT 24 688977747 ps
T612 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3175728038 Aug 11 07:01:11 PM PDT 24 Aug 11 07:01:12 PM PDT 24 25107841 ps
T126 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.225805714 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:43 PM PDT 24 52931315 ps
T613 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.347096140 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:32 PM PDT 24 67881934 ps
T102 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2696220479 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:30 PM PDT 24 3902364925 ps
T614 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2091123848 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:31 PM PDT 24 47038422 ps
T121 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3811333580 Aug 11 07:01:30 PM PDT 24 Aug 11 07:01:32 PM PDT 24 1832391793 ps
T615 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3962588518 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:30 PM PDT 24 62726567 ps
T616 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3510535645 Aug 11 07:01:48 PM PDT 24 Aug 11 07:01:48 PM PDT 24 15530422 ps
T128 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.795885537 Aug 11 07:01:24 PM PDT 24 Aug 11 07:01:28 PM PDT 24 511474136 ps
T617 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3867864305 Aug 11 07:01:24 PM PDT 24 Aug 11 07:01:24 PM PDT 24 49122687 ps
T618 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2538533984 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:32 PM PDT 24 810712272 ps
T619 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1531475515 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:41 PM PDT 24 20692370 ps
T620 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3622548730 Aug 11 07:01:41 PM PDT 24 Aug 11 07:01:42 PM PDT 24 12319966 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2251450091 Aug 11 07:01:32 PM PDT 24 Aug 11 07:01:34 PM PDT 24 30828729 ps
T622 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3153506307 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:34 PM PDT 24 18900711 ps
T623 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1022166983 Aug 11 07:01:42 PM PDT 24 Aug 11 07:01:44 PM PDT 24 110105905 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2809360450 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:30 PM PDT 24 65131165 ps
T625 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2749968172 Aug 11 07:01:47 PM PDT 24 Aug 11 07:01:48 PM PDT 24 15472623 ps
T626 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3383356436 Aug 11 07:01:33 PM PDT 24 Aug 11 07:01:35 PM PDT 24 38394002 ps
T627 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2003881440 Aug 11 07:01:10 PM PDT 24 Aug 11 07:01:10 PM PDT 24 25830674 ps
T628 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3930934111 Aug 11 07:01:11 PM PDT 24 Aug 11 07:01:16 PM PDT 24 857947282 ps
T122 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1406517677 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:23 PM PDT 24 548053452 ps
T629 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3718454293 Aug 11 07:01:24 PM PDT 24 Aug 11 07:01:27 PM PDT 24 515245666 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2861155410 Aug 11 07:01:34 PM PDT 24 Aug 11 07:01:35 PM PDT 24 712555532 ps
T631 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3195901449 Aug 11 07:01:47 PM PDT 24 Aug 11 07:01:48 PM PDT 24 60014677 ps
T632 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2186970720 Aug 11 07:01:26 PM PDT 24 Aug 11 07:01:27 PM PDT 24 114765019 ps
T633 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2909284267 Aug 11 07:01:42 PM PDT 24 Aug 11 07:01:43 PM PDT 24 35744431 ps
T634 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2248154629 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:31 PM PDT 24 39213055 ps
T635 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2471980162 Aug 11 07:01:14 PM PDT 24 Aug 11 07:01:17 PM PDT 24 879646947 ps
T636 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3795773023 Aug 11 07:01:34 PM PDT 24 Aug 11 07:01:35 PM PDT 24 30909373 ps
T637 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1948447202 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:21 PM PDT 24 118029953 ps
T638 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1653062344 Aug 11 07:01:24 PM PDT 24 Aug 11 07:01:27 PM PDT 24 46405017 ps
T639 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.992346518 Aug 11 07:01:29 PM PDT 24 Aug 11 07:10:56 PM PDT 24 38666758807 ps
T640 /workspace/coverage/cover_reg_top/38.hmac_intr_test.222605883 Aug 11 07:01:45 PM PDT 24 Aug 11 07:01:45 PM PDT 24 12864762 ps
T641 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.690047456 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:23 PM PDT 24 38562271 ps
T642 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.657248949 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:43 PM PDT 24 122198580 ps
T64 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2885135491 Aug 11 07:01:40 PM PDT 24 Aug 11 07:01:43 PM PDT 24 653905369 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2626477735 Aug 11 07:01:27 PM PDT 24 Aug 11 07:01:28 PM PDT 24 161036978 ps
T644 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3961770257 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:32 PM PDT 24 170782292 ps
T645 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1150428526 Aug 11 07:01:39 PM PDT 24 Aug 11 07:01:42 PM PDT 24 135512702 ps
T646 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1863910377 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:28 PM PDT 24 313461306 ps
T647 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2728644191 Aug 11 07:01:26 PM PDT 24 Aug 11 07:01:27 PM PDT 24 259329887 ps
T648 /workspace/coverage/cover_reg_top/40.hmac_intr_test.391896107 Aug 11 07:01:49 PM PDT 24 Aug 11 07:01:50 PM PDT 24 14007209 ps
T649 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.368917676 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:23 PM PDT 24 134225790 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4037065674 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:29 PM PDT 24 22844110 ps
T651 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3573145017 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:47 PM PDT 24 15326599 ps
T652 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.841846080 Aug 11 07:01:28 PM PDT 24 Aug 11 07:01:31 PM PDT 24 378694801 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1078570222 Aug 11 07:01:21 PM PDT 24 Aug 11 07:01:23 PM PDT 24 84340342 ps
T654 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3265660280 Aug 11 07:01:23 PM PDT 24 Aug 11 07:01:24 PM PDT 24 67740072 ps
T655 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1825634112 Aug 11 07:01:46 PM PDT 24 Aug 11 07:01:49 PM PDT 24 223314802 ps
T656 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2792574497 Aug 11 07:01:22 PM PDT 24 Aug 11 07:01:23 PM PDT 24 18732310 ps
T657 /workspace/coverage/cover_reg_top/3.hmac_intr_test.765696767 Aug 11 07:01:20 PM PDT 24 Aug 11 07:01:21 PM PDT 24 35825991 ps
T658 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.14706063 Aug 11 07:01:23 PM PDT 24 Aug 11 07:01:25 PM PDT 24 185135554 ps
T659 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2600228120 Aug 11 07:01:42 PM PDT 24 Aug 11 07:01:43 PM PDT 24 17369063 ps
T660 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1022077170 Aug 11 07:01:29 PM PDT 24 Aug 11 07:01:31 PM PDT 24 588124549 ps

Test location /workspace/coverage/default/2.hmac_datapath_stress.2638969305
Short name T1
Test name
Test status
Simulation time 15203378065 ps
CPU time 769.33 seconds
Started Aug 11 07:02:27 PM PDT 24
Finished Aug 11 07:15:17 PM PDT 24
Peak memory 677708 kb
Host smart-29fd47d1-3f0b-4955-99df-a8787f14fbd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638969305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2638969305
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3025520026
Short name T4
Test name
Test status
Simulation time 4041998434 ps
CPU time 61.59 seconds
Started Aug 11 07:03:28 PM PDT 24
Finished Aug 11 07:04:30 PM PDT 24
Peak memory 216236 kb
Host smart-c6f82d54-6baf-4c70-ae02-9db88af0e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025520026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3025520026
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2942666782
Short name T9
Test name
Test status
Simulation time 103431508546 ps
CPU time 6901.76 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 08:57:42 PM PDT 24
Peak memory 738448 kb
Host smart-4b41ce18-3ff4-4972-b72e-f3ec1674f334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942666782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2942666782
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2817355253
Short name T11
Test name
Test status
Simulation time 57768559764 ps
CPU time 467.31 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:12:04 PM PDT 24
Peak memory 199892 kb
Host smart-706f275d-fd7a-469e-b4e7-cd8938653ccd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817355253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2817355253
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.878178156
Short name T63
Test name
Test status
Simulation time 223480113 ps
CPU time 3.14 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200100 kb
Host smart-33d4469e-3d7e-45c2-b99f-6b9393ba8ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878178156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.878178156
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3793983807
Short name T32
Test name
Test status
Simulation time 333895904 ps
CPU time 0.97 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:02:29 PM PDT 24
Peak memory 219640 kb
Host smart-fcd354f8-410e-4050-967f-f28964d0decc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793983807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3793983807
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1036518971
Short name T8
Test name
Test status
Simulation time 62823436255 ps
CPU time 1586.15 seconds
Started Aug 11 07:02:41 PM PDT 24
Finished Aug 11 07:29:07 PM PDT 24
Peak memory 718972 kb
Host smart-fc045d89-510c-4490-9b2c-a6e330768ebe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036518971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1036518971
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2377494942
Short name T16
Test name
Test status
Simulation time 4350615981 ps
CPU time 41.8 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:03:18 PM PDT 24
Peak memory 199932 kb
Host smart-a6b9e5cf-1088-408a-bd2c-a2c34a844e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377494942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2377494942
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2557844010
Short name T28
Test name
Test status
Simulation time 1859626225 ps
CPU time 100.16 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:04:34 PM PDT 24
Peak memory 199832 kb
Host smart-dc598394-ffa5-4ba3-9f2f-676a5b8d8ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557844010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2557844010
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2685407581
Short name T388
Test name
Test status
Simulation time 47472436613 ps
CPU time 533.04 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:11:50 PM PDT 24
Peak memory 320524 kb
Host smart-ab1bd151-dec8-4d15-8a66-1dac094a6a56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685407581 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2685407581
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2380383792
Short name T167
Test name
Test status
Simulation time 2535959655 ps
CPU time 149.84 seconds
Started Aug 11 07:03:40 PM PDT 24
Finished Aug 11 07:06:09 PM PDT 24
Peak memory 200068 kb
Host smart-19c9d1d4-0c8e-43d1-ad2b-257625d8b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380383792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2380383792
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.805733810
Short name T90
Test name
Test status
Simulation time 16469073 ps
CPU time 0.88 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 199676 kb
Host smart-faa77a5e-702b-45b7-946e-e93f1c0428a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805733810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.805733810
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.795885537
Short name T128
Test name
Test status
Simulation time 511474136 ps
CPU time 4.1 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 200148 kb
Host smart-a813e2e7-9a79-485d-a262-12b39d607428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795885537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.795885537
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_alert_test.58714649
Short name T160
Test name
Test status
Simulation time 46029329 ps
CPU time 0.56 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:02:53 PM PDT 24
Peak memory 195636 kb
Host smart-8bd6ab11-2ab8-46d1-af1e-b3c633415afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58714649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.58714649
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3811333580
Short name T121
Test name
Test status
Simulation time 1832391793 ps
CPU time 1.89 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200136 kb
Host smart-7d1bc1e6-d4eb-4dc3-af3c-f9cc883f2539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811333580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3811333580
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/34.hmac_stress_all.826284093
Short name T295
Test name
Test status
Simulation time 26116580385 ps
CPU time 2176.06 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:39:50 PM PDT 24
Peak memory 777808 kb
Host smart-a95663e2-d9db-4f9b-8e27-580ec5da12ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826284093 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.826284093
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_smoke.541393176
Short name T138
Test name
Test status
Simulation time 3990731038 ps
CPU time 10.84 seconds
Started Aug 11 07:02:50 PM PDT 24
Finished Aug 11 07:03:01 PM PDT 24
Peak memory 199960 kb
Host smart-8728f94f-d48b-4fa2-95b2-5d8582fb9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541393176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.541393176
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2885135491
Short name T64
Test name
Test status
Simulation time 653905369 ps
CPU time 3.13 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200212 kb
Host smart-eb5c9155-d51b-44ef-8dde-9a9a33e7d785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885135491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2885135491
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2230595704
Short name T265
Test name
Test status
Simulation time 892022547 ps
CPU time 51.75 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:03:46 PM PDT 24
Peak memory 199800 kb
Host smart-c8af4dab-b7fc-4ce1-a9fa-cf6a17d6cbd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230595704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2230595704
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1863910377
Short name T646
Test name
Test status
Simulation time 313461306 ps
CPU time 7.5 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 200124 kb
Host smart-63c3c497-e386-4ae2-922b-2cdc23276d9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863910377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1863910377
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2696220479
Short name T102
Test name
Test status
Simulation time 3902364925 ps
CPU time 11.47 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 200232 kb
Host smart-da71db5c-5628-48aa-9fb8-55398726f6f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696220479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2696220479
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1189510053
Short name T591
Test name
Test status
Simulation time 75495752 ps
CPU time 0.74 seconds
Started Aug 11 07:01:11 PM PDT 24
Finished Aug 11 07:01:12 PM PDT 24
Peak memory 197740 kb
Host smart-10668e27-07b6-4950-885b-9216af7c6c38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189510053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1189510053
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1526348324
Short name T542
Test name
Test status
Simulation time 199065353 ps
CPU time 1.48 seconds
Started Aug 11 07:01:11 PM PDT 24
Finished Aug 11 07:01:13 PM PDT 24
Peak memory 200172 kb
Host smart-199ad6ff-4d6f-4b00-8027-717cc7c75c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526348324 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1526348324
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3175728038
Short name T612
Test name
Test status
Simulation time 25107841 ps
CPU time 0.86 seconds
Started Aug 11 07:01:11 PM PDT 24
Finished Aug 11 07:01:12 PM PDT 24
Peak memory 199432 kb
Host smart-d65c05d4-2a79-4dd6-8343-1ff2cfbe0a17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175728038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3175728038
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2972438843
Short name T608
Test name
Test status
Simulation time 14588971 ps
CPU time 0.58 seconds
Started Aug 11 07:01:18 PM PDT 24
Finished Aug 11 07:01:19 PM PDT 24
Peak memory 195148 kb
Host smart-1139f320-b4df-46d3-ab58-2c5c0b2e5e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972438843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2972438843
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1782274898
Short name T595
Test name
Test status
Simulation time 153330988 ps
CPU time 2.41 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:22 PM PDT 24
Peak memory 200196 kb
Host smart-9e75bbb7-d696-463d-9d44-be09b1a13ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782274898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1782274898
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2094199842
Short name T573
Test name
Test status
Simulation time 33219483 ps
CPU time 1.57 seconds
Started Aug 11 07:01:12 PM PDT 24
Finished Aug 11 07:01:13 PM PDT 24
Peak memory 200128 kb
Host smart-89df7565-e535-4583-834d-a3eb4e7267e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094199842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2094199842
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2471980162
Short name T635
Test name
Test status
Simulation time 879646947 ps
CPU time 3.06 seconds
Started Aug 11 07:01:14 PM PDT 24
Finished Aug 11 07:01:17 PM PDT 24
Peak memory 200120 kb
Host smart-30655034-8ae0-4645-a7fd-13d7329801b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471980162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2471980162
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1872042601
Short name T91
Test name
Test status
Simulation time 833528127 ps
CPU time 3.53 seconds
Started Aug 11 07:01:12 PM PDT 24
Finished Aug 11 07:01:15 PM PDT 24
Peak memory 199964 kb
Host smart-2ff398c4-a6ae-489b-8511-c45bb5d86535
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872042601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1872042601
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.889917756
Short name T100
Test name
Test status
Simulation time 208978567 ps
CPU time 9.71 seconds
Started Aug 11 07:01:14 PM PDT 24
Finished Aug 11 07:01:24 PM PDT 24
Peak memory 200144 kb
Host smart-d29d4b19-37c8-4697-8066-1220e84252f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889917756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.889917756
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1807822488
Short name T557
Test name
Test status
Simulation time 19972350 ps
CPU time 0.81 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:20 PM PDT 24
Peak memory 199388 kb
Host smart-a15f476a-dde5-4836-b0a2-813af33ce711
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807822488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1807822488
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.790671447
Short name T600
Test name
Test status
Simulation time 413830148 ps
CPU time 1.88 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 200180 kb
Host smart-42ff91d1-2b38-4f09-a994-f9903a8bccd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790671447 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.790671447
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.646807463
Short name T548
Test name
Test status
Simulation time 24686667 ps
CPU time 0.8 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:22 PM PDT 24
Peak memory 199668 kb
Host smart-c1595ea7-caaa-4427-8ff0-438b8b240246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646807463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.646807463
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2533260509
Short name T553
Test name
Test status
Simulation time 16395593 ps
CPU time 0.61 seconds
Started Aug 11 07:01:12 PM PDT 24
Finished Aug 11 07:01:12 PM PDT 24
Peak memory 195112 kb
Host smart-502bda39-b615-4098-b9fd-d78ea3d0d93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533260509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2533260509
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1078570222
Short name T653
Test name
Test status
Simulation time 84340342 ps
CPU time 1.61 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:23 PM PDT 24
Peak memory 200248 kb
Host smart-2b2ec789-5d27-4a45-af9d-2c42c04528ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078570222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1078570222
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3930934111
Short name T628
Test name
Test status
Simulation time 857947282 ps
CPU time 4.31 seconds
Started Aug 11 07:01:11 PM PDT 24
Finished Aug 11 07:01:16 PM PDT 24
Peak memory 200168 kb
Host smart-3f142ac8-4aac-4ad3-b54e-bdc5bd6d254d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930934111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3930934111
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1406517677
Short name T122
Test name
Test status
Simulation time 548053452 ps
CPU time 3.22 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:23 PM PDT 24
Peak memory 200212 kb
Host smart-d1d5769e-9534-4110-9157-18020827cf7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406517677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1406517677
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3427873086
Short name T610
Test name
Test status
Simulation time 127604441 ps
CPU time 1.29 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200024 kb
Host smart-bd32e1e8-0de5-49e6-a585-7f0d3e0dcf0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427873086 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3427873086
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3867864305
Short name T617
Test name
Test status
Simulation time 49122687 ps
CPU time 0.82 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:24 PM PDT 24
Peak memory 199580 kb
Host smart-c7902bc3-06f3-4e63-9823-8c2a59f9f9db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867864305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3867864305
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2738124352
Short name T547
Test name
Test status
Simulation time 29894895 ps
CPU time 0.56 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:29 PM PDT 24
Peak memory 195020 kb
Host smart-b9f2cfd1-28f0-4497-b168-a826c662545a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738124352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2738124352
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3079300807
Short name T109
Test name
Test status
Simulation time 177310296 ps
CPU time 1.61 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 200112 kb
Host smart-6d71d991-90a0-4ef1-99a2-4918b214d763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079300807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3079300807
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2728644191
Short name T647
Test name
Test status
Simulation time 259329887 ps
CPU time 1.77 seconds
Started Aug 11 07:01:26 PM PDT 24
Finished Aug 11 07:01:27 PM PDT 24
Peak memory 200140 kb
Host smart-2f851cf6-4341-4469-a239-1230b7ea5d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728644191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2728644191
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.126082887
Short name T62
Test name
Test status
Simulation time 149584684 ps
CPU time 3.16 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 200096 kb
Host smart-ee22defc-7ca6-48bc-a1c7-40c821cc3f6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126082887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.126082887
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1022077170
Short name T660
Test name
Test status
Simulation time 588124549 ps
CPU time 2.4 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200328 kb
Host smart-9c155258-a079-4793-87c3-c162e82d1730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022077170 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1022077170
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2091123848
Short name T614
Test name
Test status
Simulation time 47038422 ps
CPU time 0.58 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 194932 kb
Host smart-642a92da-67da-4c85-a5ef-8a72b437db1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091123848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2091123848
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.98534084
Short name T592
Test name
Test status
Simulation time 142599019 ps
CPU time 1.77 seconds
Started Aug 11 07:01:31 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200236 kb
Host smart-6be9940f-aac0-4962-a38f-54c8e7920879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98534084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_
outstanding.98534084
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2023252854
Short name T539
Test name
Test status
Simulation time 444262794 ps
CPU time 2.98 seconds
Started Aug 11 07:01:31 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 200080 kb
Host smart-754a4add-586e-47ef-94f9-f29f660ff65b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023252854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2023252854
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.992346518
Short name T639
Test name
Test status
Simulation time 38666758807 ps
CPU time 567.14 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:10:56 PM PDT 24
Peak memory 216564 kb
Host smart-620d3fb0-0685-482e-a945-26e848d5afb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992346518 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.992346518
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2809360450
Short name T624
Test name
Test status
Simulation time 65131165 ps
CPU time 0.88 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 199544 kb
Host smart-e6f3b89a-a873-4679-bf28-330bee88ac2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809360450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2809360450
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1531475515
Short name T619
Test name
Test status
Simulation time 20692370 ps
CPU time 0.58 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 195172 kb
Host smart-50dc7387-3996-44df-a8dc-be423969dd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531475515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1531475515
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3962588518
Short name T615
Test name
Test status
Simulation time 62726567 ps
CPU time 1.75 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 200236 kb
Host smart-b4d382f7-bab0-4b28-b495-b63d7cef97be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962588518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3962588518
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3105587715
Short name T580
Test name
Test status
Simulation time 35214488 ps
CPU time 1.34 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200152 kb
Host smart-c9125433-ff56-4ec0-a45e-2b3d1c272fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105587715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3105587715
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.225805714
Short name T126
Test name
Test status
Simulation time 52931315 ps
CPU time 1.73 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200208 kb
Host smart-b2c4d7d2-67b4-44e6-adad-40061da88aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225805714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.225805714
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.841846080
Short name T652
Test name
Test status
Simulation time 378694801 ps
CPU time 2.6 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 216332 kb
Host smart-86a863ba-4d2b-4737-a1dc-8fb3df6a9998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841846080 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.841846080
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.495254448
Short name T537
Test name
Test status
Simulation time 49796544 ps
CPU time 0.69 seconds
Started Aug 11 07:01:43 PM PDT 24
Finished Aug 11 07:01:44 PM PDT 24
Peak memory 197680 kb
Host smart-d4eb2c31-ed07-4cca-9fdc-6abd76a046a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495254448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.495254448
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4037065674
Short name T650
Test name
Test status
Simulation time 22844110 ps
CPU time 0.59 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:29 PM PDT 24
Peak memory 195272 kb
Host smart-a1be3fdc-04d0-42c9-85f4-0683b625787b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037065674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4037065674
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2595745752
Short name T110
Test name
Test status
Simulation time 766526167 ps
CPU time 1.06 seconds
Started Aug 11 07:01:32 PM PDT 24
Finished Aug 11 07:01:33 PM PDT 24
Peak memory 199016 kb
Host smart-d82d717b-47b7-4b53-b519-fb5f424e8534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595745752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2595745752
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1246405931
Short name T567
Test name
Test status
Simulation time 772396685 ps
CPU time 2.95 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:33 PM PDT 24
Peak memory 200136 kb
Host smart-81dd5395-4caf-418c-b768-0d0322a6e189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246405931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1246405931
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1985854182
Short name T119
Test name
Test status
Simulation time 588679171 ps
CPU time 2.86 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200184 kb
Host smart-0f18ec79-dd65-4c93-8df3-3481cf6f55c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985854182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1985854182
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.37840183
Short name T545
Test name
Test status
Simulation time 273992602 ps
CPU time 1.74 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 200136 kb
Host smart-f042a216-be81-474e-a403-0aeeff6fa45e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840183 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.37840183
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3035785994
Short name T576
Test name
Test status
Simulation time 103719962 ps
CPU time 0.95 seconds
Started Aug 11 07:01:31 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 199920 kb
Host smart-d7df06b4-36f2-477e-8ee1-e6bc217f72e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035785994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3035785994
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.652118923
Short name T593
Test name
Test status
Simulation time 20278003 ps
CPU time 0.58 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 195024 kb
Host smart-df93f321-b3fe-485a-a176-10d38f6849e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652118923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.652118923
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1825634112
Short name T655
Test name
Test status
Simulation time 223314802 ps
CPU time 2.19 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:49 PM PDT 24
Peak memory 200208 kb
Host smart-5194d7d9-e24b-428b-91b0-f0ec932465ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825634112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1825634112
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.347096140
Short name T613
Test name
Test status
Simulation time 67881934 ps
CPU time 3.35 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200160 kb
Host smart-15fcc0cb-7005-4e72-967a-29ba430e66e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347096140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.347096140
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3427122468
Short name T598
Test name
Test status
Simulation time 50581308 ps
CPU time 1.74 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200164 kb
Host smart-0bbea74a-7a2e-40ee-a3f0-a8e3173bf4c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427122468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3427122468
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2861155410
Short name T630
Test name
Test status
Simulation time 712555532 ps
CPU time 1.25 seconds
Started Aug 11 07:01:34 PM PDT 24
Finished Aug 11 07:01:35 PM PDT 24
Peak memory 199980 kb
Host smart-ea64536a-70d8-456a-982b-3dfb636b0a32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861155410 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2861155410
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3795773023
Short name T636
Test name
Test status
Simulation time 30909373 ps
CPU time 0.7 seconds
Started Aug 11 07:01:34 PM PDT 24
Finished Aug 11 07:01:35 PM PDT 24
Peak memory 197840 kb
Host smart-c6e4526c-d7a2-4562-a4f1-6b9fbb95fab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795773023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3795773023
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3670678659
Short name T581
Test name
Test status
Simulation time 14353638 ps
CPU time 0.58 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 195072 kb
Host smart-6da2cc03-769f-4b40-b2d3-bb5e9263e9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670678659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3670678659
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3013419110
Short name T585
Test name
Test status
Simulation time 80035733 ps
CPU time 1.06 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:42 PM PDT 24
Peak memory 198824 kb
Host smart-adb45474-dfe0-406e-b874-500c5adfbc82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013419110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3013419110
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.347095627
Short name T578
Test name
Test status
Simulation time 115702228 ps
CPU time 1.54 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200180 kb
Host smart-6155a8c7-0327-488f-a2c0-214e62965a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347095627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.347095627
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3383356436
Short name T626
Test name
Test status
Simulation time 38394002 ps
CPU time 1.27 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:35 PM PDT 24
Peak memory 200076 kb
Host smart-669fe77e-3cad-432c-bd9b-4b7651aaf40d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383356436 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3383356436
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.433154363
Short name T93
Test name
Test status
Simulation time 65272210 ps
CPU time 0.89 seconds
Started Aug 11 07:01:36 PM PDT 24
Finished Aug 11 07:01:37 PM PDT 24
Peak memory 199864 kb
Host smart-5e34e1a8-f562-4ede-b0e2-cac3ec6f72f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433154363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.433154363
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3519067969
Short name T538
Test name
Test status
Simulation time 12065627 ps
CPU time 0.58 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 195032 kb
Host smart-fc98082f-2cfc-4fd7-b4fb-6e60ae1551e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519067969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3519067969
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1183156248
Short name T108
Test name
Test status
Simulation time 21951559 ps
CPU time 1.12 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 198776 kb
Host smart-6ba0f43a-89ec-4d7d-8897-34a9fdd16df0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183156248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1183156248
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.362166714
Short name T611
Test name
Test status
Simulation time 688977747 ps
CPU time 3.26 seconds
Started Aug 11 07:01:32 PM PDT 24
Finished Aug 11 07:01:35 PM PDT 24
Peak memory 200228 kb
Host smart-312e0b1f-a312-48c6-a67a-4ea3a6b52a59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362166714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.362166714
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2667128296
Short name T120
Test name
Test status
Simulation time 223813801 ps
CPU time 4.33 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:37 PM PDT 24
Peak memory 200192 kb
Host smart-0fe4bad4-cdd6-4df7-82ba-01e7c3fcb063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667128296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2667128296
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1022166983
Short name T623
Test name
Test status
Simulation time 110105905 ps
CPU time 1.79 seconds
Started Aug 11 07:01:42 PM PDT 24
Finished Aug 11 07:01:44 PM PDT 24
Peak memory 200236 kb
Host smart-320351f2-0913-4bf7-85bf-0a317d7d07ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022166983 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1022166983
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3153506307
Short name T622
Test name
Test status
Simulation time 18900711 ps
CPU time 0.92 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 199816 kb
Host smart-cd05aa6d-e7ca-4e21-977c-fde32ae1b3bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153506307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3153506307
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1629419430
Short name T603
Test name
Test status
Simulation time 164628961 ps
CPU time 0.61 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:33 PM PDT 24
Peak memory 195020 kb
Host smart-f932c5f2-a107-42ea-822f-72ab18452e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629419430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1629419430
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2822465111
Short name T590
Test name
Test status
Simulation time 90767681 ps
CPU time 2.19 seconds
Started Aug 11 07:01:34 PM PDT 24
Finished Aug 11 07:01:36 PM PDT 24
Peak memory 200152 kb
Host smart-e46425a8-426c-45cb-afb4-06040ee2b258
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822465111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2822465111
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2251450091
Short name T621
Test name
Test status
Simulation time 30828729 ps
CPU time 1.43 seconds
Started Aug 11 07:01:32 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 200088 kb
Host smart-88d5588f-1ed5-4875-a92c-dd9a0e1eb1da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251450091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2251450091
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.205302357
Short name T118
Test name
Test status
Simulation time 617910989 ps
CPU time 3.23 seconds
Started Aug 11 07:01:33 PM PDT 24
Finished Aug 11 07:01:36 PM PDT 24
Peak memory 200156 kb
Host smart-927d3202-7b70-47cd-826e-20c0bd8c6b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205302357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.205302357
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1262500252
Short name T540
Test name
Test status
Simulation time 226180452338 ps
CPU time 2189.96 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:38:10 PM PDT 24
Peak memory 228160 kb
Host smart-2b1667af-2291-4a53-b988-0782ff6cbfd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262500252 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1262500252
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.583234827
Short name T589
Test name
Test status
Simulation time 19141599 ps
CPU time 0.69 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:39 PM PDT 24
Peak memory 197820 kb
Host smart-48ca0f07-c74e-4b2a-85d8-28f1e93c83dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583234827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.583234827
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2630160666
Short name T560
Test name
Test status
Simulation time 25913680 ps
CPU time 0.56 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:40 PM PDT 24
Peak memory 194996 kb
Host smart-ecbf12f7-17b6-48a2-a27d-9ea4eeeaeecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630160666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2630160666
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2007032767
Short name T105
Test name
Test status
Simulation time 37406056 ps
CPU time 1.72 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200116 kb
Host smart-0fad537d-f728-4c56-80a2-e59df9dbefcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007032767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2007032767
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1150428526
Short name T645
Test name
Test status
Simulation time 135512702 ps
CPU time 2.97 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:42 PM PDT 24
Peak memory 200108 kb
Host smart-ae364ba4-b874-45fc-af93-d37af768ffc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150428526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1150428526
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.4112481822
Short name T558
Test name
Test status
Simulation time 100014141 ps
CPU time 1.85 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 200092 kb
Host smart-fd84abe8-5ed6-4a7c-9f40-8d226c3df968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112481822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4112481822
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.410975078
Short name T561
Test name
Test status
Simulation time 1057042472 ps
CPU time 2.37 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 200192 kb
Host smart-5113cc7a-6796-4ceb-8d5b-9f0cf2db649c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410975078 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.410975078
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1721278948
Short name T103
Test name
Test status
Simulation time 57648076 ps
CPU time 0.96 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:40 PM PDT 24
Peak memory 199956 kb
Host smart-1eb7d159-ff04-4177-8b7f-96b3e18dad91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721278948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1721278948
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2192675739
Short name T536
Test name
Test status
Simulation time 16769533 ps
CPU time 0.62 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 195040 kb
Host smart-4373377b-60fc-4f58-bd47-59c0447af52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192675739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2192675739
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.657248949
Short name T642
Test name
Test status
Simulation time 122198580 ps
CPU time 2.29 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200168 kb
Host smart-b024059d-d0ff-4664-becb-622757c8f7c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657248949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.657248949
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.530679668
Short name T571
Test name
Test status
Simulation time 231445697 ps
CPU time 4.79 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:45 PM PDT 24
Peak memory 200048 kb
Host smart-1ae27c8a-c532-412f-b404-4b32491004c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530679668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.530679668
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3087915458
Short name T597
Test name
Test status
Simulation time 234991591 ps
CPU time 1.87 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200120 kb
Host smart-329955c5-4c3e-4c3b-afef-4423c6714712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087915458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3087915458
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3724912407
Short name T552
Test name
Test status
Simulation time 224012257 ps
CPU time 3.21 seconds
Started Aug 11 07:01:22 PM PDT 24
Finished Aug 11 07:01:25 PM PDT 24
Peak memory 199048 kb
Host smart-27890c1e-635f-4eb6-bbdb-f7056aed2f55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724912407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3724912407
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3850866845
Short name T96
Test name
Test status
Simulation time 499836494 ps
CPU time 13.94 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:35 PM PDT 24
Peak memory 200052 kb
Host smart-93f7744b-1243-44e3-9076-d8f8abda9288
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850866845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3850866845
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3695136767
Short name T94
Test name
Test status
Simulation time 69235839 ps
CPU time 0.73 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:20 PM PDT 24
Peak memory 197960 kb
Host smart-d7b9ce7f-60bc-4d59-bc8b-b9ad55de6ef1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695136767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3695136767
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1948447202
Short name T637
Test name
Test status
Simulation time 118029953 ps
CPU time 1.69 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 200148 kb
Host smart-c4fcdb4f-1c25-401f-8ced-8618753b066f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948447202 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1948447202
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1172291597
Short name T99
Test name
Test status
Simulation time 96661182 ps
CPU time 0.8 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 199432 kb
Host smart-17f2ede3-6fb5-4fc7-8c81-742425df84fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172291597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1172291597
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2003881440
Short name T627
Test name
Test status
Simulation time 25830674 ps
CPU time 0.57 seconds
Started Aug 11 07:01:10 PM PDT 24
Finished Aug 11 07:01:10 PM PDT 24
Peak memory 195120 kb
Host smart-adec757d-7cec-4a24-bc82-4cb1710aab15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003881440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2003881440
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.368917676
Short name T649
Test name
Test status
Simulation time 134225790 ps
CPU time 2.27 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:23 PM PDT 24
Peak memory 200084 kb
Host smart-b207ff77-b3de-4d9a-8204-d2b4de38a5a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368917676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.368917676
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1078239028
Short name T541
Test name
Test status
Simulation time 155841608 ps
CPU time 3.05 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:24 PM PDT 24
Peak memory 200132 kb
Host smart-73e70e3c-e72d-4bd6-8f4b-03ab5bf08009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078239028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1078239028
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.137448888
Short name T127
Test name
Test status
Simulation time 105921063 ps
CPU time 2.83 seconds
Started Aug 11 07:01:10 PM PDT 24
Finished Aug 11 07:01:13 PM PDT 24
Peak memory 200208 kb
Host smart-84637471-474a-4adf-843f-d7858ab79979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137448888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.137448888
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3937517300
Short name T566
Test name
Test status
Simulation time 14325581 ps
CPU time 0.64 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 195176 kb
Host smart-7680c63e-5294-455e-938a-9be582091c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937517300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3937517300
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3784196341
Short name T569
Test name
Test status
Simulation time 12419197 ps
CPU time 0.56 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:40 PM PDT 24
Peak memory 195044 kb
Host smart-8ee1591c-9a83-45eb-805f-4af56181d40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784196341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3784196341
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2750069488
Short name T563
Test name
Test status
Simulation time 13866833 ps
CPU time 0.59 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:40 PM PDT 24
Peak memory 194976 kb
Host smart-7fab3c31-9fff-415a-808d-a74c9682afdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750069488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2750069488
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3622548730
Short name T620
Test name
Test status
Simulation time 12319966 ps
CPU time 0.62 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:42 PM PDT 24
Peak memory 195100 kb
Host smart-698fa055-301f-4919-9d0d-ac4656647c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622548730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3622548730
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2600228120
Short name T659
Test name
Test status
Simulation time 17369063 ps
CPU time 0.6 seconds
Started Aug 11 07:01:42 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 195096 kb
Host smart-48e367fe-5867-43ad-bdda-dcdf9e96682a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600228120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2600228120
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2642409379
Short name T565
Test name
Test status
Simulation time 43546059 ps
CPU time 0.57 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 195100 kb
Host smart-773345d1-dd8c-4c67-ae5e-87d8717878aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642409379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2642409379
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3779838766
Short name T607
Test name
Test status
Simulation time 27360925 ps
CPU time 0.61 seconds
Started Aug 11 07:01:41 PM PDT 24
Finished Aug 11 07:01:42 PM PDT 24
Peak memory 195100 kb
Host smart-9923974b-5198-4bec-811e-8dfb9e4dd904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779838766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3779838766
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2995681865
Short name T550
Test name
Test status
Simulation time 48895028 ps
CPU time 0.58 seconds
Started Aug 11 07:01:39 PM PDT 24
Finished Aug 11 07:01:40 PM PDT 24
Peak memory 195052 kb
Host smart-aa537fa8-9a6a-4d37-ae70-7ba1b40f30c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995681865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2995681865
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4225144907
Short name T584
Test name
Test status
Simulation time 12949298 ps
CPU time 0.6 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 195128 kb
Host smart-1ee09344-750b-4575-9076-98807b735480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225144907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4225144907
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2909284267
Short name T633
Test name
Test status
Simulation time 35744431 ps
CPU time 0.6 seconds
Started Aug 11 07:01:42 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 195040 kb
Host smart-e227548b-db15-424f-a78c-c487b8d5ebc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909284267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2909284267
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1575643842
Short name T97
Test name
Test status
Simulation time 635246945 ps
CPU time 5.75 seconds
Started Aug 11 07:01:26 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200132 kb
Host smart-7f453f9a-8172-4c4d-9695-ffb64d9c16db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575643842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1575643842
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2880927256
Short name T604
Test name
Test status
Simulation time 280969813 ps
CPU time 10.02 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 199256 kb
Host smart-4337efcf-9114-4c0a-a43c-ffad907570c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880927256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2880927256
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2315605968
Short name T605
Test name
Test status
Simulation time 149493291 ps
CPU time 0.83 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 199012 kb
Host smart-084634b8-b2eb-42e9-b8e7-fd7944013907
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315605968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2315605968
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.690047456
Short name T641
Test name
Test status
Simulation time 38562271 ps
CPU time 1.23 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:23 PM PDT 24
Peak memory 200052 kb
Host smart-fbcbdb7c-3328-410d-a12c-01369841185f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690047456 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.690047456
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2792574497
Short name T656
Test name
Test status
Simulation time 18732310 ps
CPU time 0.69 seconds
Started Aug 11 07:01:22 PM PDT 24
Finished Aug 11 07:01:23 PM PDT 24
Peak memory 197524 kb
Host smart-34851b44-ea06-4e8c-898e-3d7f84811de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792574497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2792574497
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.765696767
Short name T657
Test name
Test status
Simulation time 35825991 ps
CPU time 0.56 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 195028 kb
Host smart-c52efb20-01da-4086-8681-147e648b174b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765696767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.765696767
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2248154629
Short name T634
Test name
Test status
Simulation time 39213055 ps
CPU time 1.64 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200216 kb
Host smart-67f5883b-67c0-4934-a625-98d935ba72af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248154629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2248154629
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3556225502
Short name T534
Test name
Test status
Simulation time 521946043 ps
CPU time 2.8 seconds
Started Aug 11 07:01:22 PM PDT 24
Finished Aug 11 07:01:24 PM PDT 24
Peak memory 200096 kb
Host smart-92d6dbcd-814a-4433-883d-5f6ad22dedca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556225502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3556225502
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.531794065
Short name T123
Test name
Test status
Simulation time 58542492 ps
CPU time 1.69 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 200168 kb
Host smart-f9b26596-8c08-493e-bef1-3410a1258b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531794065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.531794065
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3404329489
Short name T599
Test name
Test status
Simulation time 11340642 ps
CPU time 0.59 seconds
Started Aug 11 07:01:40 PM PDT 24
Finished Aug 11 07:01:41 PM PDT 24
Peak memory 194968 kb
Host smart-ffeb4225-fcdc-4d23-aaf2-a65f8feddd95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404329489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3404329489
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1190264969
Short name T554
Test name
Test status
Simulation time 18401503 ps
CPU time 0.63 seconds
Started Aug 11 07:01:45 PM PDT 24
Finished Aug 11 07:01:46 PM PDT 24
Peak memory 195044 kb
Host smart-8885fd3a-e615-4325-a22e-1dc77a8657fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190264969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1190264969
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.511692568
Short name T596
Test name
Test status
Simulation time 16442673 ps
CPU time 0.6 seconds
Started Aug 11 07:01:49 PM PDT 24
Finished Aug 11 07:01:49 PM PDT 24
Peak memory 195236 kb
Host smart-d82469a2-8aa3-4e03-9a13-e13f5e35232c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511692568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.511692568
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.931681702
Short name T572
Test name
Test status
Simulation time 49549913 ps
CPU time 0.6 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:46 PM PDT 24
Peak memory 195180 kb
Host smart-5c790ce4-e2c6-4e9e-8ee8-6023dbe8e45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931681702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.931681702
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3510535645
Short name T616
Test name
Test status
Simulation time 15530422 ps
CPU time 0.59 seconds
Started Aug 11 07:01:48 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 194940 kb
Host smart-beef97d1-8234-48ba-a55c-d79807716d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510535645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3510535645
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3573145017
Short name T651
Test name
Test status
Simulation time 15326599 ps
CPU time 0.68 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:47 PM PDT 24
Peak memory 195044 kb
Host smart-03512036-3f09-4ea6-9270-b107b459ade2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573145017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3573145017
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2004558474
Short name T570
Test name
Test status
Simulation time 14718607 ps
CPU time 0.58 seconds
Started Aug 11 07:01:45 PM PDT 24
Finished Aug 11 07:01:46 PM PDT 24
Peak memory 195028 kb
Host smart-f285bad8-7bbe-40e3-a781-02f1bda7c6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004558474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2004558474
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2410592386
Short name T549
Test name
Test status
Simulation time 101314309 ps
CPU time 0.61 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:46 PM PDT 24
Peak memory 194988 kb
Host smart-346cdb3d-09e5-4020-9704-916a759eebc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410592386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2410592386
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.222605883
Short name T640
Test name
Test status
Simulation time 12864762 ps
CPU time 0.59 seconds
Started Aug 11 07:01:45 PM PDT 24
Finished Aug 11 07:01:45 PM PDT 24
Peak memory 195068 kb
Host smart-0de1f18e-7f63-4c3d-b34e-9397dd6d573e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222605883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.222605883
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2749968172
Short name T625
Test name
Test status
Simulation time 15472623 ps
CPU time 0.58 seconds
Started Aug 11 07:01:47 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 195128 kb
Host smart-f44f41e8-9ba3-45e2-91bd-87d0765bfb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749968172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2749968172
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2746489708
Short name T98
Test name
Test status
Simulation time 116756609 ps
CPU time 3.15 seconds
Started Aug 11 07:01:22 PM PDT 24
Finished Aug 11 07:01:26 PM PDT 24
Peak memory 200024 kb
Host smart-1641733b-f4ed-408d-acd0-28e7ae66e7b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746489708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2746489708
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3581329462
Short name T101
Test name
Test status
Simulation time 1394116490 ps
CPU time 13.91 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 199264 kb
Host smart-213668ba-fd4d-4083-843a-69ed8fbbf186
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581329462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3581329462
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2680791872
Short name T582
Test name
Test status
Simulation time 133294465 ps
CPU time 0.88 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:29 PM PDT 24
Peak memory 199376 kb
Host smart-0d5ec913-380b-4464-8a89-05c7a715d5f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680791872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2680791872
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1943745509
Short name T609
Test name
Test status
Simulation time 79744197 ps
CPU time 1.32 seconds
Started Aug 11 07:01:20 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 200188 kb
Host smart-6a8611ff-3622-4c2c-90aa-46c742a51db9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943745509 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1943745509
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3203417645
Short name T95
Test name
Test status
Simulation time 16354364 ps
CPU time 0.95 seconds
Started Aug 11 07:01:27 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 199980 kb
Host smart-75fdb494-587a-4a76-8560-841bf5aed542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203417645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3203417645
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3101213586
Short name T568
Test name
Test status
Simulation time 110066076 ps
CPU time 0.57 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:22 PM PDT 24
Peak memory 194976 kb
Host smart-b22b74ed-2f37-4aa3-8eb3-a1e46f5a3d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101213586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3101213586
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.97657545
Short name T107
Test name
Test status
Simulation time 358918510 ps
CPU time 1.67 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 200164 kb
Host smart-45f50494-af87-4889-b4c5-bb429e324e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97657545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_o
utstanding.97657545
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2626477735
Short name T643
Test name
Test status
Simulation time 161036978 ps
CPU time 1.74 seconds
Started Aug 11 07:01:27 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 200140 kb
Host smart-971c9fa0-4a42-49fa-84c9-a9458b844d34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626477735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2626477735
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.391896107
Short name T648
Test name
Test status
Simulation time 14007209 ps
CPU time 0.64 seconds
Started Aug 11 07:01:49 PM PDT 24
Finished Aug 11 07:01:50 PM PDT 24
Peak memory 195224 kb
Host smart-b4b2357c-6ba9-4695-8852-59c435ec28f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391896107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.391896107
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3195901449
Short name T631
Test name
Test status
Simulation time 60014677 ps
CPU time 0.6 seconds
Started Aug 11 07:01:47 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 195136 kb
Host smart-8b358af3-95aa-4a47-bf12-e9462a917bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195901449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3195901449
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1840438451
Short name T602
Test name
Test status
Simulation time 24523249 ps
CPU time 0.61 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:47 PM PDT 24
Peak memory 195076 kb
Host smart-a7a62ef4-8e01-45ae-bb73-33da0ca69602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840438451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1840438451
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.304853940
Short name T587
Test name
Test status
Simulation time 31870742 ps
CPU time 0.59 seconds
Started Aug 11 07:01:44 PM PDT 24
Finished Aug 11 07:01:45 PM PDT 24
Peak memory 195128 kb
Host smart-54bb61f4-b48b-49d5-bf5f-fc47208121ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304853940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.304853940
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2260034530
Short name T543
Test name
Test status
Simulation time 12223254 ps
CPU time 0.54 seconds
Started Aug 11 07:01:44 PM PDT 24
Finished Aug 11 07:01:45 PM PDT 24
Peak memory 195008 kb
Host smart-8296306b-b65d-499a-8fbb-9a102cf54459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260034530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2260034530
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1436277541
Short name T583
Test name
Test status
Simulation time 15564656 ps
CPU time 0.55 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:46 PM PDT 24
Peak memory 195096 kb
Host smart-2fde3852-389d-406a-acad-fddf2ce8e8d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436277541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1436277541
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1441068515
Short name T579
Test name
Test status
Simulation time 11058446 ps
CPU time 0.59 seconds
Started Aug 11 07:01:47 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 195076 kb
Host smart-1601dd64-cf10-45b8-b0fd-71b414dad606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441068515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1441068515
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1662549020
Short name T588
Test name
Test status
Simulation time 25552210 ps
CPU time 0.61 seconds
Started Aug 11 07:01:45 PM PDT 24
Finished Aug 11 07:01:46 PM PDT 24
Peak memory 195008 kb
Host smart-a7d20d9d-2e25-4a39-b46e-177420e51094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662549020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1662549020
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3125246785
Short name T594
Test name
Test status
Simulation time 124914005 ps
CPU time 0.59 seconds
Started Aug 11 07:01:47 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 195132 kb
Host smart-a323fc8b-bd5a-42db-ac8c-204c3a8fbdac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125246785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3125246785
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3050212434
Short name T564
Test name
Test status
Simulation time 227635159 ps
CPU time 0.63 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:47 PM PDT 24
Peak memory 195004 kb
Host smart-aff3d1d8-75e0-4055-a36e-0174294a55cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050212434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3050212434
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2270130269
Short name T586
Test name
Test status
Simulation time 41943461 ps
CPU time 2.57 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 208420 kb
Host smart-049b42db-6bc4-458f-a9cb-911ddb80d7d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270130269 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2270130269
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3265660280
Short name T654
Test name
Test status
Simulation time 67740072 ps
CPU time 0.84 seconds
Started Aug 11 07:01:23 PM PDT 24
Finished Aug 11 07:01:24 PM PDT 24
Peak memory 199428 kb
Host smart-91b66892-1fbe-4914-bc0b-db503392f658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265660280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3265660280
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3543784868
Short name T546
Test name
Test status
Simulation time 32959218 ps
CPU time 0.57 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:29 PM PDT 24
Peak memory 195144 kb
Host smart-ad8c03eb-5a9a-4810-a95a-699a42399a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543784868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3543784868
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.14706063
Short name T658
Test name
Test status
Simulation time 185135554 ps
CPU time 1.76 seconds
Started Aug 11 07:01:23 PM PDT 24
Finished Aug 11 07:01:25 PM PDT 24
Peak memory 200112 kb
Host smart-c9e17cc0-2b09-4821-a5b3-55eef09bcad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14706063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_o
utstanding.14706063
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.849198160
Short name T575
Test name
Test status
Simulation time 3568442484 ps
CPU time 3.75 seconds
Started Aug 11 07:01:27 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 200140 kb
Host smart-cf505e93-facb-41b2-9f7d-09fb867615dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849198160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.849198160
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3814132017
Short name T125
Test name
Test status
Simulation time 1172242224 ps
CPU time 4.55 seconds
Started Aug 11 07:01:21 PM PDT 24
Finished Aug 11 07:01:26 PM PDT 24
Peak memory 200128 kb
Host smart-cc3660ad-8b46-4999-b929-4a7d024bbd32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814132017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3814132017
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.663008691
Short name T606
Test name
Test status
Simulation time 518514007 ps
CPU time 2.34 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200232 kb
Host smart-7685d9d1-b96d-4190-888c-a565e51e5fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663008691 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.663008691
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1641270166
Short name T92
Test name
Test status
Simulation time 103998559 ps
CPU time 0.71 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:25 PM PDT 24
Peak memory 198000 kb
Host smart-8e5b7fc0-348a-48b4-82fe-4ba8b50b326d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641270166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1641270166
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2699747181
Short name T556
Test name
Test status
Simulation time 69249620 ps
CPU time 0.66 seconds
Started Aug 11 07:01:32 PM PDT 24
Finished Aug 11 07:01:33 PM PDT 24
Peak memory 195100 kb
Host smart-ad1e073e-3da6-430c-acc2-4bfe3a328fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699747181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2699747181
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1995867
Short name T104
Test name
Test status
Simulation time 141451186 ps
CPU time 1.1 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:26 PM PDT 24
Peak memory 200088 kb
Host smart-2fc8d1bd-1825-4804-a09e-bb0c447c17bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_ou
tstanding.1995867
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3427302864
Short name T551
Test name
Test status
Simulation time 125135091 ps
CPU time 2.47 seconds
Started Aug 11 07:01:27 PM PDT 24
Finished Aug 11 07:01:30 PM PDT 24
Peak memory 200132 kb
Host smart-1bab2efa-ba1a-41cc-b775-f222fee76b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427302864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3427302864
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2038946029
Short name T61
Test name
Test status
Simulation time 81763288 ps
CPU time 1.83 seconds
Started Aug 11 07:01:46 PM PDT 24
Finished Aug 11 07:01:48 PM PDT 24
Peak memory 200140 kb
Host smart-815d4414-0cb6-4ed3-a8d0-85b3814bca8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038946029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2038946029
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3961770257
Short name T644
Test name
Test status
Simulation time 170782292 ps
CPU time 2.93 seconds
Started Aug 11 07:01:29 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 208424 kb
Host smart-03747fa0-294b-4d07-b0b9-664eb4aedd86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961770257 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3961770257
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2186970720
Short name T632
Test name
Test status
Simulation time 114765019 ps
CPU time 0.92 seconds
Started Aug 11 07:01:26 PM PDT 24
Finished Aug 11 07:01:27 PM PDT 24
Peak memory 199968 kb
Host smart-a4f31bb0-e2ab-4fd6-82b2-74fb9676b140
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186970720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2186970720
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.26635855
Short name T562
Test name
Test status
Simulation time 38999824 ps
CPU time 0.57 seconds
Started Aug 11 07:01:26 PM PDT 24
Finished Aug 11 07:01:27 PM PDT 24
Peak memory 195008 kb
Host smart-f7d2a3b9-76ee-4100-a813-14d0e92099a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26635855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.26635855
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2074280906
Short name T601
Test name
Test status
Simulation time 45175802 ps
CPU time 2.14 seconds
Started Aug 11 07:01:23 PM PDT 24
Finished Aug 11 07:01:25 PM PDT 24
Peak memory 200220 kb
Host smart-3267ccd1-759c-4cb3-90ca-f7db3780fb2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074280906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2074280906
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3021534662
Short name T555
Test name
Test status
Simulation time 288230558 ps
CPU time 3.5 seconds
Started Aug 11 07:01:25 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 200156 kb
Host smart-02699b3c-ac07-42e1-b567-8da8556fffdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021534662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3021534662
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2707589408
Short name T577
Test name
Test status
Simulation time 79583435 ps
CPU time 1.88 seconds
Started Aug 11 07:01:32 PM PDT 24
Finished Aug 11 07:01:34 PM PDT 24
Peak memory 200228 kb
Host smart-8ff231de-ede0-450f-bb2b-3e9bb396907b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707589408 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2707589408
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3770942395
Short name T533
Test name
Test status
Simulation time 108347077 ps
CPU time 0.81 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 199248 kb
Host smart-ea1e12cb-9fac-42ce-9e73-3a9a16975134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770942395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3770942395
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2102839753
Short name T559
Test name
Test status
Simulation time 30731826 ps
CPU time 0.59 seconds
Started Aug 11 07:01:26 PM PDT 24
Finished Aug 11 07:01:26 PM PDT 24
Peak memory 195140 kb
Host smart-cb7bd1e7-900a-49a8-ab17-9baeb566814c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102839753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2102839753
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1653062344
Short name T638
Test name
Test status
Simulation time 46405017 ps
CPU time 2.17 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:27 PM PDT 24
Peak memory 200100 kb
Host smart-1585353d-0a89-4ff1-89f2-2241d39f1576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653062344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1653062344
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3718454293
Short name T629
Test name
Test status
Simulation time 515245666 ps
CPU time 2.7 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:27 PM PDT 24
Peak memory 200156 kb
Host smart-9cbaa3e1-91c5-495a-bd53-586476f3ce64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718454293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3718454293
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4231880054
Short name T124
Test name
Test status
Simulation time 451211924 ps
CPU time 4.13 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200168 kb
Host smart-8f23d94d-b301-4419-9faf-abbf77a21608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231880054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4231880054
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.242546719
Short name T535
Test name
Test status
Simulation time 164467070 ps
CPU time 1.29 seconds
Started Aug 11 07:01:42 PM PDT 24
Finished Aug 11 07:01:43 PM PDT 24
Peak memory 200144 kb
Host smart-173ef884-95ee-4c63-935e-3fdf26b53276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242546719 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.242546719
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.606924293
Short name T89
Test name
Test status
Simulation time 65481655 ps
CPU time 0.93 seconds
Started Aug 11 07:01:31 PM PDT 24
Finished Aug 11 07:01:33 PM PDT 24
Peak memory 199868 kb
Host smart-c1cecb51-fa1e-40da-a2ff-f9bcb0b7488b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606924293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.606924293
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2579242700
Short name T574
Test name
Test status
Simulation time 13952248 ps
CPU time 0.58 seconds
Started Aug 11 07:01:30 PM PDT 24
Finished Aug 11 07:01:31 PM PDT 24
Peak memory 195012 kb
Host smart-f5ebae4f-4669-4c06-bcae-71873937172e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579242700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2579242700
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1586669900
Short name T106
Test name
Test status
Simulation time 173801837 ps
CPU time 1.16 seconds
Started Aug 11 07:01:31 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 198680 kb
Host smart-e52b84d6-a3c9-4958-89d7-f293b9c3660e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586669900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1586669900
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.486899859
Short name T544
Test name
Test status
Simulation time 74688934 ps
CPU time 3.7 seconds
Started Aug 11 07:01:24 PM PDT 24
Finished Aug 11 07:01:28 PM PDT 24
Peak memory 200144 kb
Host smart-91f07e2d-3941-451c-b66f-5f5f74e84b04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486899859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.486899859
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2538533984
Short name T618
Test name
Test status
Simulation time 810712272 ps
CPU time 4.03 seconds
Started Aug 11 07:01:28 PM PDT 24
Finished Aug 11 07:01:32 PM PDT 24
Peak memory 200108 kb
Host smart-2ec0ef34-56a6-466e-8116-d99146e636b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538533984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2538533984
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3042210329
Short name T420
Test name
Test status
Simulation time 31922981 ps
CPU time 0.58 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:02:22 PM PDT 24
Peak memory 195916 kb
Host smart-7bbdc2bd-60ce-4bc5-afc5-f12b8e4e9c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042210329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3042210329
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.916456893
Short name T397
Test name
Test status
Simulation time 401421289 ps
CPU time 24.17 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:02:47 PM PDT 24
Peak memory 199928 kb
Host smart-84ec2288-0208-4363-983b-466427272172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916456893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.916456893
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.907662640
Short name T402
Test name
Test status
Simulation time 194304778 ps
CPU time 9.74 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:02:33 PM PDT 24
Peak memory 199796 kb
Host smart-9a26f8dc-c61a-4f8e-a387-28eb76cb3d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907662640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.907662640
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1838271273
Short name T370
Test name
Test status
Simulation time 1080500406 ps
CPU time 215.36 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:06:00 PM PDT 24
Peak memory 595272 kb
Host smart-0e08dd38-5c12-4bea-bff4-a2156ae54bfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838271273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1838271273
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.938833274
Short name T507
Test name
Test status
Simulation time 31366538283 ps
CPU time 149.39 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 199904 kb
Host smart-cd9ecd3c-f378-43f1-a662-1189159206cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938833274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.938833274
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4164349825
Short name T477
Test name
Test status
Simulation time 9923852659 ps
CPU time 133.06 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 199976 kb
Host smart-626bf714-875d-4af4-81d8-1e274da3507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164349825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4164349825
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1529140634
Short name T59
Test name
Test status
Simulation time 139228771 ps
CPU time 0.83 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:02:25 PM PDT 24
Peak memory 218520 kb
Host smart-4ef7bdc2-3299-4f65-ba12-ea7d7877d875
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529140634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1529140634
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1077857432
Short name T186
Test name
Test status
Simulation time 255453886 ps
CPU time 11.8 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:02:37 PM PDT 24
Peak memory 199788 kb
Host smart-fe5e523a-d26f-46c7-bcd3-8692fe39f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077857432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1077857432
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2024014162
Short name T308
Test name
Test status
Simulation time 51406080190 ps
CPU time 330.53 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:07:55 PM PDT 24
Peak memory 216320 kb
Host smart-bf1422f9-214f-4f9f-8b67-2a05bd2bf390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024014162 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2024014162
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3433963091
Short name T69
Test name
Test status
Simulation time 7835381936 ps
CPU time 201.39 seconds
Started Aug 11 07:02:20 PM PDT 24
Finished Aug 11 07:05:42 PM PDT 24
Peak memory 358200 kb
Host smart-8d6ed32f-86ed-4224-8018-d6e76f41a9a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433963091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3433963091
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3800497563
Short name T243
Test name
Test status
Simulation time 16284717341 ps
CPU time 78.92 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:03:43 PM PDT 24
Peak memory 199912 kb
Host smart-932956f1-564e-4c4c-afd3-4a65c6900f77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3800497563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3800497563
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2177133507
Short name T501
Test name
Test status
Simulation time 6657352113 ps
CPU time 103.92 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:04:07 PM PDT 24
Peak memory 200076 kb
Host smart-61f4ffbc-b6b5-4f21-8217-c94e7eab2a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2177133507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2177133507
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.53705475
Short name T157
Test name
Test status
Simulation time 16639469316 ps
CPU time 131.01 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 199884 kb
Host smart-bd9279d3-ebc6-412e-b760-0bab3c2143fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=53705475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.53705475
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3759451897
Short name T461
Test name
Test status
Simulation time 9870030229 ps
CPU time 561.58 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:11:44 PM PDT 24
Peak memory 199808 kb
Host smart-ff1017e3-4285-46b0-a3e2-6f10cdc847e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3759451897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3759451897
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2932475566
Short name T193
Test name
Test status
Simulation time 100979882496 ps
CPU time 2299.17 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:40:42 PM PDT 24
Peak memory 215860 kb
Host smart-688eed8f-0802-410b-a1e4-88279e66e9ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2932475566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2932475566
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.693951513
Short name T130
Test name
Test status
Simulation time 213370476654 ps
CPU time 2763.81 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:48:29 PM PDT 24
Peak memory 215316 kb
Host smart-34ae8c0e-267c-44b2-a57f-654004a7c256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=693951513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.693951513
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.921250493
Short name T249
Test name
Test status
Simulation time 11803355016 ps
CPU time 35.56 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:02:57 PM PDT 24
Peak memory 199896 kb
Host smart-a3d53467-bf69-48dc-b2bc-916c28eb1aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921250493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.921250493
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3283999167
Short name T45
Test name
Test status
Simulation time 41601524 ps
CPU time 0.61 seconds
Started Aug 11 07:02:29 PM PDT 24
Finished Aug 11 07:02:29 PM PDT 24
Peak memory 196612 kb
Host smart-6f843cbc-f23a-48d4-b07d-75186416a8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283999167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3283999167
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2473767715
Short name T166
Test name
Test status
Simulation time 1115047875 ps
CPU time 63.18 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:03:26 PM PDT 24
Peak memory 199896 kb
Host smart-5696aecb-8b77-4da4-b704-d33edea57844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473767715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2473767715
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.736667768
Short name T327
Test name
Test status
Simulation time 1831965468 ps
CPU time 17.08 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:02:39 PM PDT 24
Peak memory 199844 kb
Host smart-7441e0f1-2b48-4d20-b00c-c201f6eaf97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736667768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.736667768
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1643416940
Short name T356
Test name
Test status
Simulation time 1818349765 ps
CPU time 355.13 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:08:16 PM PDT 24
Peak memory 625272 kb
Host smart-af1463c8-261a-4e1b-bef2-672d14485d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643416940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1643416940
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.522491393
Short name T301
Test name
Test status
Simulation time 4698766569 ps
CPU time 61.87 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:03:26 PM PDT 24
Peak memory 199984 kb
Host smart-e4893030-4e2b-4d8e-bf1b-8ca9a808b6c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522491393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.522491393
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1446826673
Short name T296
Test name
Test status
Simulation time 984175060 ps
CPU time 59.98 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:03:25 PM PDT 24
Peak memory 199836 kb
Host smart-6d0bdbe7-9bb2-4872-acb8-51b2a1ca5b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446826673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1446826673
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4105250313
Short name T58
Test name
Test status
Simulation time 81366701 ps
CPU time 1.01 seconds
Started Aug 11 07:02:26 PM PDT 24
Finished Aug 11 07:02:27 PM PDT 24
Peak memory 219612 kb
Host smart-b9cc5180-bf67-4a8a-b8cf-895ecf37282a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105250313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4105250313
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3209409874
Short name T383
Test name
Test status
Simulation time 714298492 ps
CPU time 8.22 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:02:30 PM PDT 24
Peak memory 199828 kb
Host smart-3f1c1aed-9e25-411b-b739-0f68f9f7a14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209409874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3209409874
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1609229578
Short name T532
Test name
Test status
Simulation time 34482537005 ps
CPU time 842.87 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:16:27 PM PDT 24
Peak memory 723540 kb
Host smart-9b7eac0b-7dd7-423f-b869-89791b19b4fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609229578 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1609229578
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2555660175
Short name T68
Test name
Test status
Simulation time 140235077037 ps
CPU time 1984.88 seconds
Started Aug 11 07:02:27 PM PDT 24
Finished Aug 11 07:35:32 PM PDT 24
Peak memory 799228 kb
Host smart-1efc3b2e-66b7-44cb-a3f9-d6d27d951252
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555660175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2555660175
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3925245332
Short name T180
Test name
Test status
Simulation time 11816095572 ps
CPU time 37.39 seconds
Started Aug 11 07:02:21 PM PDT 24
Finished Aug 11 07:02:59 PM PDT 24
Peak memory 199912 kb
Host smart-8e19ef2c-94d4-4a07-a890-73ccb80db70c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3925245332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3925245332
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1876567560
Short name T440
Test name
Test status
Simulation time 9773735410 ps
CPU time 61.26 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:03:25 PM PDT 24
Peak memory 199940 kb
Host smart-9cd5e0cc-1ea2-4b9a-90dc-9bfef55e9c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1876567560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1876567560
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1015610383
Short name T260
Test name
Test status
Simulation time 14394343077 ps
CPU time 91.83 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:03:55 PM PDT 24
Peak memory 199912 kb
Host smart-80f51442-718a-45de-84b0-fbb3be24554b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1015610383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1015610383
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.393510143
Short name T261
Test name
Test status
Simulation time 92215164308 ps
CPU time 560.43 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:11:46 PM PDT 24
Peak memory 199868 kb
Host smart-aea87e8b-62d1-4139-9a82-e4da2c8db8a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=393510143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.393510143
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.659132747
Short name T366
Test name
Test status
Simulation time 152416596724 ps
CPU time 2616.92 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:46:02 PM PDT 24
Peak memory 208292 kb
Host smart-ce882a16-e752-4d1a-99a4-5f528beac7e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=659132747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.659132747
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.1556337200
Short name T396
Test name
Test status
Simulation time 136402651368 ps
CPU time 2425.98 seconds
Started Aug 11 07:02:23 PM PDT 24
Finished Aug 11 07:42:50 PM PDT 24
Peak memory 215676 kb
Host smart-acd1fcc3-5661-4488-a615-e79bc1dea85a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1556337200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1556337200
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1477486321
Short name T145
Test name
Test status
Simulation time 19585262500 ps
CPU time 64.79 seconds
Started Aug 11 07:02:22 PM PDT 24
Finished Aug 11 07:03:27 PM PDT 24
Peak memory 199932 kb
Host smart-c5369724-71e7-4d1d-a17b-c20791653e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477486321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1477486321
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2827182731
Short name T398
Test name
Test status
Simulation time 13669097 ps
CPU time 0.59 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:02:47 PM PDT 24
Peak memory 194920 kb
Host smart-8f314f7d-7efe-4ddb-b082-7211541be646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827182731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2827182731
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2375756701
Short name T163
Test name
Test status
Simulation time 2843413674 ps
CPU time 11.76 seconds
Started Aug 11 07:02:48 PM PDT 24
Finished Aug 11 07:03:00 PM PDT 24
Peak memory 199904 kb
Host smart-41cb8666-83b7-45d3-9919-df3b42f118c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375756701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2375756701
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.301369811
Short name T143
Test name
Test status
Simulation time 7426331545 ps
CPU time 57.82 seconds
Started Aug 11 07:02:48 PM PDT 24
Finished Aug 11 07:03:46 PM PDT 24
Peak memory 200000 kb
Host smart-27f3bec9-abe3-4554-903d-b8f10d348b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301369811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.301369811
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1031800518
Short name T369
Test name
Test status
Simulation time 6789322203 ps
CPU time 655.28 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:13:40 PM PDT 24
Peak memory 731552 kb
Host smart-12df7b9f-3c9c-491e-b9f8-409a361f15b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031800518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1031800518
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2443761152
Short name T321
Test name
Test status
Simulation time 23150507011 ps
CPU time 93.86 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:04:19 PM PDT 24
Peak memory 199856 kb
Host smart-2e6f9ff0-e324-45bf-b306-29e5006d10b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443761152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2443761152
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2758405778
Short name T514
Test name
Test status
Simulation time 36288000849 ps
CPU time 134.54 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 199944 kb
Host smart-460f2c1c-2926-4e4d-9b4a-1bfdfdd474e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758405778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2758405778
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1076676927
Short name T39
Test name
Test status
Simulation time 2626609156 ps
CPU time 143.87 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:05:11 PM PDT 24
Peak memory 200112 kb
Host smart-263e2398-7165-4f7d-921b-792e2b79ca8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076676927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1076676927
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.59279275
Short name T453
Test name
Test status
Simulation time 3593303478 ps
CPU time 46.41 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:03:32 PM PDT 24
Peak memory 199960 kb
Host smart-24680320-6c66-48a2-9783-3850d5639af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59279275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.59279275
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2222576869
Short name T294
Test name
Test status
Simulation time 14155805 ps
CPU time 0.59 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:02:46 PM PDT 24
Peak memory 194888 kb
Host smart-ba85a7ce-eb99-47f0-9a46-88c7e470270b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222576869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2222576869
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.426485410
Short name T395
Test name
Test status
Simulation time 2325674323 ps
CPU time 33.02 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:03:19 PM PDT 24
Peak memory 199940 kb
Host smart-a63931c4-c24e-4e3f-8479-d41ac7349964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426485410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.426485410
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3697177972
Short name T21
Test name
Test status
Simulation time 567731084 ps
CPU time 7.85 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 199896 kb
Host smart-fd99417f-134a-410e-876e-e0c4282acd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697177972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3697177972
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1110832000
Short name T224
Test name
Test status
Simulation time 1325875627 ps
CPU time 233.99 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:06:41 PM PDT 24
Peak memory 606608 kb
Host smart-3cde256d-5bb3-483c-86ed-64402df36986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110832000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1110832000
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1605291789
Short name T73
Test name
Test status
Simulation time 4540590380 ps
CPU time 95 seconds
Started Aug 11 07:02:50 PM PDT 24
Finished Aug 11 07:04:25 PM PDT 24
Peak memory 199900 kb
Host smart-49c2ea54-75e8-4850-a857-38b48584ad93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605291789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1605291789
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2786599458
Short name T263
Test name
Test status
Simulation time 13586388167 ps
CPU time 47.64 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:03:34 PM PDT 24
Peak memory 199924 kb
Host smart-41cabda4-6c4c-4c36-9884-56fca4b9c747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786599458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2786599458
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.415752875
Short name T41
Test name
Test status
Simulation time 1463426153 ps
CPU time 5.84 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:02:51 PM PDT 24
Peak memory 199844 kb
Host smart-cba945aa-af16-4d54-ae74-e71a6e2b8c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415752875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.415752875
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2876621060
Short name T496
Test name
Test status
Simulation time 3828648908 ps
CPU time 236.88 seconds
Started Aug 11 07:02:50 PM PDT 24
Finished Aug 11 07:06:47 PM PDT 24
Peak memory 199888 kb
Host smart-108325ac-12cb-4934-b073-61a6eb062262
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876621060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2876621060
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.479464330
Short name T83
Test name
Test status
Simulation time 4327451609 ps
CPU time 97.57 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:04:30 PM PDT 24
Peak memory 199996 kb
Host smart-64b94578-b315-4a0b-84dd-efc83cbac453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479464330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.479464330
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3139698174
Short name T340
Test name
Test status
Simulation time 135939623 ps
CPU time 0.58 seconds
Started Aug 11 07:02:56 PM PDT 24
Finished Aug 11 07:02:57 PM PDT 24
Peak memory 194928 kb
Host smart-8f2369d9-ae56-4477-8edb-d9f5a161ab53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139698174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3139698174
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1658432997
Short name T362
Test name
Test status
Simulation time 439279327 ps
CPU time 13.21 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:02:59 PM PDT 24
Peak memory 199804 kb
Host smart-71e43eca-f636-4bab-965f-a7e32af6fd57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658432997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1658432997
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2495375791
Short name T380
Test name
Test status
Simulation time 4773952100 ps
CPU time 22.41 seconds
Started Aug 11 07:02:51 PM PDT 24
Finished Aug 11 07:03:13 PM PDT 24
Peak memory 199968 kb
Host smart-f5293b2d-f63f-4eb4-a6c0-075137241bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495375791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2495375791
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1635961344
Short name T230
Test name
Test status
Simulation time 7018295162 ps
CPU time 324.91 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:08:19 PM PDT 24
Peak memory 647040 kb
Host smart-84a7b31a-6a02-467b-a348-e88be4914e45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635961344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1635961344
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1420950348
Short name T459
Test name
Test status
Simulation time 7035248444 ps
CPU time 121.59 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 199972 kb
Host smart-4c5f034b-15da-4df0-9bbe-4ed64f9d65b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420950348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1420950348
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1447906249
Short name T493
Test name
Test status
Simulation time 10828221395 ps
CPU time 159.4 seconds
Started Aug 11 07:02:49 PM PDT 24
Finished Aug 11 07:05:28 PM PDT 24
Peak memory 199936 kb
Host smart-9d5dbdd2-85d5-49c0-a2a9-67ec6be1ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447906249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1447906249
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3448456887
Short name T185
Test name
Test status
Simulation time 1168776898 ps
CPU time 13.5 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:03:00 PM PDT 24
Peak memory 199788 kb
Host smart-8b2e843c-6404-4089-9d14-e61080753885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448456887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3448456887
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1898493532
Short name T498
Test name
Test status
Simulation time 124103651596 ps
CPU time 2443.95 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:43:36 PM PDT 24
Peak memory 698844 kb
Host smart-251e1035-2ec4-4b8f-a5b9-c296219ad0dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898493532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1898493532
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.657166164
Short name T47
Test name
Test status
Simulation time 1798720826 ps
CPU time 82.54 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:04:15 PM PDT 24
Peak memory 199816 kb
Host smart-58379812-1686-4d76-b1d9-07fffb655716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657166164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.657166164
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.612239292
Short name T214
Test name
Test status
Simulation time 16853648 ps
CPU time 0.6 seconds
Started Aug 11 07:02:51 PM PDT 24
Finished Aug 11 07:02:52 PM PDT 24
Peak memory 195960 kb
Host smart-e03c46d2-4526-4377-8fc1-4ccbc77db405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612239292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.612239292
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3405268041
Short name T225
Test name
Test status
Simulation time 6332641795 ps
CPU time 59.47 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:03:55 PM PDT 24
Peak memory 199876 kb
Host smart-774c0ca5-d43b-489a-8d7c-35a07bb81e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405268041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3405268041
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3893301708
Short name T339
Test name
Test status
Simulation time 7313144901 ps
CPU time 785.9 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:16:01 PM PDT 24
Peak memory 650108 kb
Host smart-706a3a65-1a1d-4b90-a7c1-1392d41575f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893301708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3893301708
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.952880093
Short name T159
Test name
Test status
Simulation time 49222677 ps
CPU time 1.08 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:02:59 PM PDT 24
Peak memory 199724 kb
Host smart-3eaee5e0-324e-4eea-909a-3b9a63feddf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952880093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.952880093
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1335429484
Short name T235
Test name
Test status
Simulation time 9720274915 ps
CPU time 175.46 seconds
Started Aug 11 07:02:51 PM PDT 24
Finished Aug 11 07:05:46 PM PDT 24
Peak memory 209272 kb
Host smart-8180451a-dc34-454e-8a48-c9ac3074b944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335429484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1335429484
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1749529315
Short name T33
Test name
Test status
Simulation time 3221099949 ps
CPU time 14.3 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:03:06 PM PDT 24
Peak memory 199928 kb
Host smart-e90d82d1-5933-4f8d-b548-c28241b1a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749529315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1749529315
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2227144704
Short name T336
Test name
Test status
Simulation time 133938809986 ps
CPU time 833.76 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:16:47 PM PDT 24
Peak memory 445356 kb
Host smart-1ac17840-8536-4785-99c5-ea3f53b28a6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227144704 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2227144704
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.7126949
Short name T271
Test name
Test status
Simulation time 2036764796 ps
CPU time 99.83 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:04:34 PM PDT 24
Peak memory 199868 kb
Host smart-46710ed1-be6f-4e4d-b272-7bfaa6fbd76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7126949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.7126949
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2224695035
Short name T228
Test name
Test status
Simulation time 2355308800 ps
CPU time 29.85 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:23 PM PDT 24
Peak memory 199968 kb
Host smart-6c2420fd-3151-4797-a065-84197be8c660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224695035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2224695035
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2178145929
Short name T455
Test name
Test status
Simulation time 985186621 ps
CPU time 18.23 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:03:10 PM PDT 24
Peak memory 199924 kb
Host smart-778aea08-9489-464f-be14-3a813081647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178145929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2178145929
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.941500063
Short name T162
Test name
Test status
Simulation time 5099842412 ps
CPU time 966.34 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:19:00 PM PDT 24
Peak memory 715684 kb
Host smart-abdf6618-794f-4062-b8d8-36158e073838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941500063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.941500063
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.444109614
Short name T38
Test name
Test status
Simulation time 71162870838 ps
CPU time 144.73 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:05:20 PM PDT 24
Peak memory 199892 kb
Host smart-69db7e1e-60f3-4cd4-871c-31b6dbef5f71
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444109614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.444109614
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1392665791
Short name T311
Test name
Test status
Simulation time 1925724300 ps
CPU time 50.13 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:03:44 PM PDT 24
Peak memory 199844 kb
Host smart-37d29b0e-bde0-4780-bd2b-78bdc5185d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392665791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1392665791
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.902208126
Short name T509
Test name
Test status
Simulation time 3095406045 ps
CPU time 11.3 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:03:07 PM PDT 24
Peak memory 199912 kb
Host smart-6e4de06b-3ec9-4498-bff7-7dabfb8dfe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902208126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.902208126
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1672517465
Short name T431
Test name
Test status
Simulation time 28154969418 ps
CPU time 2189.6 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:39:23 PM PDT 24
Peak memory 823760 kb
Host smart-74e36dbb-57f4-4e04-ad9b-375f5b13c98f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672517465 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1672517465
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4275195242
Short name T203
Test name
Test status
Simulation time 71509666248 ps
CPU time 89.77 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:04:23 PM PDT 24
Peak memory 199900 kb
Host smart-219aa31e-ce75-4cef-bb6c-a4c82837ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275195242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4275195242
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2657193821
Short name T196
Test name
Test status
Simulation time 13068845 ps
CPU time 0.56 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:02:56 PM PDT 24
Peak memory 194888 kb
Host smart-d8f4f390-c67b-4444-bd21-17ea0c33c438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657193821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2657193821
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1923136816
Short name T338
Test name
Test status
Simulation time 4380169421 ps
CPU time 42.75 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:36 PM PDT 24
Peak memory 200056 kb
Host smart-60742395-5152-43f9-b153-eb099a34f649
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1923136816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1923136816
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2742739970
Short name T519
Test name
Test status
Simulation time 1716944198 ps
CPU time 47.35 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:41 PM PDT 24
Peak memory 199896 kb
Host smart-2489ad04-9029-41b5-b4e5-9988e8f40184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742739970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2742739970
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3651734148
Short name T197
Test name
Test status
Simulation time 974546458 ps
CPU time 160.11 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:05:35 PM PDT 24
Peak memory 480440 kb
Host smart-9992762b-6efb-4f6f-8102-6a6481c8b0d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651734148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3651734148
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1203420184
Short name T272
Test name
Test status
Simulation time 8109614074 ps
CPU time 72.95 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:04:05 PM PDT 24
Peak memory 199792 kb
Host smart-ce32f4bd-91a1-4714-940b-afdb3692b5e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203420184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1203420184
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2240672395
Short name T437
Test name
Test status
Simulation time 6361833880 ps
CPU time 110.51 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:04:46 PM PDT 24
Peak memory 199896 kb
Host smart-755151ce-0d18-4608-b318-a391da6ba57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240672395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2240672395
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2794546830
Short name T164
Test name
Test status
Simulation time 113581103 ps
CPU time 5.35 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:03:00 PM PDT 24
Peak memory 199940 kb
Host smart-6b565a9c-192a-49a4-90f0-2dd8ab88bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794546830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2794546830
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2842159495
Short name T113
Test name
Test status
Simulation time 21537354938 ps
CPU time 94.26 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:04:28 PM PDT 24
Peak memory 199920 kb
Host smart-711b294a-82ec-4487-a7f7-c822773eb896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842159495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2842159495
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3652046222
Short name T322
Test name
Test status
Simulation time 14565209 ps
CPU time 0.58 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 194888 kb
Host smart-7c8e88b3-7ed4-4a8a-85c5-a222af8a66b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652046222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3652046222
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1361759169
Short name T415
Test name
Test status
Simulation time 639023248 ps
CPU time 36.1 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:03:32 PM PDT 24
Peak memory 199864 kb
Host smart-e5318bdc-b547-4569-9243-dad5a3aa7f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361759169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1361759169
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1903281952
Short name T26
Test name
Test status
Simulation time 919394094 ps
CPU time 9.04 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:02 PM PDT 24
Peak memory 199804 kb
Host smart-f25fcf39-e200-45d9-ad16-19d529f4b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903281952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1903281952
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2115297344
Short name T147
Test name
Test status
Simulation time 3927197591 ps
CPU time 720.84 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:14:54 PM PDT 24
Peak memory 683532 kb
Host smart-735cfcea-c4cf-4f83-86d5-ced2373e6dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115297344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2115297344
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2177059342
Short name T342
Test name
Test status
Simulation time 149020588190 ps
CPU time 152.2 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:05:28 PM PDT 24
Peak memory 199908 kb
Host smart-be4abed5-bc95-461e-9d5c-556898c8e9c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177059342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2177059342
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1093239523
Short name T427
Test name
Test status
Simulation time 9994570740 ps
CPU time 131.69 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:05:05 PM PDT 24
Peak memory 216328 kb
Host smart-49ffa900-b73f-4cc4-afd3-bd58f5ed93a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093239523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1093239523
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2832376243
Short name T170
Test name
Test status
Simulation time 1411065980 ps
CPU time 3.16 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:02:57 PM PDT 24
Peak memory 199888 kb
Host smart-67a94d24-a701-486c-83b6-dda265d7c4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832376243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2832376243
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2901950965
Short name T57
Test name
Test status
Simulation time 85609862244 ps
CPU time 181.14 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:05:55 PM PDT 24
Peak memory 199984 kb
Host smart-acffd3c5-f43b-4b5f-a9ef-2882a24dee52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901950965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2901950965
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3817299778
Short name T17
Test name
Test status
Simulation time 7759825408 ps
CPU time 94.25 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:04:26 PM PDT 24
Peak memory 199916 kb
Host smart-194bfca9-fd8d-4301-bcf8-5292b90fcb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817299778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3817299778
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1701689261
Short name T323
Test name
Test status
Simulation time 16474636 ps
CPU time 0.62 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:02:54 PM PDT 24
Peak memory 195940 kb
Host smart-975186b5-d151-4916-a13b-54b20412739c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701689261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1701689261
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3046304020
Short name T280
Test name
Test status
Simulation time 417768382 ps
CPU time 24.77 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:03:17 PM PDT 24
Peak memory 199880 kb
Host smart-7ef57113-6813-455b-8be4-9e7c7fdc9c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046304020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3046304020
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2348893419
Short name T173
Test name
Test status
Simulation time 1290530638 ps
CPU time 4.88 seconds
Started Aug 11 07:02:56 PM PDT 24
Finished Aug 11 07:03:01 PM PDT 24
Peak memory 199844 kb
Host smart-cdb97825-cbeb-4ff1-a443-7403d6895aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348893419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2348893419
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.686551323
Short name T513
Test name
Test status
Simulation time 528753871 ps
CPU time 57.33 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:03:53 PM PDT 24
Peak memory 323608 kb
Host smart-7a080fc9-1dbd-465d-8052-67d3779aa4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686551323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.686551323
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.537485308
Short name T288
Test name
Test status
Simulation time 20345201887 ps
CPU time 87.71 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:04:22 PM PDT 24
Peak memory 199884 kb
Host smart-3fed36ff-6549-4bf5-8074-6e518a46dca2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537485308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.537485308
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2911483935
Short name T198
Test name
Test status
Simulation time 22306535214 ps
CPU time 195.87 seconds
Started Aug 11 07:02:56 PM PDT 24
Finished Aug 11 07:06:12 PM PDT 24
Peak memory 199928 kb
Host smart-a66ddd1b-5738-4755-9c81-ba30718b3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911483935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2911483935
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.118082281
Short name T298
Test name
Test status
Simulation time 858339600 ps
CPU time 11.45 seconds
Started Aug 11 07:02:51 PM PDT 24
Finished Aug 11 07:03:03 PM PDT 24
Peak memory 199860 kb
Host smart-153aea74-7083-4a2d-b5bb-f5a76246e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118082281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.118082281
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.965382062
Short name T140
Test name
Test status
Simulation time 13176544973 ps
CPU time 307.37 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:08:01 PM PDT 24
Peak memory 576652 kb
Host smart-dc5380f2-fc15-4c23-8cd9-9ad5f094d264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965382062 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.965382062
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3227925555
Short name T466
Test name
Test status
Simulation time 10663546743 ps
CPU time 31.86 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:25 PM PDT 24
Peak memory 199916 kb
Host smart-95e7762a-f815-46b9-b5ff-91a9598a5193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227925555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3227925555
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2930934141
Short name T456
Test name
Test status
Simulation time 33122189 ps
CPU time 0.66 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 195916 kb
Host smart-c9b8396c-9b2b-4d75-aa14-2f48e04e0fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930934141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2930934141
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1090754248
Short name T254
Test name
Test status
Simulation time 447808362 ps
CPU time 3.18 seconds
Started Aug 11 07:02:51 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 199676 kb
Host smart-10be9e91-c48c-4bbd-8ab8-0c87705fc5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090754248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1090754248
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.208939951
Short name T331
Test name
Test status
Simulation time 21857121816 ps
CPU time 982.47 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:19:18 PM PDT 24
Peak memory 717520 kb
Host smart-ea1f3295-dc74-4f7a-833d-d6ffd04a7860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208939951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.208939951
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1553918592
Short name T422
Test name
Test status
Simulation time 2515000772 ps
CPU time 43.48 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:03:39 PM PDT 24
Peak memory 199852 kb
Host smart-890997f0-85ac-4285-9251-7a50aee95336
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553918592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1553918592
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.807129731
Short name T531
Test name
Test status
Simulation time 476124973 ps
CPU time 18.09 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:03:15 PM PDT 24
Peak memory 199792 kb
Host smart-5077b4e1-a211-4e19-a377-a9127d6d2071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807129731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.807129731
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.659227092
Short name T207
Test name
Test status
Simulation time 173714299 ps
CPU time 1.75 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 199784 kb
Host smart-54a585bc-a808-4230-a8ef-17a38aa12ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659227092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.659227092
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.131266042
Short name T405
Test name
Test status
Simulation time 47860215149 ps
CPU time 214.78 seconds
Started Aug 11 07:02:51 PM PDT 24
Finished Aug 11 07:06:26 PM PDT 24
Peak memory 216404 kb
Host smart-6ec11034-3884-4f93-80ec-4619ecb8d501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131266042 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.131266042
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3331747145
Short name T523
Test name
Test status
Simulation time 1206964433 ps
CPU time 34.13 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:28 PM PDT 24
Peak memory 199884 kb
Host smart-2899ae2f-b0cc-4bc5-817c-3fbd8774ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331747145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3331747145
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.905188109
Short name T281
Test name
Test status
Simulation time 45244552 ps
CPU time 0.61 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:02:55 PM PDT 24
Peak memory 196544 kb
Host smart-3d2d2de0-dbdf-4c09-b64a-e84348584644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905188109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.905188109
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2630800030
Short name T385
Test name
Test status
Simulation time 1319199285 ps
CPU time 72.64 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:04:05 PM PDT 24
Peak memory 199768 kb
Host smart-387629b3-53c5-44e5-8944-5141417e1619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630800030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2630800030
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2942318380
Short name T210
Test name
Test status
Simulation time 11918344473 ps
CPU time 26.06 seconds
Started Aug 11 07:02:59 PM PDT 24
Finished Aug 11 07:03:25 PM PDT 24
Peak memory 199888 kb
Host smart-7a1c5142-0804-450f-9151-f590ccae6dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942318380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2942318380
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2042325419
Short name T148
Test name
Test status
Simulation time 12125721 ps
CPU time 0.68 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:02:54 PM PDT 24
Peak memory 198072 kb
Host smart-d6905ace-63f6-4cef-bf37-7091e2ba7471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042325419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2042325419
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2737686934
Short name T255
Test name
Test status
Simulation time 291053310 ps
CPU time 16.17 seconds
Started Aug 11 07:02:59 PM PDT 24
Finished Aug 11 07:03:15 PM PDT 24
Peak memory 199792 kb
Host smart-c0bd64c0-5820-4aec-b8ae-675ca5fcbd50
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737686934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2737686934
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1572137367
Short name T51
Test name
Test status
Simulation time 34153840366 ps
CPU time 169.68 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:05:43 PM PDT 24
Peak memory 200120 kb
Host smart-4aae26cf-9c20-496a-83b5-64cecb0f82fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572137367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1572137367
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2909476350
Short name T129
Test name
Test status
Simulation time 579269705 ps
CPU time 12.82 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:03:10 PM PDT 24
Peak memory 199848 kb
Host smart-d027f004-93a2-4fb5-94b9-ceaca236e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909476350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2909476350
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2516592201
Short name T293
Test name
Test status
Simulation time 31363598396 ps
CPU time 1102.02 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:21:16 PM PDT 24
Peak memory 699692 kb
Host smart-62822743-9129-477b-8e4e-b9d45cd21405
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516592201 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2516592201
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4022842132
Short name T489
Test name
Test status
Simulation time 1620544606 ps
CPU time 73.4 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:04:07 PM PDT 24
Peak memory 199760 kb
Host smart-ecb00c68-bc00-49d9-ad1e-fe2cc6b80ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022842132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4022842132
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1260059138
Short name T3
Test name
Test status
Simulation time 41087505 ps
CPU time 0.6 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:02:28 PM PDT 24
Peak memory 194888 kb
Host smart-703b2ad2-a75a-4622-ae36-4705120a8416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260059138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1260059138
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1641887707
Short name T20
Test name
Test status
Simulation time 20403752682 ps
CPU time 93.53 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:04:02 PM PDT 24
Peak memory 215260 kb
Host smart-091d9cb0-0401-47ee-88f5-fcfcb89e5259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641887707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1641887707
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.345327626
Short name T287
Test name
Test status
Simulation time 2654946844 ps
CPU time 12.82 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:02:41 PM PDT 24
Peak memory 199872 kb
Host smart-42fb83bb-0e13-4e82-8eb5-b21ac2709ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345327626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.345327626
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_error.2114282019
Short name T433
Test name
Test status
Simulation time 22337860501 ps
CPU time 98.22 seconds
Started Aug 11 07:02:24 PM PDT 24
Finished Aug 11 07:04:02 PM PDT 24
Peak memory 199944 kb
Host smart-9fc85b9f-7edb-4ad7-96d0-09d37c26e070
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114282019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2114282019
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1544660624
Short name T154
Test name
Test status
Simulation time 2910395942 ps
CPU time 48.65 seconds
Started Aug 11 07:02:27 PM PDT 24
Finished Aug 11 07:03:16 PM PDT 24
Peak memory 199880 kb
Host smart-d1e837bd-0a0a-4a53-a7b0-89727d1ca472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544660624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1544660624
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.3186207378
Short name T367
Test name
Test status
Simulation time 4560050119 ps
CPU time 7.84 seconds
Started Aug 11 07:02:27 PM PDT 24
Finished Aug 11 07:02:35 PM PDT 24
Peak memory 199900 kb
Host smart-b00c9d9b-20ee-45ff-a966-81512c70a646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186207378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3186207378
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3393877580
Short name T115
Test name
Test status
Simulation time 104235753602 ps
CPU time 382.73 seconds
Started Aug 11 07:02:26 PM PDT 24
Finished Aug 11 07:08:49 PM PDT 24
Peak memory 208148 kb
Host smart-c52c784b-3d6a-45c6-9a4d-954b5bc9eee8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393877580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3393877580
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2279065040
Short name T67
Test name
Test status
Simulation time 66766687906 ps
CPU time 361.18 seconds
Started Aug 11 07:02:26 PM PDT 24
Finished Aug 11 07:08:27 PM PDT 24
Peak memory 208200 kb
Host smart-28cccce5-b2e1-4794-8d05-9bb89e4f8c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279065040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2279065040
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1858694476
Short name T299
Test name
Test status
Simulation time 2608746759 ps
CPU time 45.05 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:03:13 PM PDT 24
Peak memory 200068 kb
Host smart-84430b03-83ff-4983-9958-1e8f616ec1a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1858694476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1858694476
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1232577916
Short name T353
Test name
Test status
Simulation time 9902373641 ps
CPU time 109.3 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:04:17 PM PDT 24
Peak memory 199912 kb
Host smart-bc0941cf-36d8-4ba6-aaf3-8126495af3d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1232577916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1232577916
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2451898514
Short name T303
Test name
Test status
Simulation time 38629306357 ps
CPU time 122.71 seconds
Started Aug 11 07:02:26 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 199968 kb
Host smart-4c851bc5-6db1-4726-b1f8-a7848f628132
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2451898514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2451898514
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1508961605
Short name T258
Test name
Test status
Simulation time 10907236265 ps
CPU time 595.6 seconds
Started Aug 11 07:02:27 PM PDT 24
Finished Aug 11 07:12:22 PM PDT 24
Peak memory 199900 kb
Host smart-2b9d9a89-b398-4122-813e-59d5a3762390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1508961605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1508961605
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1416440229
Short name T135
Test name
Test status
Simulation time 145931691616 ps
CPU time 2676.94 seconds
Started Aug 11 07:02:25 PM PDT 24
Finished Aug 11 07:47:03 PM PDT 24
Peak memory 215420 kb
Host smart-ee3c0095-8562-4bfb-8c6c-30e7d002cb49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1416440229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1416440229
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2695626392
Short name T134
Test name
Test status
Simulation time 207496490838 ps
CPU time 2157.89 seconds
Started Aug 11 07:02:28 PM PDT 24
Finished Aug 11 07:38:26 PM PDT 24
Peak memory 215916 kb
Host smart-8db50971-c094-4be7-8be6-618d85f82360
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2695626392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2695626392
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3363649864
Short name T375
Test name
Test status
Simulation time 1092629548 ps
CPU time 58.7 seconds
Started Aug 11 07:02:31 PM PDT 24
Finished Aug 11 07:03:30 PM PDT 24
Peak memory 199828 kb
Host smart-9c025b56-04b9-4fa8-86ba-5c3468de1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363649864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3363649864
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1222162621
Short name T165
Test name
Test status
Simulation time 15093112 ps
CPU time 0.59 seconds
Started Aug 11 07:02:56 PM PDT 24
Finished Aug 11 07:02:57 PM PDT 24
Peak memory 195972 kb
Host smart-e011ded6-7643-41dd-b94b-d335db7717d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222162621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1222162621
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.289846077
Short name T29
Test name
Test status
Simulation time 1292414828 ps
CPU time 65.94 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:04:01 PM PDT 24
Peak memory 199816 kb
Host smart-ab9507b1-595d-45ae-b1c1-082668604a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289846077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.289846077
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3939793023
Short name T462
Test name
Test status
Simulation time 211543921 ps
CPU time 4.92 seconds
Started Aug 11 07:02:59 PM PDT 24
Finished Aug 11 07:03:04 PM PDT 24
Peak memory 199784 kb
Host smart-4886aa13-84d8-427e-87e7-0ba032748592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939793023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3939793023
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.230486570
Short name T234
Test name
Test status
Simulation time 4768929468 ps
CPU time 493.12 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:11:08 PM PDT 24
Peak memory 711356 kb
Host smart-c8f2c51b-c21e-4e99-9d19-2df8648cec87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230486570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.230486570
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1723352985
Short name T404
Test name
Test status
Simulation time 1665537449 ps
CPU time 78.47 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:04:12 PM PDT 24
Peak memory 199836 kb
Host smart-ae1ef15e-32d5-44ee-a0ff-8179a4628267
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723352985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1723352985
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.22268616
Short name T238
Test name
Test status
Simulation time 7553086834 ps
CPU time 132.65 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:05:05 PM PDT 24
Peak memory 199968 kb
Host smart-397a5c0a-1a28-471c-adb1-95b966c6626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22268616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.22268616
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2423902604
Short name T359
Test name
Test status
Simulation time 1021455895 ps
CPU time 13.62 seconds
Started Aug 11 07:02:53 PM PDT 24
Finished Aug 11 07:03:07 PM PDT 24
Peak memory 199876 kb
Host smart-2f80a03b-4eb0-4e60-aa65-03af97beb66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423902604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2423902604
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3540547943
Short name T81
Test name
Test status
Simulation time 49463002448 ps
CPU time 692.94 seconds
Started Aug 11 07:02:59 PM PDT 24
Finished Aug 11 07:14:32 PM PDT 24
Peak memory 433328 kb
Host smart-7eb51a5e-c98b-4f29-a620-08d4cdfd5ddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540547943 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3540547943
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2315450407
Short name T417
Test name
Test status
Simulation time 79517120289 ps
CPU time 138.44 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:05:13 PM PDT 24
Peak memory 199872 kb
Host smart-84428a79-22d7-4f95-8233-6cb4d267d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315450407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2315450407
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1579995775
Short name T241
Test name
Test status
Simulation time 19684795 ps
CPU time 0.59 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:02:59 PM PDT 24
Peak memory 196628 kb
Host smart-5cf90815-ce51-4a6f-a22d-786354f52787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579995775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1579995775
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1616298532
Short name T49
Test name
Test status
Simulation time 884131614 ps
CPU time 51.52 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:03:57 PM PDT 24
Peak memory 199924 kb
Host smart-7eee3c8a-a3be-4406-bd57-3674cc34fa1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616298532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1616298532
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.762787197
Short name T439
Test name
Test status
Simulation time 5547661260 ps
CPU time 36.65 seconds
Started Aug 11 07:03:00 PM PDT 24
Finished Aug 11 07:03:37 PM PDT 24
Peak memory 199936 kb
Host smart-d5b424c3-5079-4eb6-8ebc-fc823297a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762787197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.762787197
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4132520540
Short name T392
Test name
Test status
Simulation time 4506723991 ps
CPU time 285.43 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:07:44 PM PDT 24
Peak memory 622900 kb
Host smart-0509ab94-3f39-48bf-8d47-f43fa347a3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132520540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4132520540
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.135021188
Short name T250
Test name
Test status
Simulation time 1714810678 ps
CPU time 22.55 seconds
Started Aug 11 07:03:02 PM PDT 24
Finished Aug 11 07:03:24 PM PDT 24
Peak memory 199872 kb
Host smart-23817f46-c574-4784-8db3-f1aba6c5459f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135021188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.135021188
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3654651048
Short name T211
Test name
Test status
Simulation time 20314215813 ps
CPU time 135.11 seconds
Started Aug 11 07:02:54 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 199900 kb
Host smart-05a4c0e3-8181-4300-b184-bf351ea342e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654651048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3654651048
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2267757551
Short name T360
Test name
Test status
Simulation time 160283424 ps
CPU time 3.07 seconds
Started Aug 11 07:02:55 PM PDT 24
Finished Aug 11 07:02:59 PM PDT 24
Peak memory 199880 kb
Host smart-48595bf4-6c33-4181-9ff2-3cc9fbf127a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267757551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2267757551
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3530339750
Short name T34
Test name
Test status
Simulation time 5121032565 ps
CPU time 144.06 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:05:22 PM PDT 24
Peak memory 200112 kb
Host smart-28d51f70-980f-45f4-a21e-8166c23ca616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530339750 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3530339750
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1760058535
Short name T384
Test name
Test status
Simulation time 22027281339 ps
CPU time 102.23 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:04:40 PM PDT 24
Peak memory 199848 kb
Host smart-10c00e6b-5561-4324-adf2-f274dff04762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760058535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1760058535
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3129346196
Short name T410
Test name
Test status
Simulation time 38346211 ps
CPU time 0.56 seconds
Started Aug 11 07:03:00 PM PDT 24
Finished Aug 11 07:03:01 PM PDT 24
Peak memory 194836 kb
Host smart-772d24ce-a60f-4f8e-b5b6-d51526301ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129346196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3129346196
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1781134351
Short name T259
Test name
Test status
Simulation time 1258525188 ps
CPU time 71.63 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:04:10 PM PDT 24
Peak memory 199912 kb
Host smart-47edcc93-e2d7-4bf2-98e6-d0e6c97fe7bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781134351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1781134351
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1420331745
Short name T116
Test name
Test status
Simulation time 587760702 ps
CPU time 29.89 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:03:29 PM PDT 24
Peak memory 199860 kb
Host smart-912adf6c-5655-4af3-aafa-b46c9df67b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420331745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1420331745
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.972321513
Short name T458
Test name
Test status
Simulation time 1227418527 ps
CPU time 198.39 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:06:16 PM PDT 24
Peak memory 461344 kb
Host smart-6b2f4fcd-5e93-40d9-8a79-d2433e1ca91e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972321513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.972321513
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1025397443
Short name T46
Test name
Test status
Simulation time 1450117507 ps
CPU time 79.61 seconds
Started Aug 11 07:03:00 PM PDT 24
Finished Aug 11 07:04:20 PM PDT 24
Peak memory 199924 kb
Host smart-3754f3ef-380e-44db-865a-76284fa359cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025397443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1025397443
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3498458941
Short name T2
Test name
Test status
Simulation time 25286822781 ps
CPU time 114.84 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:04:52 PM PDT 24
Peak memory 199948 kb
Host smart-3af3f76a-8b36-48f4-b0bb-7248f62eed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498458941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3498458941
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3840501421
Short name T60
Test name
Test status
Simulation time 1374617505 ps
CPU time 4.39 seconds
Started Aug 11 07:03:01 PM PDT 24
Finished Aug 11 07:03:05 PM PDT 24
Peak memory 199872 kb
Host smart-e0ef9520-0196-4d91-b147-3a35296302a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840501421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3840501421
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1941765702
Short name T343
Test name
Test status
Simulation time 13205618594 ps
CPU time 52.88 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:03:58 PM PDT 24
Peak memory 199924 kb
Host smart-658e27ab-e333-4370-850a-d04f82d20d08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941765702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1941765702
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.598784615
Short name T176
Test name
Test status
Simulation time 806690363 ps
CPU time 14.67 seconds
Started Aug 11 07:02:57 PM PDT 24
Finished Aug 11 07:03:12 PM PDT 24
Peak memory 199828 kb
Host smart-b4027cf4-2e61-4180-b208-91f292ecb5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598784615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.598784615
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1283519684
Short name T158
Test name
Test status
Simulation time 24217120 ps
CPU time 0.56 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 07:03:09 PM PDT 24
Peak memory 194924 kb
Host smart-a0d62a8e-2f18-4885-ae17-0c84e5f5a28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283519684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1283519684
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4264103956
Short name T436
Test name
Test status
Simulation time 1555844062 ps
CPU time 89.36 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:04:27 PM PDT 24
Peak memory 199904 kb
Host smart-e7aa5e01-07bb-425f-8868-26ca0b3cc8df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264103956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4264103956
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2870481805
Short name T500
Test name
Test status
Simulation time 511029175 ps
CPU time 27.58 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:03:33 PM PDT 24
Peak memory 199864 kb
Host smart-e94b3cec-3248-42d7-b44c-af3328affa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870481805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2870481805
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.687228744
Short name T278
Test name
Test status
Simulation time 12366559939 ps
CPU time 487.94 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:11:13 PM PDT 24
Peak memory 634224 kb
Host smart-f92977ce-b073-4d82-98c4-8e2a0009bd3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687228744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.687228744
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3837147600
Short name T418
Test name
Test status
Simulation time 5068053964 ps
CPU time 23.16 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:03:22 PM PDT 24
Peak memory 199824 kb
Host smart-be3d846f-ee83-4c1b-82f1-85867b7d63d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837147600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3837147600
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.727383450
Short name T429
Test name
Test status
Simulation time 47366035735 ps
CPU time 191.87 seconds
Started Aug 11 07:03:00 PM PDT 24
Finished Aug 11 07:06:12 PM PDT 24
Peak memory 208160 kb
Host smart-b9366b0b-d1b4-4bb5-a831-23c7f8a96849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727383450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.727383450
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1246433516
Short name T371
Test name
Test status
Simulation time 171014259 ps
CPU time 3.45 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:03:02 PM PDT 24
Peak memory 199908 kb
Host smart-6818dc78-7f4b-4242-be54-b296504282ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246433516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1246433516
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2575464251
Short name T499
Test name
Test status
Simulation time 53381447087 ps
CPU time 1143.12 seconds
Started Aug 11 07:02:58 PM PDT 24
Finished Aug 11 07:22:01 PM PDT 24
Peak memory 682352 kb
Host smart-dae39d7a-abdb-47d8-b0e3-b8d71ec78e45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575464251 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2575464251
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1170924043
Short name T506
Test name
Test status
Simulation time 18007969154 ps
CPU time 103.25 seconds
Started Aug 11 07:02:59 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 199832 kb
Host smart-ea2b466e-a233-4681-8e44-73c9487012ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170924043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1170924043
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1718722124
Short name T408
Test name
Test status
Simulation time 46968789 ps
CPU time 0.58 seconds
Started Aug 11 07:03:06 PM PDT 24
Finished Aug 11 07:03:07 PM PDT 24
Peak memory 195956 kb
Host smart-c746f0ec-b83d-4d58-8945-09af7bc8acc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718722124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1718722124
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3679805258
Short name T19
Test name
Test status
Simulation time 5549374612 ps
CPU time 78.93 seconds
Started Aug 11 07:03:06 PM PDT 24
Finished Aug 11 07:04:25 PM PDT 24
Peak memory 199928 kb
Host smart-75f95744-5911-469e-a1e2-2357704f97dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679805258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3679805258
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.473163398
Short name T484
Test name
Test status
Simulation time 10508390984 ps
CPU time 61.6 seconds
Started Aug 11 07:03:03 PM PDT 24
Finished Aug 11 07:04:05 PM PDT 24
Peak memory 208132 kb
Host smart-9a62888d-a4fd-449b-8c5a-6587ece8705e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473163398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.473163398
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1722721256
Short name T381
Test name
Test status
Simulation time 5068558005 ps
CPU time 798.89 seconds
Started Aug 11 07:03:07 PM PDT 24
Finished Aug 11 07:16:26 PM PDT 24
Peak memory 666488 kb
Host smart-edbbfa0b-e80c-4800-984d-a1b643bedb47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722721256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1722721256
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.826103520
Short name T328
Test name
Test status
Simulation time 25962730605 ps
CPU time 112.35 seconds
Started Aug 11 07:03:07 PM PDT 24
Finished Aug 11 07:05:00 PM PDT 24
Peak memory 199940 kb
Host smart-c8aec7d5-40c1-455f-b8f1-415963a9ce68
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826103520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.826103520
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3867802984
Short name T131
Test name
Test status
Simulation time 59244998035 ps
CPU time 179.23 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 07:06:08 PM PDT 24
Peak memory 199952 kb
Host smart-93ee22fc-bcb4-4a44-94a1-0bbcb429a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867802984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3867802984
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.211667055
Short name T393
Test name
Test status
Simulation time 1019336643 ps
CPU time 12.26 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:03:17 PM PDT 24
Peak memory 199852 kb
Host smart-e38251a8-4d03-49a3-9d66-c287bbb20f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211667055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.211667055
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1316297429
Short name T365
Test name
Test status
Simulation time 80101771125 ps
CPU time 1248.64 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 07:23:58 PM PDT 24
Peak memory 656036 kb
Host smart-7a8e20db-0641-404a-9371-c22ba02754f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316297429 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1316297429
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3869952343
Short name T406
Test name
Test status
Simulation time 10438026820 ps
CPU time 126.6 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 07:05:16 PM PDT 24
Peak memory 199932 kb
Host smart-99b11689-b0c2-4f7d-b8d8-6fa964a0245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869952343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3869952343
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1708046359
Short name T283
Test name
Test status
Simulation time 21594178 ps
CPU time 0.58 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:03:06 PM PDT 24
Peak memory 194936 kb
Host smart-e08ab6e8-2f45-42f0-bf02-59e912280ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708046359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1708046359
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.496814072
Short name T290
Test name
Test status
Simulation time 577178253 ps
CPU time 33.34 seconds
Started Aug 11 07:03:04 PM PDT 24
Finished Aug 11 07:03:38 PM PDT 24
Peak memory 200076 kb
Host smart-26bc4dcb-2698-4b2e-81d5-71ca4fa31b73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496814072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.496814072
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2162591505
Short name T15
Test name
Test status
Simulation time 1164162922 ps
CPU time 16.8 seconds
Started Aug 11 07:03:03 PM PDT 24
Finished Aug 11 07:03:20 PM PDT 24
Peak memory 199924 kb
Host smart-6abb044a-0dc5-4189-9782-fe232c25df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162591505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2162591505
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.781929744
Short name T515
Test name
Test status
Simulation time 5241536328 ps
CPU time 924.78 seconds
Started Aug 11 07:03:02 PM PDT 24
Finished Aug 11 07:18:27 PM PDT 24
Peak memory 751768 kb
Host smart-3def07f5-7083-44fd-b90f-994d75d816c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781929744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.781929744
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2826679467
Short name T212
Test name
Test status
Simulation time 2111113501 ps
CPU time 28.67 seconds
Started Aug 11 07:03:04 PM PDT 24
Finished Aug 11 07:03:32 PM PDT 24
Peak memory 199824 kb
Host smart-edc0d564-ed18-480d-bf3a-2db89a41b5b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826679467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2826679467
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.684971310
Short name T70
Test name
Test status
Simulation time 15001307642 ps
CPU time 104.83 seconds
Started Aug 11 07:03:07 PM PDT 24
Finished Aug 11 07:04:52 PM PDT 24
Peak memory 199960 kb
Host smart-a8a22d98-9dbd-4e6f-82db-02ba40f62364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684971310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.684971310
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.246655068
Short name T52
Test name
Test status
Simulation time 863991728 ps
CPU time 7.41 seconds
Started Aug 11 07:03:04 PM PDT 24
Finished Aug 11 07:03:11 PM PDT 24
Peak memory 199852 kb
Host smart-06454d4f-4859-4f56-a018-e0eb124cc9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246655068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.246655068
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.194942301
Short name T483
Test name
Test status
Simulation time 311550173648 ps
CPU time 2823.52 seconds
Started Aug 11 07:03:05 PM PDT 24
Finished Aug 11 07:50:09 PM PDT 24
Peak memory 780300 kb
Host smart-006c85af-eeaa-450f-8e8f-60b9201ded98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194942301 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.194942301
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.196480277
Short name T423
Test name
Test status
Simulation time 900294703 ps
CPU time 42.07 seconds
Started Aug 11 07:03:03 PM PDT 24
Finished Aug 11 07:03:46 PM PDT 24
Peak memory 199832 kb
Host smart-29511414-367e-4ccd-a2f3-a23500789569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196480277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.196480277
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2739408760
Short name T274
Test name
Test status
Simulation time 15510882 ps
CPU time 0.6 seconds
Started Aug 11 07:03:11 PM PDT 24
Finished Aug 11 07:03:11 PM PDT 24
Peak memory 195664 kb
Host smart-a96d9ac6-2fcb-4a08-8d9e-baabe9301b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739408760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2739408760
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3664941736
Short name T472
Test name
Test status
Simulation time 5652937467 ps
CPU time 70.2 seconds
Started Aug 11 07:03:08 PM PDT 24
Finished Aug 11 07:04:18 PM PDT 24
Peak memory 199972 kb
Host smart-9be67460-1801-4567-8392-01c65606509f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664941736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3664941736
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4205254762
Short name T275
Test name
Test status
Simulation time 706933513 ps
CPU time 9.43 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:03:25 PM PDT 24
Peak memory 198952 kb
Host smart-886c55b0-1225-4cd7-9d22-433506b33603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205254762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4205254762
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1351937966
Short name T414
Test name
Test status
Simulation time 1029865550 ps
CPU time 138.93 seconds
Started Aug 11 07:03:11 PM PDT 24
Finished Aug 11 07:05:30 PM PDT 24
Peak memory 337192 kb
Host smart-8e68580e-d141-4722-b2df-f162ec5c6ce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351937966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1351937966
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3055371316
Short name T438
Test name
Test status
Simulation time 9111491641 ps
CPU time 41.25 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:03:57 PM PDT 24
Peak memory 199084 kb
Host smart-f6ce0fbf-b19c-445b-9cad-2a5b01fad34a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055371316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3055371316
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.456122182
Short name T168
Test name
Test status
Simulation time 258285503 ps
CPU time 7.26 seconds
Started Aug 11 07:03:10 PM PDT 24
Finished Aug 11 07:03:18 PM PDT 24
Peak memory 199784 kb
Host smart-c2809457-a291-4676-9981-eda199f4cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456122182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.456122182
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4287550852
Short name T478
Test name
Test status
Simulation time 138534247 ps
CPU time 2.65 seconds
Started Aug 11 07:03:03 PM PDT 24
Finished Aug 11 07:03:06 PM PDT 24
Peak memory 199864 kb
Host smart-e03f6ef3-4584-44c2-927f-958f764bc1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287550852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4287550852
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.422430922
Short name T79
Test name
Test status
Simulation time 33527496416 ps
CPU time 113.09 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 07:05:02 PM PDT 24
Peak memory 200064 kb
Host smart-729c9d7c-e0db-42f6-99e8-dce04bfdf666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422430922 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.422430922
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1384525670
Short name T471
Test name
Test status
Simulation time 12915124776 ps
CPU time 132.52 seconds
Started Aug 11 07:03:11 PM PDT 24
Finished Aug 11 07:05:23 PM PDT 24
Peak memory 199912 kb
Host smart-1c41a5a2-a6ad-425c-a9b3-405cf159a85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384525670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1384525670
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.682392097
Short name T226
Test name
Test status
Simulation time 14060253 ps
CPU time 0.63 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:03:16 PM PDT 24
Peak memory 195528 kb
Host smart-2826a39e-ed73-43ad-b672-3175666c72ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682392097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.682392097
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1623159820
Short name T175
Test name
Test status
Simulation time 371155290 ps
CPU time 22.19 seconds
Started Aug 11 07:03:11 PM PDT 24
Finished Aug 11 07:03:33 PM PDT 24
Peak memory 199812 kb
Host smart-47b78219-ee23-416f-944d-dbc41294e091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623159820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1623159820
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.464807809
Short name T142
Test name
Test status
Simulation time 819376523 ps
CPU time 41.53 seconds
Started Aug 11 07:03:11 PM PDT 24
Finished Aug 11 07:03:53 PM PDT 24
Peak memory 199852 kb
Host smart-fd934804-1a7d-4c54-a0dd-67ea01014f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464807809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.464807809
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1815137340
Short name T419
Test name
Test status
Simulation time 1979605788 ps
CPU time 195.69 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 07:06:24 PM PDT 24
Peak memory 580336 kb
Host smart-9c4e5e31-5488-4470-a77e-66cd74a4ad51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815137340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1815137340
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.615534196
Short name T267
Test name
Test status
Simulation time 2969966484 ps
CPU time 155.8 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:05:51 PM PDT 24
Peak memory 199944 kb
Host smart-5c30ec40-c67d-4a5f-ab14-debd386b61df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615534196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.615534196
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2680278556
Short name T475
Test name
Test status
Simulation time 18784531869 ps
CPU time 123.46 seconds
Started Aug 11 07:03:10 PM PDT 24
Finished Aug 11 07:05:14 PM PDT 24
Peak memory 216096 kb
Host smart-9ed3af33-25fd-431b-ac30-bf379af0f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680278556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2680278556
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1986024904
Short name T264
Test name
Test status
Simulation time 3477913765 ps
CPU time 12.17 seconds
Started Aug 11 07:03:10 PM PDT 24
Finished Aug 11 07:03:22 PM PDT 24
Peak memory 199952 kb
Host smart-a8f39ade-de40-4421-8bce-a447d8974070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986024904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1986024904
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2328685927
Short name T204
Test name
Test status
Simulation time 149501181741 ps
CPU time 3941.43 seconds
Started Aug 11 07:03:09 PM PDT 24
Finished Aug 11 08:08:51 PM PDT 24
Peak memory 798000 kb
Host smart-a88a10a1-698a-4c4a-a7eb-eb9ae145ca98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328685927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2328685927
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1934295195
Short name T252
Test name
Test status
Simulation time 1555513374 ps
CPU time 22.46 seconds
Started Aug 11 07:03:10 PM PDT 24
Finished Aug 11 07:03:33 PM PDT 24
Peak memory 199868 kb
Host smart-e0f18b91-e7bc-447d-81df-c2f83f380270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934295195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1934295195
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.875189522
Short name T174
Test name
Test status
Simulation time 50984908 ps
CPU time 0.6 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:03:17 PM PDT 24
Peak memory 195976 kb
Host smart-d9639fd6-aabe-469f-a40b-dee658f2dd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875189522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.875189522
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.292954175
Short name T222
Test name
Test status
Simulation time 1382984387 ps
CPU time 39.89 seconds
Started Aug 11 07:03:17 PM PDT 24
Finished Aug 11 07:03:57 PM PDT 24
Peak memory 199924 kb
Host smart-a10c98fe-0a1d-426e-bd2c-c1811f602130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292954175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.292954175
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1457350438
Short name T485
Test name
Test status
Simulation time 1413742799 ps
CPU time 23.33 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:03:39 PM PDT 24
Peak memory 199836 kb
Host smart-cbcab4c5-9403-471b-bb5d-98a0015cf2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457350438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1457350438
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2932485662
Short name T253
Test name
Test status
Simulation time 16982751899 ps
CPU time 1048.32 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:20:44 PM PDT 24
Peak memory 740308 kb
Host smart-c45f73fe-212f-4ef6-a55c-d5e7b1884978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932485662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2932485662
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2484694758
Short name T426
Test name
Test status
Simulation time 5945906916 ps
CPU time 52 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:04:08 PM PDT 24
Peak memory 199968 kb
Host smart-7865d5ce-ec4e-41b4-ae86-09c31eae4010
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484694758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2484694758
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3152923517
Short name T182
Test name
Test status
Simulation time 596693203 ps
CPU time 34.07 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:03:50 PM PDT 24
Peak memory 199900 kb
Host smart-3fc1eb3d-6396-4b14-8332-0d0a2e988331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152923517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3152923517
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.490741037
Short name T319
Test name
Test status
Simulation time 192459027 ps
CPU time 9.43 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:03:26 PM PDT 24
Peak memory 199752 kb
Host smart-f813c49a-92c6-4d67-a2c6-fe4fb0c1e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490741037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.490741037
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3325473718
Short name T285
Test name
Test status
Simulation time 15714554349 ps
CPU time 192.55 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:06:29 PM PDT 24
Peak memory 216284 kb
Host smart-d62352ea-9592-4114-b911-776663800898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325473718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3325473718
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1369148198
Short name T386
Test name
Test status
Simulation time 1203730894 ps
CPU time 8.87 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:03:24 PM PDT 24
Peak memory 199816 kb
Host smart-87198768-121a-416b-8358-2e9257629f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369148198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1369148198
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1517395405
Short name T179
Test name
Test status
Simulation time 20012864 ps
CPU time 0.59 seconds
Started Aug 11 07:03:17 PM PDT 24
Finished Aug 11 07:03:17 PM PDT 24
Peak memory 194908 kb
Host smart-310ab6d3-fdd0-4ce3-b585-b7f451205ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517395405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1517395405
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2738279572
Short name T12
Test name
Test status
Simulation time 2462027590 ps
CPU time 79.47 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:04:35 PM PDT 24
Peak memory 199880 kb
Host smart-18cfdfdc-1c81-41e5-bc8a-9266f0fc59ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738279572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2738279572
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3018308891
Short name T530
Test name
Test status
Simulation time 23794529704 ps
CPU time 51.39 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:04:07 PM PDT 24
Peak memory 199952 kb
Host smart-4b305d8d-5eb9-48c6-9bf2-c79ebd7db70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018308891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3018308891
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3792542280
Short name T282
Test name
Test status
Simulation time 55125306132 ps
CPU time 460.36 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:10:56 PM PDT 24
Peak memory 607008 kb
Host smart-59e4dce8-4693-4609-8574-84c6872b6f75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792542280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3792542280
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.507575062
Short name T305
Test name
Test status
Simulation time 2991468542 ps
CPU time 37.85 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:03:53 PM PDT 24
Peak memory 199948 kb
Host smart-b3c4f152-b418-4669-90bf-050c63c26cec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507575062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.507575062
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.889251288
Short name T313
Test name
Test status
Simulation time 2421111729 ps
CPU time 32.3 seconds
Started Aug 11 07:03:17 PM PDT 24
Finished Aug 11 07:03:49 PM PDT 24
Peak memory 199992 kb
Host smart-9accee49-301b-4556-a72d-6929556a53a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889251288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.889251288
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1218750471
Short name T451
Test name
Test status
Simulation time 987275918 ps
CPU time 11.61 seconds
Started Aug 11 07:03:17 PM PDT 24
Finished Aug 11 07:03:29 PM PDT 24
Peak memory 199872 kb
Host smart-ab1bbac6-7f08-42f4-afee-6df9eb08fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218750471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1218750471
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3840054887
Short name T84
Test name
Test status
Simulation time 100288732871 ps
CPU time 2364.88 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:42:41 PM PDT 24
Peak memory 702008 kb
Host smart-e93c1312-16e7-4002-9b60-902736f1ce7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840054887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3840054887
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3818386591
Short name T85
Test name
Test status
Simulation time 99544793241 ps
CPU time 94.17 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 199848 kb
Host smart-8c96b9f0-9a4a-4fdc-b103-933280dc38ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818386591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3818386591
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.354421567
Short name T156
Test name
Test status
Simulation time 31868776 ps
CPU time 0.58 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:02:36 PM PDT 24
Peak memory 195972 kb
Host smart-5ba337e6-fc32-4b5c-830d-6f437a6b1b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354421567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.354421567
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.784238714
Short name T454
Test name
Test status
Simulation time 1031949630 ps
CPU time 37.39 seconds
Started Aug 11 07:02:50 PM PDT 24
Finished Aug 11 07:03:28 PM PDT 24
Peak memory 199852 kb
Host smart-ed72cfe8-90f2-4022-b178-599b53401345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784238714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.784238714
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3856266444
Short name T306
Test name
Test status
Simulation time 24708911903 ps
CPU time 1059.91 seconds
Started Aug 11 07:02:26 PM PDT 24
Finished Aug 11 07:20:06 PM PDT 24
Peak memory 728564 kb
Host smart-d6ab936e-71e9-4a8c-a427-ef4fcaa876fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856266444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3856266444
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.124558844
Short name T284
Test name
Test status
Simulation time 4661459858 ps
CPU time 77.47 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:03:54 PM PDT 24
Peak memory 199888 kb
Host smart-e021fdf3-b061-4d43-9725-bde791045089
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124558844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.124558844
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2789804150
Short name T352
Test name
Test status
Simulation time 7387399018 ps
CPU time 87.87 seconds
Started Aug 11 07:02:31 PM PDT 24
Finished Aug 11 07:03:59 PM PDT 24
Peak memory 199952 kb
Host smart-d6c93695-6655-4c56-9b47-0ffc5c89a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789804150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2789804150
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3843733478
Short name T36
Test name
Test status
Simulation time 63153034 ps
CPU time 0.8 seconds
Started Aug 11 07:02:34 PM PDT 24
Finished Aug 11 07:02:35 PM PDT 24
Peak memory 218388 kb
Host smart-d798d0e0-4d19-4ab9-ab88-c65bfbbd031a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843733478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3843733478
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1458054620
Short name T512
Test name
Test status
Simulation time 1643352790 ps
CPU time 13.94 seconds
Started Aug 11 07:02:30 PM PDT 24
Finished Aug 11 07:02:44 PM PDT 24
Peak memory 199860 kb
Host smart-3c718414-19d9-489a-8365-049ab2f633f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458054620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1458054620
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.912405566
Short name T13
Test name
Test status
Simulation time 7475243353 ps
CPU time 384.75 seconds
Started Aug 11 07:02:32 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 254148 kb
Host smart-9f5a9362-ce21-4c30-837a-68c24de4b055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912405566 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.912405566
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1574103043
Short name T66
Test name
Test status
Simulation time 26670392604 ps
CPU time 466.09 seconds
Started Aug 11 07:02:35 PM PDT 24
Finished Aug 11 07:10:21 PM PDT 24
Peak memory 208244 kb
Host smart-5b060347-f54d-4f6d-a6fe-fd6aa25e2626
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574103043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1574103043
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1157300188
Short name T144
Test name
Test status
Simulation time 20677325893 ps
CPU time 71.4 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:03:49 PM PDT 24
Peak memory 199976 kb
Host smart-bcc540c3-3730-47e2-baa0-459d89ee0786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1157300188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1157300188
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3209118974
Short name T487
Test name
Test status
Simulation time 7241217453 ps
CPU time 100.16 seconds
Started Aug 11 07:02:32 PM PDT 24
Finished Aug 11 07:04:12 PM PDT 24
Peak memory 199792 kb
Host smart-379542fd-5d1c-42dc-9624-725d6df7e488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3209118974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3209118974
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2130946802
Short name T149
Test name
Test status
Simulation time 20481555330 ps
CPU time 88.3 seconds
Started Aug 11 07:02:34 PM PDT 24
Finished Aug 11 07:04:02 PM PDT 24
Peak memory 199896 kb
Host smart-c37d44da-3f69-4552-af25-71466850a8e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2130946802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2130946802
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2798500427
Short name T206
Test name
Test status
Simulation time 162266380163 ps
CPU time 578.64 seconds
Started Aug 11 07:02:33 PM PDT 24
Finished Aug 11 07:12:12 PM PDT 24
Peak memory 199912 kb
Host smart-d622b0a8-ad35-4615-a8c6-c78587be6596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2798500427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2798500427
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3875226995
Short name T262
Test name
Test status
Simulation time 541683085416 ps
CPU time 2816.74 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:49:33 PM PDT 24
Peak memory 215300 kb
Host smart-21a0e092-9472-4b0d-914a-6c7d0a0a1bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3875226995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3875226995
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2643931806
Short name T221
Test name
Test status
Simulation time 84726010553 ps
CPU time 2388.91 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:42:27 PM PDT 24
Peak memory 216160 kb
Host smart-54bf9bef-0593-49a1-b5ad-80bb67ae8222
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2643931806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2643931806
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.593146452
Short name T72
Test name
Test status
Simulation time 5132483071 ps
CPU time 43.62 seconds
Started Aug 11 07:02:33 PM PDT 24
Finished Aug 11 07:03:17 PM PDT 24
Peak memory 199872 kb
Host smart-7991c013-68b0-4d51-a43b-55f6623a5a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593146452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.593146452
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.816439387
Short name T54
Test name
Test status
Simulation time 37361417 ps
CPU time 0.58 seconds
Started Aug 11 07:03:22 PM PDT 24
Finished Aug 11 07:03:23 PM PDT 24
Peak memory 194900 kb
Host smart-fdd4efa0-7909-47e0-addf-f61ea24e21ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816439387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.816439387
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2081763243
Short name T200
Test name
Test status
Simulation time 220968507 ps
CPU time 13.03 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:03:29 PM PDT 24
Peak memory 199860 kb
Host smart-34c9a8c9-8a30-4ec8-b12c-e12080611153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081763243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2081763243
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.857732976
Short name T527
Test name
Test status
Simulation time 2986306562 ps
CPU time 57.22 seconds
Started Aug 11 07:03:16 PM PDT 24
Finished Aug 11 07:04:14 PM PDT 24
Peak memory 216080 kb
Host smart-020ca754-e8c8-4dd4-b272-201902766123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857732976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.857732976
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.787592363
Short name T486
Test name
Test status
Simulation time 6758390868 ps
CPU time 1192.54 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:23:08 PM PDT 24
Peak memory 746416 kb
Host smart-4546e742-c348-424e-9841-ce538c9de639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787592363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.787592363
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2360279063
Short name T526
Test name
Test status
Simulation time 15481106758 ps
CPU time 83.33 seconds
Started Aug 11 07:03:22 PM PDT 24
Finished Aug 11 07:04:46 PM PDT 24
Peak memory 199900 kb
Host smart-ece2cc62-cbbc-4b08-ac25-50d2ecc58735
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360279063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2360279063
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1744507375
Short name T277
Test name
Test status
Simulation time 19304575671 ps
CPU time 66.35 seconds
Started Aug 11 07:03:17 PM PDT 24
Finished Aug 11 07:04:23 PM PDT 24
Peak memory 199952 kb
Host smart-c2796c9f-9a02-42c4-b900-b04041d8fc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744507375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1744507375
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3229184753
Short name T443
Test name
Test status
Simulation time 454893286 ps
CPU time 5.75 seconds
Started Aug 11 07:03:15 PM PDT 24
Finished Aug 11 07:03:21 PM PDT 24
Peak memory 199928 kb
Host smart-92d2f91d-d1fa-482c-a72f-2b40ebd79388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229184753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3229184753
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2668954535
Short name T117
Test name
Test status
Simulation time 106841719072 ps
CPU time 1349.12 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:25:51 PM PDT 24
Peak memory 729464 kb
Host smart-d58b9446-922f-455a-a3b6-c2f94ef0e42d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668954535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2668954535
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3418814099
Short name T192
Test name
Test status
Simulation time 3931930371 ps
CPU time 70.05 seconds
Started Aug 11 07:03:22 PM PDT 24
Finished Aug 11 07:04:32 PM PDT 24
Peak memory 200048 kb
Host smart-6dd1a9f8-e693-4d71-8525-c0a8ffc33a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418814099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3418814099
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.737622519
Short name T297
Test name
Test status
Simulation time 31898207 ps
CPU time 0.55 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:03:22 PM PDT 24
Peak memory 195544 kb
Host smart-b7ed9692-c0d1-4c4a-94e7-0532e75eff39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737622519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.737622519
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1204744551
Short name T511
Test name
Test status
Simulation time 227691808 ps
CPU time 12.36 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:03:34 PM PDT 24
Peak memory 199860 kb
Host smart-baf1b781-a61a-449e-9719-80d5356ca2eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204744551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1204744551
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4007540967
Short name T505
Test name
Test status
Simulation time 1275767577 ps
CPU time 69 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:04:31 PM PDT 24
Peak memory 199812 kb
Host smart-35737b50-37d4-4ed3-80ce-fcf68ea2eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007540967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4007540967
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1027310153
Short name T188
Test name
Test status
Simulation time 17514075605 ps
CPU time 726.95 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:15:28 PM PDT 24
Peak memory 655760 kb
Host smart-cb2634b6-6fdb-4264-bdff-b8d0959c106b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027310153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1027310153
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.740514426
Short name T354
Test name
Test status
Simulation time 3889520540 ps
CPU time 51.1 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:04:12 PM PDT 24
Peak memory 199876 kb
Host smart-b5f61da4-ae36-4c62-9364-8470937f6f54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740514426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.740514426
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.432872003
Short name T378
Test name
Test status
Simulation time 1012162573 ps
CPU time 57.91 seconds
Started Aug 11 07:03:22 PM PDT 24
Finished Aug 11 07:04:20 PM PDT 24
Peak memory 199856 kb
Host smart-67bb36d1-f33b-4de6-8a08-975acdc43a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432872003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.432872003
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1637497992
Short name T320
Test name
Test status
Simulation time 690421490 ps
CPU time 8.31 seconds
Started Aug 11 07:03:22 PM PDT 24
Finished Aug 11 07:03:31 PM PDT 24
Peak memory 199828 kb
Host smart-facabc80-f015-4ee5-9fc1-eb96d7223eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637497992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1637497992
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2980923397
Short name T82
Test name
Test status
Simulation time 86607248 ps
CPU time 0.61 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:03:22 PM PDT 24
Peak memory 195552 kb
Host smart-f65f5e97-45aa-469d-a8f0-083fb60d3882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980923397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2980923397
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.564676882
Short name T335
Test name
Test status
Simulation time 33478725362 ps
CPU time 92.04 seconds
Started Aug 11 07:03:21 PM PDT 24
Finished Aug 11 07:04:53 PM PDT 24
Peak memory 199884 kb
Host smart-bb127a9c-b49a-4e27-9557-a06f6351afea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564676882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.564676882
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2313870035
Short name T205
Test name
Test status
Simulation time 14207230 ps
CPU time 0.59 seconds
Started Aug 11 07:03:30 PM PDT 24
Finished Aug 11 07:03:30 PM PDT 24
Peak memory 195556 kb
Host smart-4f3c389c-a50e-4718-8347-82f92e5caa75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313870035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2313870035
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2762372394
Short name T132
Test name
Test status
Simulation time 792291577 ps
CPU time 36.8 seconds
Started Aug 11 07:03:27 PM PDT 24
Finished Aug 11 07:04:04 PM PDT 24
Peak memory 199788 kb
Host smart-a903fb93-7fed-41fd-abb2-e479f0d45787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762372394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2762372394
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.230972967
Short name T364
Test name
Test status
Simulation time 18128031008 ps
CPU time 847.54 seconds
Started Aug 11 07:03:29 PM PDT 24
Finished Aug 11 07:17:37 PM PDT 24
Peak memory 745132 kb
Host smart-5bee937b-5b29-47a7-a08d-bf83d5ad4f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230972967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.230972967
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.46740237
Short name T407
Test name
Test status
Simulation time 1839770044 ps
CPU time 99.02 seconds
Started Aug 11 07:03:30 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 199832 kb
Host smart-4220b9aa-c411-4b59-b7d4-7f1a0bcc0a90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46740237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.46740237
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1117129108
Short name T318
Test name
Test status
Simulation time 18474269757 ps
CPU time 80.37 seconds
Started Aug 11 07:03:28 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 199884 kb
Host smart-5cf86039-c724-43b4-a54d-24fcde407742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117129108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1117129108
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.119776942
Short name T337
Test name
Test status
Simulation time 1186148458 ps
CPU time 7.84 seconds
Started Aug 11 07:03:23 PM PDT 24
Finished Aug 11 07:03:30 PM PDT 24
Peak memory 199892 kb
Host smart-f701ae7d-2fe8-463e-8699-97a916865443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119776942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.119776942
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2851410442
Short name T376
Test name
Test status
Simulation time 20734901047 ps
CPU time 1945.72 seconds
Started Aug 11 07:03:30 PM PDT 24
Finished Aug 11 07:35:56 PM PDT 24
Peak memory 770516 kb
Host smart-5f1b5fc6-e61c-40cc-b14a-3e7c0dd7a524
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851410442 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2851410442
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1904273171
Short name T44
Test name
Test status
Simulation time 583673371 ps
CPU time 11.03 seconds
Started Aug 11 07:03:28 PM PDT 24
Finished Aug 11 07:03:39 PM PDT 24
Peak memory 199832 kb
Host smart-afc358ba-166e-4025-9a40-d3c105f772e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904273171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1904273171
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2726246967
Short name T314
Test name
Test status
Simulation time 63863692 ps
CPU time 0.59 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:03:35 PM PDT 24
Peak memory 196576 kb
Host smart-a53bbc40-e863-4bc6-9d86-36f50e39f7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726246967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2726246967
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2742214043
Short name T444
Test name
Test status
Simulation time 2338047302 ps
CPU time 38.17 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:04:13 PM PDT 24
Peak memory 199908 kb
Host smart-2f7aa7ec-d93b-4596-b3c8-630cffe7cb91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742214043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2742214043
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2603138892
Short name T279
Test name
Test status
Simulation time 3686044749 ps
CPU time 18.7 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:03:52 PM PDT 24
Peak memory 199904 kb
Host smart-b03a4969-9d9c-4b94-8811-8b67ab19a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603138892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2603138892
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.690981632
Short name T269
Test name
Test status
Simulation time 32020706256 ps
CPU time 497.32 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:11:51 PM PDT 24
Peak memory 655932 kb
Host smart-78502788-0538-401e-8c20-5ae089a814e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690981632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.690981632
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.622817899
Short name T229
Test name
Test status
Simulation time 8440142140 ps
CPU time 33.23 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:04:06 PM PDT 24
Peak memory 199964 kb
Host smart-6065b1aa-9d50-45da-869c-caec0830ccf8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622817899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.622817899
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1551561547
Short name T430
Test name
Test status
Simulation time 4596228330 ps
CPU time 24.35 seconds
Started Aug 11 07:03:27 PM PDT 24
Finished Aug 11 07:03:52 PM PDT 24
Peak memory 199980 kb
Host smart-93ec11c6-6036-4098-9def-8b7686b946c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551561547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1551561547
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.680385767
Short name T136
Test name
Test status
Simulation time 1009758264 ps
CPU time 4.68 seconds
Started Aug 11 07:03:29 PM PDT 24
Finished Aug 11 07:03:34 PM PDT 24
Peak memory 199832 kb
Host smart-80504d99-7dbe-4b64-b523-7014f3b5756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680385767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.680385767
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2273377198
Short name T194
Test name
Test status
Simulation time 540003417264 ps
CPU time 552.02 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:12:45 PM PDT 24
Peak memory 373600 kb
Host smart-d13d6b36-8335-4ac7-b8aa-e9618237d659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273377198 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2273377198
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.640847977
Short name T87
Test name
Test status
Simulation time 19758761287 ps
CPU time 101.12 seconds
Started Aug 11 07:03:37 PM PDT 24
Finished Aug 11 07:05:19 PM PDT 24
Peak memory 199948 kb
Host smart-1fb91d14-0b66-4898-81ba-38b3e8ca6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640847977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.640847977
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1145811128
Short name T245
Test name
Test status
Simulation time 13876032 ps
CPU time 0.61 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:03:35 PM PDT 24
Peak memory 195896 kb
Host smart-1a13b08f-3897-477f-9a49-fcb64dc50818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145811128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1145811128
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2377285813
Short name T317
Test name
Test status
Simulation time 3969398231 ps
CPU time 105.8 seconds
Started Aug 11 07:03:32 PM PDT 24
Finished Aug 11 07:05:18 PM PDT 24
Peak memory 199944 kb
Host smart-468ec41f-204d-4a73-be6d-ba4ca05d168a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377285813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2377285813
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2128906194
Short name T448
Test name
Test status
Simulation time 2871825572 ps
CPU time 51.53 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:04:26 PM PDT 24
Peak memory 199916 kb
Host smart-61c1f24b-8400-4be5-bcc8-2ce7eedd660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128906194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2128906194
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3984394320
Short name T460
Test name
Test status
Simulation time 8324003183 ps
CPU time 1754.5 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:32:48 PM PDT 24
Peak memory 776920 kb
Host smart-9de8950c-6e14-4694-b927-187cbc9aec4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984394320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3984394320
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.150877378
Short name T445
Test name
Test status
Simulation time 35464739842 ps
CPU time 85.12 seconds
Started Aug 11 07:03:36 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 199980 kb
Host smart-86b74310-e466-4def-b3ef-70a14c78b7be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150877378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.150877378
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.401458757
Short name T266
Test name
Test status
Simulation time 3096229167 ps
CPU time 57.28 seconds
Started Aug 11 07:03:37 PM PDT 24
Finished Aug 11 07:04:34 PM PDT 24
Peak memory 199916 kb
Host smart-bc85f803-0182-4959-8b8e-375a07a4b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401458757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.401458757
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1251820657
Short name T411
Test name
Test status
Simulation time 251297155 ps
CPU time 11.02 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:03:45 PM PDT 24
Peak memory 199852 kb
Host smart-59b19727-1bc4-48cf-a0d9-873daf06c883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251820657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1251820657
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1316309027
Short name T494
Test name
Test status
Simulation time 24845043743 ps
CPU time 81.92 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:04:56 PM PDT 24
Peak memory 199956 kb
Host smart-4172aa7b-2bc0-4b13-a232-5610ef77b9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316309027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1316309027
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3642620443
Short name T449
Test name
Test status
Simulation time 41260599 ps
CPU time 0.58 seconds
Started Aug 11 07:03:37 PM PDT 24
Finished Aug 11 07:03:38 PM PDT 24
Peak memory 195552 kb
Host smart-ea315079-25cc-4b1a-a9ad-2636d1e38e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642620443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3642620443
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.744837572
Short name T315
Test name
Test status
Simulation time 1162521057 ps
CPU time 64.81 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:04:38 PM PDT 24
Peak memory 199828 kb
Host smart-14006d4a-6f4f-4a62-b15a-6c4235229ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744837572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.744837572
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.525825043
Short name T469
Test name
Test status
Simulation time 4394050144 ps
CPU time 15.64 seconds
Started Aug 11 07:03:35 PM PDT 24
Finished Aug 11 07:03:50 PM PDT 24
Peak memory 199940 kb
Host smart-448b0fbb-1b81-4033-9003-ab8ced19abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525825043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.525825043
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3132833129
Short name T209
Test name
Test status
Simulation time 5912283948 ps
CPU time 1118.17 seconds
Started Aug 11 07:03:32 PM PDT 24
Finished Aug 11 07:22:11 PM PDT 24
Peak memory 711596 kb
Host smart-3a18c643-a2b4-4f31-85a3-c5ec4ade2cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132833129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3132833129
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2658428956
Short name T152
Test name
Test status
Simulation time 22899840833 ps
CPU time 150.31 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:06:04 PM PDT 24
Peak memory 199916 kb
Host smart-3db34259-a4ac-463f-bfd7-0562ae1d88b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658428956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2658428956
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2246257018
Short name T240
Test name
Test status
Simulation time 11180888485 ps
CPU time 68.75 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:04:42 PM PDT 24
Peak memory 199968 kb
Host smart-3b61c65f-7c7f-4434-aa9c-2b3aa6466646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246257018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2246257018
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4054170588
Short name T233
Test name
Test status
Simulation time 537662486 ps
CPU time 7.62 seconds
Started Aug 11 07:03:37 PM PDT 24
Finished Aug 11 07:03:45 PM PDT 24
Peak memory 199832 kb
Host smart-cf261cca-908a-4b46-a44d-03256ff1270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054170588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4054170588
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3389797127
Short name T86
Test name
Test status
Simulation time 116511996868 ps
CPU time 2612.25 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:47:06 PM PDT 24
Peak memory 762648 kb
Host smart-83affa6f-dbee-439a-836e-55aaf8f3138e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389797127 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3389797127
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3927920336
Short name T329
Test name
Test status
Simulation time 21937986086 ps
CPU time 80.09 seconds
Started Aug 11 07:03:35 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 199940 kb
Host smart-52f168e8-d4da-4247-bee0-a5dedc77fbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927920336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3927920336
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2221963122
Short name T374
Test name
Test status
Simulation time 22965362 ps
CPU time 0.58 seconds
Started Aug 11 07:03:38 PM PDT 24
Finished Aug 11 07:03:39 PM PDT 24
Peak memory 196628 kb
Host smart-294de79b-c731-4be3-8dec-44058a2d03b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221963122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2221963122
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3141885352
Short name T236
Test name
Test status
Simulation time 2804029068 ps
CPU time 27.27 seconds
Started Aug 11 07:03:36 PM PDT 24
Finished Aug 11 07:04:04 PM PDT 24
Peak memory 199916 kb
Host smart-3775fa01-3c3a-4fd5-98d7-3d4a74430dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141885352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3141885352
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3807776402
Short name T141
Test name
Test status
Simulation time 585353399 ps
CPU time 31.83 seconds
Started Aug 11 07:03:39 PM PDT 24
Finished Aug 11 07:04:11 PM PDT 24
Peak memory 199908 kb
Host smart-f7b7fa78-0299-44c4-b7f2-387ded2e63a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807776402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3807776402
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1492395032
Short name T199
Test name
Test status
Simulation time 4906127811 ps
CPU time 981.8 seconds
Started Aug 11 07:03:39 PM PDT 24
Finished Aug 11 07:20:01 PM PDT 24
Peak memory 750424 kb
Host smart-d54ab784-1c46-4858-a3f4-94c4f9be909f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492395032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1492395032
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1290298637
Short name T292
Test name
Test status
Simulation time 9674206769 ps
CPU time 33.63 seconds
Started Aug 11 07:03:40 PM PDT 24
Finished Aug 11 07:04:14 PM PDT 24
Peak memory 199956 kb
Host smart-e4d94b3a-dac6-4f61-b9b8-24df04a770ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290298637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1290298637
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3128791671
Short name T377
Test name
Test status
Simulation time 26580769358 ps
CPU time 250.27 seconds
Started Aug 11 07:03:33 PM PDT 24
Finished Aug 11 07:07:44 PM PDT 24
Peak memory 216204 kb
Host smart-2d587270-b4ce-49ce-9f30-e3ffc357b2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128791671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3128791671
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1500054352
Short name T333
Test name
Test status
Simulation time 229738601 ps
CPU time 10.41 seconds
Started Aug 11 07:03:34 PM PDT 24
Finished Aug 11 07:03:44 PM PDT 24
Peak memory 199824 kb
Host smart-05c5165e-f938-447b-ba75-afc4545b63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500054352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1500054352
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3224654129
Short name T114
Test name
Test status
Simulation time 6582126316 ps
CPU time 69.97 seconds
Started Aug 11 07:03:40 PM PDT 24
Finished Aug 11 07:04:50 PM PDT 24
Peak memory 199904 kb
Host smart-bc4f4d06-6782-4684-b7a1-f00e7a44240f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224654129 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3224654129
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4065138520
Short name T482
Test name
Test status
Simulation time 2948863969 ps
CPU time 73.76 seconds
Started Aug 11 07:03:39 PM PDT 24
Finished Aug 11 07:04:53 PM PDT 24
Peak memory 199908 kb
Host smart-2f890254-29fb-478d-9bdf-4a4c2b5c64f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065138520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4065138520
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.529121618
Short name T217
Test name
Test status
Simulation time 12871529 ps
CPU time 0.58 seconds
Started Aug 11 07:03:39 PM PDT 24
Finished Aug 11 07:03:39 PM PDT 24
Peak memory 195920 kb
Host smart-98c73579-2b07-4bda-ae9c-94266a8973e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529121618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.529121618
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3802717921
Short name T465
Test name
Test status
Simulation time 1517636312 ps
CPU time 88.67 seconds
Started Aug 11 07:03:40 PM PDT 24
Finished Aug 11 07:05:09 PM PDT 24
Peak memory 199892 kb
Host smart-3fc37d63-d203-4ec0-b784-607596bf7351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802717921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3802717921
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1998881608
Short name T48
Test name
Test status
Simulation time 1482890485 ps
CPU time 26.14 seconds
Started Aug 11 07:03:42 PM PDT 24
Finished Aug 11 07:04:09 PM PDT 24
Peak memory 199852 kb
Host smart-87df0219-224b-4e42-9b39-6d9868fc74ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998881608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1998881608
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1246591364
Short name T184
Test name
Test status
Simulation time 3975072341 ps
CPU time 392.58 seconds
Started Aug 11 07:03:40 PM PDT 24
Finished Aug 11 07:10:12 PM PDT 24
Peak memory 666472 kb
Host smart-b96d7475-01f3-4951-91bf-6eb50906d558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246591364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1246591364
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4136896396
Short name T220
Test name
Test status
Simulation time 265385139 ps
CPU time 3.83 seconds
Started Aug 11 07:03:40 PM PDT 24
Finished Aug 11 07:03:44 PM PDT 24
Peak memory 199780 kb
Host smart-9f8c14c2-32dd-48fe-8c6e-e1be6c52e3d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136896396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4136896396
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_smoke.191702802
Short name T492
Test name
Test status
Simulation time 505302922 ps
CPU time 3.53 seconds
Started Aug 11 07:03:39 PM PDT 24
Finished Aug 11 07:03:43 PM PDT 24
Peak memory 199880 kb
Host smart-07629ea6-5928-44dc-9f60-bf42173584ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191702802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.191702802
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1735034446
Short name T268
Test name
Test status
Simulation time 518598428004 ps
CPU time 1503.44 seconds
Started Aug 11 07:03:43 PM PDT 24
Finished Aug 11 07:28:46 PM PDT 24
Peak memory 216296 kb
Host smart-e82e476f-151f-441f-a0b3-c65f5d58835a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735034446 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1735034446
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1257950518
Short name T161
Test name
Test status
Simulation time 189212108 ps
CPU time 5.49 seconds
Started Aug 11 07:03:42 PM PDT 24
Finished Aug 11 07:03:48 PM PDT 24
Peak memory 199712 kb
Host smart-cc89ec5e-b152-4465-9e11-da5cb46f2330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257950518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1257950518
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3544298471
Short name T325
Test name
Test status
Simulation time 24066106 ps
CPU time 0.6 seconds
Started Aug 11 07:03:46 PM PDT 24
Finished Aug 11 07:03:47 PM PDT 24
Peak memory 195868 kb
Host smart-42693a4c-f3cf-4615-8823-04b04ac5e607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544298471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3544298471
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3856949062
Short name T42
Test name
Test status
Simulation time 1753303906 ps
CPU time 27.09 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:04:14 PM PDT 24
Peak memory 199828 kb
Host smart-b1f21f63-b93d-4c49-800d-6922be6d3225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856949062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3856949062
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3107702965
Short name T520
Test name
Test status
Simulation time 8128475480 ps
CPU time 27.68 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:04:15 PM PDT 24
Peak memory 199952 kb
Host smart-60a56449-2f8f-461b-8591-29a8c3a0a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107702965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3107702965
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3989150266
Short name T202
Test name
Test status
Simulation time 4956133929 ps
CPU time 1024.89 seconds
Started Aug 11 07:03:46 PM PDT 24
Finished Aug 11 07:20:52 PM PDT 24
Peak memory 741964 kb
Host smart-72685d5e-47b1-4cb3-a298-701f0ac924cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989150266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3989150266
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3575910381
Short name T169
Test name
Test status
Simulation time 10624288237 ps
CPU time 135.53 seconds
Started Aug 11 07:03:44 PM PDT 24
Finished Aug 11 07:06:00 PM PDT 24
Peak memory 199876 kb
Host smart-5f6e5491-61d4-4a8b-a14e-b574afe7cb27
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575910381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3575910381
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1243656988
Short name T389
Test name
Test status
Simulation time 6450994396 ps
CPU time 23.93 seconds
Started Aug 11 07:03:45 PM PDT 24
Finished Aug 11 07:04:09 PM PDT 24
Peak memory 199864 kb
Host smart-d85af855-c2dc-41d5-9786-edbce4311163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243656988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1243656988
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1682888828
Short name T270
Test name
Test status
Simulation time 1568228976 ps
CPU time 12.35 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:03:59 PM PDT 24
Peak memory 199892 kb
Host smart-8cc86937-a67e-417a-b67e-78cdaaf06492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682888828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1682888828
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.892526754
Short name T248
Test name
Test status
Simulation time 6658809443 ps
CPU time 264.88 seconds
Started Aug 11 07:03:46 PM PDT 24
Finished Aug 11 07:08:11 PM PDT 24
Peak memory 451912 kb
Host smart-d5c8d49b-8e4e-4a29-9193-fce90151054f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892526754 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.892526754
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2676315360
Short name T111
Test name
Test status
Simulation time 349766785 ps
CPU time 17.68 seconds
Started Aug 11 07:03:46 PM PDT 24
Finished Aug 11 07:04:03 PM PDT 24
Peak memory 199780 kb
Host smart-da641467-a16b-4358-9e51-e0ea4c331ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676315360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2676315360
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3732030306
Short name T273
Test name
Test status
Simulation time 46364994 ps
CPU time 0.62 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:03:47 PM PDT 24
Peak memory 195952 kb
Host smart-3d91cfd6-3acf-4765-90d8-5a9fae5696a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732030306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3732030306
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.510045693
Short name T464
Test name
Test status
Simulation time 3311374864 ps
CPU time 46.6 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:04:33 PM PDT 24
Peak memory 199904 kb
Host smart-d8ff393e-855d-4250-95ad-ac2ab70637bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510045693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.510045693
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1145802730
Short name T77
Test name
Test status
Simulation time 40409712220 ps
CPU time 44.98 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:04:32 PM PDT 24
Peak memory 199988 kb
Host smart-bf875baa-18cc-494b-aff1-1c3d1766555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145802730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1145802730
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3577923472
Short name T151
Test name
Test status
Simulation time 8391602491 ps
CPU time 907.73 seconds
Started Aug 11 07:03:46 PM PDT 24
Finished Aug 11 07:18:54 PM PDT 24
Peak memory 683064 kb
Host smart-dad98aa1-f7bb-4e7f-bfba-fbe844763f58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577923472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3577923472
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2053471671
Short name T391
Test name
Test status
Simulation time 10912484637 ps
CPU time 136.98 seconds
Started Aug 11 07:03:45 PM PDT 24
Finished Aug 11 07:06:02 PM PDT 24
Peak memory 199988 kb
Host smart-1d12db88-8975-41aa-8287-73523e970e7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053471671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2053471671
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2176916967
Short name T276
Test name
Test status
Simulation time 44858898682 ps
CPU time 138.17 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:06:06 PM PDT 24
Peak memory 199900 kb
Host smart-0f6efc48-2282-49cf-87db-fc7ce44a3887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176916967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2176916967
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2689026969
Short name T5
Test name
Test status
Simulation time 1526259362 ps
CPU time 12.32 seconds
Started Aug 11 07:03:46 PM PDT 24
Finished Aug 11 07:03:58 PM PDT 24
Peak memory 199804 kb
Host smart-6557f4d8-f343-4192-9e18-10a70b33e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689026969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2689026969
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3834717531
Short name T452
Test name
Test status
Simulation time 55976562380 ps
CPU time 841.78 seconds
Started Aug 11 07:03:44 PM PDT 24
Finished Aug 11 07:17:46 PM PDT 24
Peak memory 429216 kb
Host smart-0db3d2b5-8e64-4081-8239-d33889f71199
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834717531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3834717531
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4293846673
Short name T421
Test name
Test status
Simulation time 875132211 ps
CPU time 47.09 seconds
Started Aug 11 07:03:45 PM PDT 24
Finished Aug 11 07:04:32 PM PDT 24
Peak memory 199860 kb
Host smart-69fe75b0-9d9e-4d85-8129-107826b01e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293846673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4293846673
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1603886363
Short name T491
Test name
Test status
Simulation time 12049124 ps
CPU time 0.62 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:02:39 PM PDT 24
Peak memory 195968 kb
Host smart-37b7e658-659e-49ad-b580-493239e482df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603886363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1603886363
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3728768717
Short name T435
Test name
Test status
Simulation time 2244047131 ps
CPU time 85.07 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:04:01 PM PDT 24
Peak memory 199924 kb
Host smart-64d3e159-9c8f-4edd-8b92-71259a22a76c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728768717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3728768717
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3332745564
Short name T237
Test name
Test status
Simulation time 4865756198 ps
CPU time 21.19 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:02:57 PM PDT 24
Peak memory 199972 kb
Host smart-cf9a3da6-3049-4023-88a0-07efb237fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332745564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3332745564
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.194210076
Short name T181
Test name
Test status
Simulation time 14393998067 ps
CPU time 482.97 seconds
Started Aug 11 07:02:33 PM PDT 24
Finished Aug 11 07:10:36 PM PDT 24
Peak memory 689060 kb
Host smart-4668ad34-f82c-467d-8797-f447912831d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194210076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.194210076
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.9278168
Short name T7
Test name
Test status
Simulation time 7105533874 ps
CPU time 126.34 seconds
Started Aug 11 07:02:33 PM PDT 24
Finished Aug 11 07:04:39 PM PDT 24
Peak memory 199868 kb
Host smart-de9f62f8-0175-4d68-b72c-8977718ce171
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9278168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.9278168
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1474827964
Short name T246
Test name
Test status
Simulation time 13188231630 ps
CPU time 85.84 seconds
Started Aug 11 07:02:32 PM PDT 24
Finished Aug 11 07:03:58 PM PDT 24
Peak memory 199892 kb
Host smart-5abbb96a-2f4d-4a4e-a288-4df6dbdb2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474827964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1474827964
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2464323231
Short name T56
Test name
Test status
Simulation time 158626963 ps
CPU time 0.84 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:02:41 PM PDT 24
Peak memory 218500 kb
Host smart-3783e205-af6a-4a74-9787-7684053bf538
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464323231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2464323231
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3580908365
Short name T177
Test name
Test status
Simulation time 2469631105 ps
CPU time 9.42 seconds
Started Aug 11 07:02:34 PM PDT 24
Finished Aug 11 07:02:44 PM PDT 24
Peak memory 200052 kb
Host smart-550d7297-e8f0-4806-a6ba-dde263c6b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580908365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3580908365
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.818881851
Short name T80
Test name
Test status
Simulation time 33563955821 ps
CPU time 423.91 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:09:44 PM PDT 24
Peak memory 216256 kb
Host smart-0f74b81c-ca95-4e43-88b8-3150788e9764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818881851 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.818881851
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2735320814
Short name T190
Test name
Test status
Simulation time 3040083237 ps
CPU time 47.99 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:03:28 PM PDT 24
Peak memory 199908 kb
Host smart-4b6c5c4a-3e78-4df1-97ef-7c72a4c1ea5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2735320814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2735320814
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1665418247
Short name T330
Test name
Test status
Simulation time 8635532444 ps
CPU time 96.08 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:04:23 PM PDT 24
Peak memory 199904 kb
Host smart-1d00dd8e-e477-4c6d-b4d8-048a58281d7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1665418247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1665418247
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.411248353
Short name T310
Test name
Test status
Simulation time 75695658120 ps
CPU time 79.37 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:03:59 PM PDT 24
Peak memory 200124 kb
Host smart-a7ed4e68-e34b-4fc2-8c5b-823167d5754a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=411248353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.411248353
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.686894552
Short name T525
Test name
Test status
Simulation time 186765030195 ps
CPU time 611.04 seconds
Started Aug 11 07:02:36 PM PDT 24
Finished Aug 11 07:12:47 PM PDT 24
Peak memory 199840 kb
Host smart-4a83a743-846b-4ba4-82df-f99479a9baec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=686894552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.686894552
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.116801949
Short name T400
Test name
Test status
Simulation time 134610861322 ps
CPU time 2296.95 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:40:56 PM PDT 24
Peak memory 215404 kb
Host smart-7131a0ad-6917-41cb-8bb6-44efb84a6b34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=116801949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.116801949
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.30996051
Short name T504
Test name
Test status
Simulation time 36683860751 ps
CPU time 2078.64 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:37:24 PM PDT 24
Peak memory 216128 kb
Host smart-14cab2ab-f8de-41ca-8835-49ded9b835b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=30996051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.30996051
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1295986126
Short name T219
Test name
Test status
Simulation time 2662379743 ps
CPU time 114.45 seconds
Started Aug 11 07:02:32 PM PDT 24
Finished Aug 11 07:04:26 PM PDT 24
Peak memory 199908 kb
Host smart-cad67e76-ddaf-40c9-a00a-a5b129bd8853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295986126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1295986126
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1057060641
Short name T348
Test name
Test status
Simulation time 49551290 ps
CPU time 0.62 seconds
Started Aug 11 07:03:53 PM PDT 24
Finished Aug 11 07:03:53 PM PDT 24
Peak memory 196648 kb
Host smart-7151ca36-4cb5-4cc8-995f-55c3897923a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057060641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1057060641
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.4212691699
Short name T150
Test name
Test status
Simulation time 509300883 ps
CPU time 26.78 seconds
Started Aug 11 07:03:55 PM PDT 24
Finished Aug 11 07:04:22 PM PDT 24
Peak memory 199848 kb
Host smart-53f28f22-1b24-4f1c-a5fb-88efb8064430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212691699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4212691699
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3002850899
Short name T361
Test name
Test status
Simulation time 602722493 ps
CPU time 4.23 seconds
Started Aug 11 07:03:55 PM PDT 24
Finished Aug 11 07:03:59 PM PDT 24
Peak memory 199744 kb
Host smart-870b9c57-2650-45aa-afca-930bfff36076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002850899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3002850899
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1640557686
Short name T497
Test name
Test status
Simulation time 21838634130 ps
CPU time 968.17 seconds
Started Aug 11 07:03:53 PM PDT 24
Finished Aug 11 07:20:02 PM PDT 24
Peak memory 683016 kb
Host smart-a8836b0c-6664-4103-b69d-e66c71428a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640557686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1640557686
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.132884877
Short name T251
Test name
Test status
Simulation time 1705370022 ps
CPU time 91.51 seconds
Started Aug 11 07:03:52 PM PDT 24
Finished Aug 11 07:05:24 PM PDT 24
Peak memory 199816 kb
Host smart-da7e172d-a904-4b5d-a84e-da6199f90528
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132884877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.132884877
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2619939813
Short name T43
Test name
Test status
Simulation time 6473630165 ps
CPU time 58.22 seconds
Started Aug 11 07:03:47 PM PDT 24
Finished Aug 11 07:04:45 PM PDT 24
Peak memory 199912 kb
Host smart-dc524672-64d9-4b5c-8900-8b22b4bf9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619939813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2619939813
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.589149010
Short name T470
Test name
Test status
Simulation time 1268410834 ps
CPU time 14.64 seconds
Started Aug 11 07:03:49 PM PDT 24
Finished Aug 11 07:04:04 PM PDT 24
Peak memory 199848 kb
Host smart-835f0684-c2f9-4fc7-8bd9-ac9b5a03d0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589149010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.589149010
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1331185668
Short name T447
Test name
Test status
Simulation time 69847729773 ps
CPU time 805.58 seconds
Started Aug 11 07:03:51 PM PDT 24
Finished Aug 11 07:17:17 PM PDT 24
Peak memory 199912 kb
Host smart-1683c072-b488-4c24-8cd5-3fe00f1febc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331185668 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1331185668
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3264984968
Short name T112
Test name
Test status
Simulation time 32188063135 ps
CPU time 143.65 seconds
Started Aug 11 07:03:52 PM PDT 24
Finished Aug 11 07:06:15 PM PDT 24
Peak memory 199856 kb
Host smart-e4af2aa2-362c-47f3-9f50-c529b06bd3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264984968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3264984968
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.713808096
Short name T434
Test name
Test status
Simulation time 21819179 ps
CPU time 0.59 seconds
Started Aug 11 07:03:55 PM PDT 24
Finished Aug 11 07:03:56 PM PDT 24
Peak memory 194928 kb
Host smart-6ac95427-c900-4dd8-94cf-6b70d5b42bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713808096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.713808096
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.480058900
Short name T412
Test name
Test status
Simulation time 361793146 ps
CPU time 18.87 seconds
Started Aug 11 07:03:55 PM PDT 24
Finished Aug 11 07:04:14 PM PDT 24
Peak memory 199828 kb
Host smart-d6c5dad8-b23f-46a0-85c6-269d45be8429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480058900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.480058900
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2638452796
Short name T357
Test name
Test status
Simulation time 36087274088 ps
CPU time 56.32 seconds
Started Aug 11 07:03:52 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 199904 kb
Host smart-bc75c704-8a77-409d-913d-729a49821006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638452796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2638452796
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1719140594
Short name T355
Test name
Test status
Simulation time 2563889273 ps
CPU time 60.55 seconds
Started Aug 11 07:03:52 PM PDT 24
Finished Aug 11 07:04:53 PM PDT 24
Peak memory 316232 kb
Host smart-3195f4c5-9e50-463d-a3ca-2df33ef0f2af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719140594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1719140594
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3997414230
Short name T467
Test name
Test status
Simulation time 1724422447 ps
CPU time 89.16 seconds
Started Aug 11 07:03:51 PM PDT 24
Finished Aug 11 07:05:20 PM PDT 24
Peak memory 199756 kb
Host smart-3bef2452-8ef9-4911-944c-247c9d4d1b73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997414230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3997414230
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3593821450
Short name T351
Test name
Test status
Simulation time 4610068039 ps
CPU time 85.64 seconds
Started Aug 11 07:03:51 PM PDT 24
Finished Aug 11 07:05:17 PM PDT 24
Peak memory 200060 kb
Host smart-195b70d3-274e-4848-808c-ac3f5def15cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593821450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3593821450
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1203068196
Short name T256
Test name
Test status
Simulation time 1668225349 ps
CPU time 5.65 seconds
Started Aug 11 07:03:56 PM PDT 24
Finished Aug 11 07:04:02 PM PDT 24
Peak memory 199788 kb
Host smart-1bbcc67d-bc28-41d8-8df5-7e07cd742a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203068196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1203068196
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.4230779217
Short name T88
Test name
Test status
Simulation time 186241949423 ps
CPU time 1348.77 seconds
Started Aug 11 07:03:55 PM PDT 24
Finished Aug 11 07:26:24 PM PDT 24
Peak memory 746244 kb
Host smart-7970379a-ed83-481d-9e50-2b58fb16d639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230779217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.4230779217
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1474245786
Short name T517
Test name
Test status
Simulation time 5041894308 ps
CPU time 32.57 seconds
Started Aug 11 07:03:51 PM PDT 24
Finished Aug 11 07:04:24 PM PDT 24
Peak memory 199928 kb
Host smart-33576d22-0254-4c15-b62f-3a2ad8e365c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474245786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1474245786
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1608629324
Short name T178
Test name
Test status
Simulation time 12374476 ps
CPU time 0.59 seconds
Started Aug 11 07:03:59 PM PDT 24
Finished Aug 11 07:04:00 PM PDT 24
Peak memory 196588 kb
Host smart-71671fa5-3468-4e6e-a31b-f28530d424d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608629324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1608629324
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1208704303
Short name T286
Test name
Test status
Simulation time 1636143373 ps
CPU time 47.65 seconds
Started Aug 11 07:03:58 PM PDT 24
Finished Aug 11 07:04:46 PM PDT 24
Peak memory 199808 kb
Host smart-cf1519fd-2e5f-4bb0-9c4b-be598f331cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208704303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1208704303
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1492851618
Short name T529
Test name
Test status
Simulation time 820912315 ps
CPU time 44.62 seconds
Started Aug 11 07:04:00 PM PDT 24
Finished Aug 11 07:04:45 PM PDT 24
Peak memory 199888 kb
Host smart-b4a3484c-4f7f-49ee-afe3-e46c0d55512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492851618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1492851618
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1635529959
Short name T146
Test name
Test status
Simulation time 12207568543 ps
CPU time 459.04 seconds
Started Aug 11 07:04:02 PM PDT 24
Finished Aug 11 07:11:41 PM PDT 24
Peak memory 637408 kb
Host smart-8aea6dd7-fa94-448d-b3a8-b6d85c25f04c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635529959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1635529959
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2378579594
Short name T441
Test name
Test status
Simulation time 2938813914 ps
CPU time 81.81 seconds
Started Aug 11 07:04:01 PM PDT 24
Finished Aug 11 07:05:23 PM PDT 24
Peak memory 199916 kb
Host smart-8010b61f-bd4e-4f82-94ef-afc207240de0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378579594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2378579594
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1024831139
Short name T334
Test name
Test status
Simulation time 11758772878 ps
CPU time 205.72 seconds
Started Aug 11 07:03:59 PM PDT 24
Finished Aug 11 07:07:25 PM PDT 24
Peak memory 199908 kb
Host smart-a5664590-eac1-4d8d-a127-ae316e6b95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024831139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1024831139
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3338244711
Short name T137
Test name
Test status
Simulation time 485259922 ps
CPU time 10.65 seconds
Started Aug 11 07:03:55 PM PDT 24
Finished Aug 11 07:04:05 PM PDT 24
Peak memory 199772 kb
Host smart-09e5ee8a-39c1-438a-adb8-3adf760148f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338244711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3338244711
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.602942177
Short name T503
Test name
Test status
Simulation time 71637432752 ps
CPU time 1259.87 seconds
Started Aug 11 07:03:59 PM PDT 24
Finished Aug 11 07:24:59 PM PDT 24
Peak memory 693360 kb
Host smart-32864f55-f8e5-4ba6-be03-7ebc735f826a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602942177 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.602942177
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2434432306
Short name T495
Test name
Test status
Simulation time 47416286817 ps
CPU time 106.22 seconds
Started Aug 11 07:03:59 PM PDT 24
Finished Aug 11 07:05:45 PM PDT 24
Peak memory 199980 kb
Host smart-f7094fe9-b43d-41f0-aae5-8db7b2172b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434432306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2434432306
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2567710366
Short name T409
Test name
Test status
Simulation time 23118091 ps
CPU time 0.59 seconds
Started Aug 11 07:04:00 PM PDT 24
Finished Aug 11 07:04:00 PM PDT 24
Peak memory 195920 kb
Host smart-33988b43-28fe-4372-95b7-4bb45299056a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567710366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2567710366
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2912432593
Short name T201
Test name
Test status
Simulation time 8724050839 ps
CPU time 99.24 seconds
Started Aug 11 07:04:01 PM PDT 24
Finished Aug 11 07:05:40 PM PDT 24
Peak memory 199840 kb
Host smart-3d6e9f91-ec6f-415e-806e-2a7dd86aa9a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912432593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2912432593
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.954863900
Short name T479
Test name
Test status
Simulation time 451840936 ps
CPU time 25.79 seconds
Started Aug 11 07:04:00 PM PDT 24
Finished Aug 11 07:04:26 PM PDT 24
Peak memory 199860 kb
Host smart-bb5bc5da-18bd-49a8-8de0-1aa47a1432db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954863900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.954863900
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.108707876
Short name T326
Test name
Test status
Simulation time 7518848708 ps
CPU time 1584.69 seconds
Started Aug 11 07:04:00 PM PDT 24
Finished Aug 11 07:30:25 PM PDT 24
Peak memory 767312 kb
Host smart-7498cee9-571e-40e4-90d5-b83355114e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108707876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.108707876
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1594769380
Short name T309
Test name
Test status
Simulation time 8853591487 ps
CPU time 55.56 seconds
Started Aug 11 07:04:00 PM PDT 24
Finished Aug 11 07:04:56 PM PDT 24
Peak memory 199872 kb
Host smart-81303a7f-fbca-4a9c-9838-e63e12d28913
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594769380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1594769380
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3684797744
Short name T172
Test name
Test status
Simulation time 16658918486 ps
CPU time 156.7 seconds
Started Aug 11 07:04:00 PM PDT 24
Finished Aug 11 07:06:36 PM PDT 24
Peak memory 200080 kb
Host smart-d75b77e9-7cc0-40ce-aa6f-f77b04bf66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684797744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3684797744
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2895313307
Short name T307
Test name
Test status
Simulation time 1368424227 ps
CPU time 15.8 seconds
Started Aug 11 07:04:02 PM PDT 24
Finished Aug 11 07:04:18 PM PDT 24
Peak memory 199824 kb
Host smart-82f14433-4830-4356-9fcb-e3ef62a04b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895313307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2895313307
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3121716068
Short name T23
Test name
Test status
Simulation time 71677196942 ps
CPU time 1255.19 seconds
Started Aug 11 07:03:59 PM PDT 24
Finished Aug 11 07:24:54 PM PDT 24
Peak memory 667064 kb
Host smart-5d8306dd-63c6-4113-87c8-ffb442733cbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121716068 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3121716068
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2865508569
Short name T332
Test name
Test status
Simulation time 542109185 ps
CPU time 8.18 seconds
Started Aug 11 07:04:01 PM PDT 24
Finished Aug 11 07:04:09 PM PDT 24
Peak memory 199820 kb
Host smart-c86eb156-b9ba-47b8-a047-d95bcba2eaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865508569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2865508569
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3261561565
Short name T457
Test name
Test status
Simulation time 15792653 ps
CPU time 0.61 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:04:07 PM PDT 24
Peak memory 195952 kb
Host smart-bfd653d2-89a6-44e6-8401-c5fc2575604e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261561565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3261561565
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3987535768
Short name T502
Test name
Test status
Simulation time 3441777826 ps
CPU time 36.43 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:04:43 PM PDT 24
Peak memory 199952 kb
Host smart-21bbdce0-9de9-4bc6-b2d3-811cb8f33b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987535768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3987535768
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2877988638
Short name T425
Test name
Test status
Simulation time 11435184666 ps
CPU time 39.74 seconds
Started Aug 11 07:04:09 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 199864 kb
Host smart-4df1ce79-cc04-466e-bb37-2837dd51e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877988638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2877988638
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3235708381
Short name T481
Test name
Test status
Simulation time 3730211597 ps
CPU time 316.94 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:09:24 PM PDT 24
Peak memory 481444 kb
Host smart-e0fd6623-d981-41ae-bb89-6add57b0f0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235708381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3235708381
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1364759058
Short name T231
Test name
Test status
Simulation time 32516243998 ps
CPU time 190.18 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:07:17 PM PDT 24
Peak memory 199952 kb
Host smart-7813e7a5-5649-4e38-9e74-d2f90adfae24
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364759058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1364759058
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3613204464
Short name T75
Test name
Test status
Simulation time 3599153759 ps
CPU time 213.68 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:07:41 PM PDT 24
Peak memory 216292 kb
Host smart-f1b6b1cd-5a86-4279-b9eb-97741864ff70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613204464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3613204464
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3963854528
Short name T446
Test name
Test status
Simulation time 5294112783 ps
CPU time 15.81 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:04:22 PM PDT 24
Peak memory 199884 kb
Host smart-3c852eb6-9111-4422-bb59-75419cd5db0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963854528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3963854528
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.39926664
Short name T518
Test name
Test status
Simulation time 54486998623 ps
CPU time 607.39 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:14:13 PM PDT 24
Peak memory 199972 kb
Host smart-9b10e68b-f6a3-46d4-a625-e0e35f502c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39926664 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.39926664
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2141887158
Short name T74
Test name
Test status
Simulation time 6838237260 ps
CPU time 44.91 seconds
Started Aug 11 07:04:05 PM PDT 24
Finished Aug 11 07:04:50 PM PDT 24
Peak memory 199920 kb
Host smart-beed4e67-e40b-465e-a374-365eed722ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141887158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2141887158
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2026789223
Short name T155
Test name
Test status
Simulation time 76912707 ps
CPU time 0.57 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:04:06 PM PDT 24
Peak memory 196580 kb
Host smart-7a3550bf-5015-4bcd-9685-977775256221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026789223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2026789223
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.202381547
Short name T490
Test name
Test status
Simulation time 1604263583 ps
CPU time 95.11 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:05:41 PM PDT 24
Peak memory 199860 kb
Host smart-c7b77ac9-9426-49a3-bff4-f41e5afc228e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202381547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.202381547
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1119287526
Short name T372
Test name
Test status
Simulation time 933398181 ps
CPU time 8.63 seconds
Started Aug 11 07:04:12 PM PDT 24
Finished Aug 11 07:04:20 PM PDT 24
Peak memory 199920 kb
Host smart-d21ea2c4-f151-4b50-9440-19936df64c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119287526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1119287526
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1335651892
Short name T350
Test name
Test status
Simulation time 2735679902 ps
CPU time 505.03 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:12:32 PM PDT 24
Peak memory 666624 kb
Host smart-b322a2d4-e8b4-4085-a8f3-73178f740037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335651892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1335651892
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.153752766
Short name T428
Test name
Test status
Simulation time 8495265056 ps
CPU time 144.21 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:06:30 PM PDT 24
Peak memory 199804 kb
Host smart-b121a2d2-2985-412d-b487-e5dd45beb499
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153752766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.153752766
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.662142767
Short name T289
Test name
Test status
Simulation time 18033952203 ps
CPU time 143.08 seconds
Started Aug 11 07:04:05 PM PDT 24
Finished Aug 11 07:06:28 PM PDT 24
Peak memory 199940 kb
Host smart-b9a6a754-a456-461f-87d7-6e31e6a52479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662142767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.662142767
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3001551013
Short name T324
Test name
Test status
Simulation time 688895267 ps
CPU time 3.57 seconds
Started Aug 11 07:04:09 PM PDT 24
Finished Aug 11 07:04:13 PM PDT 24
Peak memory 199808 kb
Host smart-04c7d4fa-f73e-4bc6-81c9-5a781d95ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001551013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3001551013
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3599436203
Short name T312
Test name
Test status
Simulation time 15896092306 ps
CPU time 276.34 seconds
Started Aug 11 07:04:09 PM PDT 24
Finished Aug 11 07:08:46 PM PDT 24
Peak memory 199932 kb
Host smart-22ef704f-2c2f-4eb4-9bdd-a3f95d6acdf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599436203 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3599436203
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3190979828
Short name T239
Test name
Test status
Simulation time 2369199456 ps
CPU time 8.73 seconds
Started Aug 11 07:04:05 PM PDT 24
Finished Aug 11 07:04:13 PM PDT 24
Peak memory 199848 kb
Host smart-b9aac06c-f26c-4411-b627-8b56a0bcc215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190979828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3190979828
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2569737119
Short name T227
Test name
Test status
Simulation time 32930394 ps
CPU time 0.58 seconds
Started Aug 11 07:04:12 PM PDT 24
Finished Aug 11 07:04:12 PM PDT 24
Peak memory 195556 kb
Host smart-570b3f01-8f56-491e-abb7-64794a5c4767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569737119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2569737119
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3878369282
Short name T516
Test name
Test status
Simulation time 901694450 ps
CPU time 48.6 seconds
Started Aug 11 07:04:06 PM PDT 24
Finished Aug 11 07:04:55 PM PDT 24
Peak memory 199800 kb
Host smart-52280436-044b-4291-8a14-5d38c7b62f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878369282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3878369282
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2516096438
Short name T510
Test name
Test status
Simulation time 2774442987 ps
CPU time 36.85 seconds
Started Aug 11 07:04:05 PM PDT 24
Finished Aug 11 07:04:42 PM PDT 24
Peak memory 199912 kb
Host smart-5e918fc9-27d4-44e7-82b7-bb9644e76ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516096438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2516096438
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.585949247
Short name T508
Test name
Test status
Simulation time 9013637299 ps
CPU time 778 seconds
Started Aug 11 07:04:05 PM PDT 24
Finished Aug 11 07:17:03 PM PDT 24
Peak memory 639196 kb
Host smart-ec0d5bc2-7196-4da8-98c4-ded576f34bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585949247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.585949247
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.744868264
Short name T488
Test name
Test status
Simulation time 9061886035 ps
CPU time 155.27 seconds
Started Aug 11 07:04:13 PM PDT 24
Finished Aug 11 07:06:49 PM PDT 24
Peak memory 199964 kb
Host smart-1dc03a61-58db-45a6-ac15-111c7165e69b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744868264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.744868264
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4095881238
Short name T387
Test name
Test status
Simulation time 7968125568 ps
CPU time 147.86 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:06:35 PM PDT 24
Peak memory 208144 kb
Host smart-72c2bf7b-2d5a-447a-ba78-344ac71ae39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095881238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4095881238
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1581947967
Short name T133
Test name
Test status
Simulation time 171439488 ps
CPU time 6.45 seconds
Started Aug 11 07:04:07 PM PDT 24
Finished Aug 11 07:04:13 PM PDT 24
Peak memory 199828 kb
Host smart-12b7672b-7625-417f-bc8c-b8ed75de4f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581947967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1581947967
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3705846051
Short name T358
Test name
Test status
Simulation time 29641276932 ps
CPU time 1075.42 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:22:07 PM PDT 24
Peak memory 675220 kb
Host smart-2cb41499-a6db-4756-8411-3e63d0a86f1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705846051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3705846051
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.933524285
Short name T213
Test name
Test status
Simulation time 2037615591 ps
CPU time 27.57 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:04:38 PM PDT 24
Peak memory 199844 kb
Host smart-843bfdf5-8713-4aad-a18c-0a6578973994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933524285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.933524285
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2986514570
Short name T450
Test name
Test status
Simulation time 13499064 ps
CPU time 0.58 seconds
Started Aug 11 07:04:12 PM PDT 24
Finished Aug 11 07:04:12 PM PDT 24
Peak memory 195912 kb
Host smart-13f1990d-274e-4714-b28f-12a9db4861b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986514570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2986514570
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.930971202
Short name T316
Test name
Test status
Simulation time 288113262 ps
CPU time 4.37 seconds
Started Aug 11 07:04:13 PM PDT 24
Finished Aug 11 07:04:18 PM PDT 24
Peak memory 199832 kb
Host smart-0af3544e-16f1-4fd3-b164-3619141abe48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930971202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.930971202
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3608671974
Short name T345
Test name
Test status
Simulation time 4922432016 ps
CPU time 38.52 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:04:49 PM PDT 24
Peak memory 199956 kb
Host smart-493468d0-7056-4bbf-9762-7db31dcfdfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608671974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3608671974
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1794734775
Short name T218
Test name
Test status
Simulation time 63082578747 ps
CPU time 1307.12 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:25:59 PM PDT 24
Peak memory 786000 kb
Host smart-007c9c55-cd08-4040-b7de-0b03b2f4fc28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794734775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1794734775
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3886317368
Short name T191
Test name
Test status
Simulation time 209450425508 ps
CPU time 274.3 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:08:45 PM PDT 24
Peak memory 199908 kb
Host smart-b246ae14-1083-41a5-8f80-5bf7b932a425
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886317368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3886317368
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.569640183
Short name T183
Test name
Test status
Simulation time 929732941 ps
CPU time 53.42 seconds
Started Aug 11 07:04:10 PM PDT 24
Finished Aug 11 07:05:04 PM PDT 24
Peak memory 199880 kb
Host smart-67cc141b-749d-4e7f-8a31-36c2fa246066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569640183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.569640183
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1839666865
Short name T373
Test name
Test status
Simulation time 365292942 ps
CPU time 1.86 seconds
Started Aug 11 07:04:12 PM PDT 24
Finished Aug 11 07:04:14 PM PDT 24
Peak memory 199860 kb
Host smart-f9ed4648-4dfe-4ae6-9043-4c48ba3cae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839666865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1839666865
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1069766107
Short name T139
Test name
Test status
Simulation time 17411784165 ps
CPU time 846.51 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:18:18 PM PDT 24
Peak memory 199960 kb
Host smart-eaffee85-b577-4350-8827-eb731b1b74e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069766107 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1069766107
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3498628535
Short name T31
Test name
Test status
Simulation time 365230463 ps
CPU time 18.37 seconds
Started Aug 11 07:04:10 PM PDT 24
Finished Aug 11 07:04:28 PM PDT 24
Peak memory 199796 kb
Host smart-1b8ff72d-e585-4267-92ab-db7100299fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498628535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3498628535
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.570382432
Short name T55
Test name
Test status
Simulation time 15219155 ps
CPU time 0.61 seconds
Started Aug 11 07:04:20 PM PDT 24
Finished Aug 11 07:04:21 PM PDT 24
Peak memory 196572 kb
Host smart-1be15d46-6036-463e-b0bc-9a6a456b24e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570382432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.570382432
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.37780805
Short name T40
Test name
Test status
Simulation time 1120559242 ps
CPU time 11.38 seconds
Started Aug 11 07:04:09 PM PDT 24
Finished Aug 11 07:04:21 PM PDT 24
Peak memory 199840 kb
Host smart-2d7fbe43-c1c4-4fd3-b898-280a8ad02bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37780805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.37780805
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.908008825
Short name T27
Test name
Test status
Simulation time 3794072465 ps
CPU time 50.12 seconds
Started Aug 11 07:04:13 PM PDT 24
Finished Aug 11 07:05:03 PM PDT 24
Peak memory 199940 kb
Host smart-bf65f420-d1c8-41fc-ab75-81c049df29cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908008825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.908008825
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2255418402
Short name T76
Test name
Test status
Simulation time 18194591952 ps
CPU time 674.85 seconds
Started Aug 11 07:04:10 PM PDT 24
Finished Aug 11 07:15:25 PM PDT 24
Peak memory 730376 kb
Host smart-c2c62fc0-ba37-46df-be3c-7fa168a7a46e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255418402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2255418402
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.307209753
Short name T53
Test name
Test status
Simulation time 37321399901 ps
CPU time 152.78 seconds
Started Aug 11 07:04:12 PM PDT 24
Finished Aug 11 07:06:45 PM PDT 24
Peak memory 199932 kb
Host smart-c1681cbf-9bbf-44bf-96c1-c501ad15f1df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307209753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.307209753
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4279573558
Short name T208
Test name
Test status
Simulation time 6282672123 ps
CPU time 119.29 seconds
Started Aug 11 07:04:11 PM PDT 24
Finished Aug 11 07:06:10 PM PDT 24
Peak memory 200100 kb
Host smart-ae5a71d4-57d9-4c4a-a7ec-66249c8932e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279573558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4279573558
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1112965668
Short name T22
Test name
Test status
Simulation time 433036479 ps
CPU time 1.72 seconds
Started Aug 11 07:04:10 PM PDT 24
Finished Aug 11 07:04:11 PM PDT 24
Peak memory 199880 kb
Host smart-bc8765af-abb9-4a82-b82c-be036f0d938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112965668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1112965668
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.4116680168
Short name T368
Test name
Test status
Simulation time 1209785298 ps
CPU time 58.96 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:05:16 PM PDT 24
Peak memory 199772 kb
Host smart-f6b10077-167c-4452-8877-0e0017834cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116680168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.4116680168
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.544261340
Short name T187
Test name
Test status
Simulation time 19073018 ps
CPU time 0.53 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:04:18 PM PDT 24
Peak memory 194760 kb
Host smart-7bb51ab4-276c-4c35-b012-143c5e3a744d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544261340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.544261340
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2715127927
Short name T223
Test name
Test status
Simulation time 3254441715 ps
CPU time 45.83 seconds
Started Aug 11 07:04:18 PM PDT 24
Finished Aug 11 07:05:04 PM PDT 24
Peak memory 199888 kb
Host smart-30c1394b-bab3-4400-a7b3-67adf8b54e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715127927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2715127927
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2326193929
Short name T347
Test name
Test status
Simulation time 8983859623 ps
CPU time 16.7 seconds
Started Aug 11 07:04:16 PM PDT 24
Finished Aug 11 07:04:33 PM PDT 24
Peak memory 199848 kb
Host smart-870245f1-3c36-4e20-aa1a-60790d383342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326193929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2326193929
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1190085337
Short name T379
Test name
Test status
Simulation time 1760444892 ps
CPU time 250.64 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:08:28 PM PDT 24
Peak memory 627772 kb
Host smart-69466ba5-8911-4e54-9a64-daee66d8eaa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190085337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1190085337
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3047834000
Short name T37
Test name
Test status
Simulation time 3659613664 ps
CPU time 96.95 seconds
Started Aug 11 07:04:16 PM PDT 24
Finished Aug 11 07:05:53 PM PDT 24
Peak memory 199952 kb
Host smart-4f289ad8-5eb7-4474-9eaa-d03e9bf09354
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047834000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3047834000
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2486482063
Short name T35
Test name
Test status
Simulation time 5001282401 ps
CPU time 79.04 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:05:36 PM PDT 24
Peak memory 216136 kb
Host smart-4ae61e98-085c-409f-86fb-2067076bd0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486482063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2486482063
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1700789774
Short name T416
Test name
Test status
Simulation time 340101519 ps
CPU time 6.08 seconds
Started Aug 11 07:04:14 PM PDT 24
Finished Aug 11 07:04:21 PM PDT 24
Peak memory 199908 kb
Host smart-4aeef8c9-2fdf-449c-ac94-9af299800b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700789774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1700789774
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2774209366
Short name T476
Test name
Test status
Simulation time 251624410596 ps
CPU time 1589.81 seconds
Started Aug 11 07:04:18 PM PDT 24
Finished Aug 11 07:30:48 PM PDT 24
Peak memory 717792 kb
Host smart-f9f4011c-61bf-473b-98a5-70f958f74ced
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774209366 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2774209366
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3582514530
Short name T232
Test name
Test status
Simulation time 5365036798 ps
CPU time 65.41 seconds
Started Aug 11 07:04:17 PM PDT 24
Finished Aug 11 07:05:22 PM PDT 24
Peak memory 199912 kb
Host smart-afe6de55-3a43-487c-8986-7a1ac16e613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582514530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3582514530
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2462125164
Short name T413
Test name
Test status
Simulation time 12209498 ps
CPU time 0.59 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:02:48 PM PDT 24
Peak memory 194880 kb
Host smart-12cf1f0a-1784-4b48-8c11-133fbe1e1796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462125164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2462125164
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3330404249
Short name T244
Test name
Test status
Simulation time 1479929899 ps
CPU time 20.46 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:03:08 PM PDT 24
Peak memory 199804 kb
Host smart-0e0b0e9e-6f25-42c4-be5f-bd29f299f61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330404249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3330404249
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3491441781
Short name T24
Test name
Test status
Simulation time 7347483662 ps
CPU time 64.17 seconds
Started Aug 11 07:02:41 PM PDT 24
Finished Aug 11 07:03:45 PM PDT 24
Peak memory 199936 kb
Host smart-6629ddf7-61e8-4564-8433-3b214c6ca713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491441781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3491441781
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.758272049
Short name T247
Test name
Test status
Simulation time 5209585682 ps
CPU time 203.65 seconds
Started Aug 11 07:02:37 PM PDT 24
Finished Aug 11 07:06:01 PM PDT 24
Peak memory 478152 kb
Host smart-90eb76dd-8e96-4b1b-b9f5-1eef6aca63e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758272049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.758272049
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2908028954
Short name T300
Test name
Test status
Simulation time 10692647516 ps
CPU time 149.16 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:05:07 PM PDT 24
Peak memory 199900 kb
Host smart-bc36179f-0b4e-4a25-ad17-44bdb4866c13
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908028954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2908028954
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.480824791
Short name T403
Test name
Test status
Simulation time 7082324742 ps
CPU time 102.06 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 199876 kb
Host smart-b216a90f-f263-4b33-a518-96873036d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480824791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.480824791
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3013826106
Short name T195
Test name
Test status
Simulation time 2420551195 ps
CPU time 5.24 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:02:44 PM PDT 24
Peak memory 199516 kb
Host smart-0988f236-f2be-402a-994b-817c62c90310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013826106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3013826106
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.584605619
Short name T468
Test name
Test status
Simulation time 118746585878 ps
CPU time 3176.38 seconds
Started Aug 11 07:02:37 PM PDT 24
Finished Aug 11 07:55:34 PM PDT 24
Peak memory 798352 kb
Host smart-2bde9ca4-9479-4be0-8581-c2cb9610d1c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584605619 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.584605619
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3200108595
Short name T14
Test name
Test status
Simulation time 56912978764 ps
CPU time 247.72 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:06:47 PM PDT 24
Peak memory 215948 kb
Host smart-aec43b27-746f-4320-a741-c6e3af369ed4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200108595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3200108595
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3260816245
Short name T394
Test name
Test status
Simulation time 3686211470 ps
CPU time 95.84 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:04:15 PM PDT 24
Peak memory 199896 kb
Host smart-f9b0de7a-80fc-4a9e-9120-f085fd478e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260816245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3260816245
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.399209097
Short name T215
Test name
Test status
Simulation time 112205708 ps
CPU time 0.57 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:02:40 PM PDT 24
Peak memory 194848 kb
Host smart-ffd6a82e-3d4b-4d24-aa6d-8145c5428da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399209097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.399209097
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3110637812
Short name T341
Test name
Test status
Simulation time 438023907 ps
CPU time 24.64 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:03:03 PM PDT 24
Peak memory 199876 kb
Host smart-702293ed-48cd-4001-af36-006f0aa9ab51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110637812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3110637812
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2717873413
Short name T399
Test name
Test status
Simulation time 4439957376 ps
CPU time 57.12 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:03:36 PM PDT 24
Peak memory 199884 kb
Host smart-3d6a6716-7f3b-4e6b-9ef4-47a715ae749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717873413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2717873413
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.435264304
Short name T304
Test name
Test status
Simulation time 3425596781 ps
CPU time 377.47 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:08:57 PM PDT 24
Peak memory 661796 kb
Host smart-376b2aaf-7959-4009-ad57-e564c8bf554e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435264304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.435264304
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2524755374
Short name T302
Test name
Test status
Simulation time 41852758870 ps
CPU time 202 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:06:01 PM PDT 24
Peak memory 199868 kb
Host smart-6dd7082b-db0e-44e3-8848-aa64c229476d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524755374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2524755374
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.97163536
Short name T71
Test name
Test status
Simulation time 11203838867 ps
CPU time 75.35 seconds
Started Aug 11 07:02:38 PM PDT 24
Finished Aug 11 07:03:53 PM PDT 24
Peak memory 208188 kb
Host smart-998e6b88-d1c1-4167-be39-1383cdeefba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97163536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.97163536
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3509388926
Short name T521
Test name
Test status
Simulation time 121048258 ps
CPU time 1.65 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:02:40 PM PDT 24
Peak memory 199736 kb
Host smart-17168b71-3179-48d5-9872-3d26a18e062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509388926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3509388926
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3826955225
Short name T522
Test name
Test status
Simulation time 429471692986 ps
CPU time 949.01 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:18:29 PM PDT 24
Peak memory 638592 kb
Host smart-0fcdb0ed-eb76-4e13-a93f-3aa0f7d6aff8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826955225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3826955225
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.628717928
Short name T65
Test name
Test status
Simulation time 95964275219 ps
CPU time 1962.37 seconds
Started Aug 11 07:02:42 PM PDT 24
Finished Aug 11 07:35:25 PM PDT 24
Peak memory 230628 kb
Host smart-1932436c-498b-4100-b908-85e4df46d34b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628717928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.628717928
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1446872578
Short name T18
Test name
Test status
Simulation time 5532400214 ps
CPU time 69.59 seconds
Started Aug 11 07:02:41 PM PDT 24
Finished Aug 11 07:03:50 PM PDT 24
Peak memory 199980 kb
Host smart-c4733001-4431-4812-a641-410b211fb423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446872578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1446872578
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.362507840
Short name T346
Test name
Test status
Simulation time 13469244 ps
CPU time 0.58 seconds
Started Aug 11 07:02:41 PM PDT 24
Finished Aug 11 07:02:42 PM PDT 24
Peak memory 195564 kb
Host smart-b3f5a8e4-eadb-4913-86d3-7a7356294a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362507840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.362507840
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3318712639
Short name T216
Test name
Test status
Simulation time 15345238349 ps
CPU time 58.83 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:03:39 PM PDT 24
Peak memory 199832 kb
Host smart-4a1842ce-50a9-46e1-9891-0a7318b90e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318712639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3318712639
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1944178244
Short name T390
Test name
Test status
Simulation time 8301957313 ps
CPU time 27.17 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:03:07 PM PDT 24
Peak memory 199836 kb
Host smart-752e7e56-17f8-48df-8bfe-1d697cd570ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944178244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1944178244
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.846990919
Short name T6
Test name
Test status
Simulation time 21729174005 ps
CPU time 915.64 seconds
Started Aug 11 07:02:42 PM PDT 24
Finished Aug 11 07:17:58 PM PDT 24
Peak memory 617900 kb
Host smart-2f3fc6dd-f55f-4df8-8c01-878001d1be61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846990919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.846990919
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.680584127
Short name T30
Test name
Test status
Simulation time 136266517792 ps
CPU time 126.27 seconds
Started Aug 11 07:02:42 PM PDT 24
Finished Aug 11 07:04:48 PM PDT 24
Peak memory 199844 kb
Host smart-accd2a70-57c5-4277-8997-73be61efd78d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680584127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.680584127
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3752599447
Short name T463
Test name
Test status
Simulation time 3449123269 ps
CPU time 96.93 seconds
Started Aug 11 07:02:39 PM PDT 24
Finished Aug 11 07:04:16 PM PDT 24
Peak memory 199908 kb
Host smart-7531c90d-aafd-4515-acd8-a3375bf28d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752599447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3752599447
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3313645525
Short name T432
Test name
Test status
Simulation time 896915888 ps
CPU time 15.08 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:02:56 PM PDT 24
Peak memory 199836 kb
Host smart-ef5064b9-e819-4ef0-835a-c087665e0642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313645525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3313645525
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2882396299
Short name T442
Test name
Test status
Simulation time 85610923834 ps
CPU time 1777.15 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:32:18 PM PDT 24
Peak memory 720696 kb
Host smart-352d390d-d440-428b-a0ac-f7bb2349fd6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882396299 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2882396299
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.551380001
Short name T401
Test name
Test status
Simulation time 776721052 ps
CPU time 3.08 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:02:48 PM PDT 24
Peak memory 199668 kb
Host smart-caf14956-45d7-49da-89e7-a62a7d052a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551380001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.551380001
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2271066717
Short name T242
Test name
Test status
Simulation time 34043632 ps
CPU time 0.58 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:02:47 PM PDT 24
Peak memory 195712 kb
Host smart-a5a916a8-fc3f-4ea7-884c-1de952b15798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271066717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2271066717
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3325860197
Short name T528
Test name
Test status
Simulation time 1336705215 ps
CPU time 76.83 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:04:02 PM PDT 24
Peak memory 199808 kb
Host smart-c3a64638-337b-4303-9f20-01303ccd0436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325860197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3325860197
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1274969080
Short name T480
Test name
Test status
Simulation time 3525997709 ps
CPU time 11.09 seconds
Started Aug 11 07:02:49 PM PDT 24
Finished Aug 11 07:03:00 PM PDT 24
Peak memory 199868 kb
Host smart-c475255e-3c45-465a-873f-94300d850a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274969080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1274969080
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3735998858
Short name T473
Test name
Test status
Simulation time 10058234284 ps
CPU time 920.24 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:18:07 PM PDT 24
Peak memory 722568 kb
Host smart-c6694efa-8e85-4ad0-b537-201e779feb21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735998858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3735998858
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4035289779
Short name T524
Test name
Test status
Simulation time 3342197724 ps
CPU time 43.97 seconds
Started Aug 11 07:02:49 PM PDT 24
Finished Aug 11 07:03:34 PM PDT 24
Peak memory 199904 kb
Host smart-ebdd1f1a-dcbb-4691-800b-3dadcd0aac10
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035289779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4035289779
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3058293881
Short name T171
Test name
Test status
Simulation time 2367977904 ps
CPU time 121.65 seconds
Started Aug 11 07:02:40 PM PDT 24
Finished Aug 11 07:04:41 PM PDT 24
Peak memory 199848 kb
Host smart-687a1225-9faf-4af0-abb4-294fd913d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058293881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3058293881
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.254084787
Short name T349
Test name
Test status
Simulation time 2227258927 ps
CPU time 13.16 seconds
Started Aug 11 07:02:41 PM PDT 24
Finished Aug 11 07:02:54 PM PDT 24
Peak memory 199968 kb
Host smart-d0fc1329-c00d-4e7c-b74b-2ae1e3677bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254084787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.254084787
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.375701674
Short name T189
Test name
Test status
Simulation time 2742119388 ps
CPU time 30.84 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:03:23 PM PDT 24
Peak memory 199872 kb
Host smart-fc757ab5-7302-410c-878e-1c60153c845b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375701674 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.375701674
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.603844326
Short name T25
Test name
Test status
Simulation time 104769350386 ps
CPU time 580.52 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:12:25 PM PDT 24
Peak memory 582816 kb
Host smart-e332c97d-c33f-4807-85e9-d0a49d165276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603844326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.603844326
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.103550159
Short name T257
Test name
Test status
Simulation time 5016053547 ps
CPU time 115.22 seconds
Started Aug 11 07:02:44 PM PDT 24
Finished Aug 11 07:04:39 PM PDT 24
Peak memory 199932 kb
Host smart-2f0b86cf-9146-4cec-bb6c-638247b99c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103550159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.103550159
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4078232064
Short name T153
Test name
Test status
Simulation time 14310887 ps
CPU time 0.62 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:02:47 PM PDT 24
Peak memory 194912 kb
Host smart-56005427-e9cf-41d6-bba3-91df52b447cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078232064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4078232064
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1498838651
Short name T50
Test name
Test status
Simulation time 1931481730 ps
CPU time 55.96 seconds
Started Aug 11 07:02:44 PM PDT 24
Finished Aug 11 07:03:40 PM PDT 24
Peak memory 199892 kb
Host smart-cb609329-5c90-4836-aab2-bd29b15838a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498838651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1498838651
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3646676984
Short name T474
Test name
Test status
Simulation time 1196264464 ps
CPU time 32.79 seconds
Started Aug 11 07:02:52 PM PDT 24
Finished Aug 11 07:03:25 PM PDT 24
Peak memory 199820 kb
Host smart-599af9e2-cc8e-4528-963d-0c4eec2c1de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646676984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3646676984
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2068785501
Short name T291
Test name
Test status
Simulation time 45968246477 ps
CPU time 1114.11 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:21:20 PM PDT 24
Peak memory 770992 kb
Host smart-68295cc9-4a12-401b-905e-94c914663175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068785501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2068785501
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1900222240
Short name T363
Test name
Test status
Simulation time 13250884871 ps
CPU time 49.23 seconds
Started Aug 11 07:02:46 PM PDT 24
Finished Aug 11 07:03:35 PM PDT 24
Peak memory 199852 kb
Host smart-8c6297a6-1e7e-40b5-afe7-123ad3a6a777
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900222240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1900222240
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3781832199
Short name T382
Test name
Test status
Simulation time 33904612161 ps
CPU time 102.2 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:04:29 PM PDT 24
Peak memory 199964 kb
Host smart-bcd8a045-d8eb-4fee-aa37-dbc9c2d6df62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781832199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3781832199
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2327302113
Short name T344
Test name
Test status
Simulation time 156435271 ps
CPU time 3.69 seconds
Started Aug 11 07:02:49 PM PDT 24
Finished Aug 11 07:02:52 PM PDT 24
Peak memory 199844 kb
Host smart-6559105a-6478-4772-8675-f7aa7ce98404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327302113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2327302113
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.745932889
Short name T78
Test name
Test status
Simulation time 190760395581 ps
CPU time 813.8 seconds
Started Aug 11 07:02:47 PM PDT 24
Finished Aug 11 07:16:21 PM PDT 24
Peak memory 467912 kb
Host smart-d0582563-7b93-4485-81ae-2b842340142f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745932889 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.745932889
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.148442919
Short name T10
Test name
Test status
Simulation time 584864206553 ps
CPU time 1650.96 seconds
Started Aug 11 07:02:45 PM PDT 24
Finished Aug 11 07:30:17 PM PDT 24
Peak memory 642544 kb
Host smart-1d459a22-3ca2-4a27-90c0-9948f2e64171
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148442919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.148442919
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.697378373
Short name T424
Test name
Test status
Simulation time 5687071147 ps
CPU time 59.61 seconds
Started Aug 11 07:02:44 PM PDT 24
Finished Aug 11 07:03:43 PM PDT 24
Peak memory 199828 kb
Host smart-da67aaae-b642-4d6e-b4df-4caf8ff8590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697378373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.697378373
Directory /workspace/9.hmac_wipe_secret/latest
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