Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16800454	1			T3	67297		T6	2767		T4	490
all_values[1]	16800454	1			T3	67297		T6	2767		T4	490
all_values[2]	16800454	1			T3	67297		T6	2767		T4	490

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263124

1

T3

3

T4

147

T7

382

auto[1]

50138238

1

T3

201888

T6

8301

T4

1323

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43113786

1

T3

163845

T6

7380

T4

1322

auto[1]

7287576

1

T3

38046

T6

921

T4

148

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80970	1			T7	382		T11	19		T24	1338
all_values[0]	auto[0]	auto[1]	307	1			T11	2		T24	6		T44	8
all_values[0]	auto[1]	auto[0]	16700812	1			T3	67279		T6	2763		T4	482
all_values[0]	auto[1]	auto[1]	18365	1			T3	18		T6	4		T4	8
all_values[1]	auto[0]	auto[0]	88581	1			T11	21		T24	4		T22	6139
all_values[1]	auto[0]	auto[1]	185	1			T24	3		T44	7		T45	3
all_values[1]	auto[1]	auto[0]	16711442	1			T3	67297		T6	2767		T4	490
all_values[1]	auto[1]	auto[1]	246	1			T24	3		T44	1		T45	1
all_values[2]	auto[0]	auto[0]	51140	1			T3	1		T4	7		T11	21
all_values[2]	auto[0]	auto[1]	41941	1			T3	2		T4	140		T10	17
all_values[2]	auto[1]	auto[0]	9480841	1			T3	29268		T6	1850		T4	343
all_values[2]	auto[1]	auto[1]	7226532	1			T3	38026		T6	917		T7	9366