Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102185

1

T6

6

T4

228

T7

44

auto[1]

112926

1

T3

62

T6

2

T4

144

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	82979	1			T3	19		T6	3		T4	125
len_1026_2046	4430	1			T4	2		T5	17		T10	16
len_514_1022	3409	1			T6	1		T4	2		T7	4
len_2_510	3016	1			T7	4		T5	62		T8	2
len_2056	190	1			T29	1		T24	3		T44	6
len_2048	255	1			T3	1		T10	1		T29	2
len_2040	224	1			T29	2		T24	10		T136	5
len_1032	142	1			T29	1		T44	2		T45	1
len_1024	1768	1			T3	2		T19	112		T8	1
len_1016	185	1			T29	6		T24	1		T44	4
len_520	155	1			T11	1		T29	5		T44	5
len_512	312	1			T4	2		T10	3		T29	1
len_504	162	1			T11	1		T24	9		T44	3
len_8	1036	1			T3	7		T47	1		T22	10
len_0	9293	1			T3	2		T4	55		T11	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

113

1

T3

2

T10

2

T42

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	40467	1			T6	2		T4	58		T7	18
auto[0]	len_1026_2046	1984	1			T5	15		T10	8		T29	2
auto[0]	len_514_1022	2066	1			T6	1		T7	4		T5	6
auto[0]	len_2_510	2076	1			T5	10		T10	4		T24	34
auto[0]	len_2056	118	1			T24	3		T44	3		T45	1
auto[0]	len_2048	146	1			T10	1		T29	2		T24	1
auto[0]	len_2040	106	1			T29	2		T24	2		T136	3
auto[0]	len_1032	71	1			T29	1		T45	1		T89	2
auto[0]	len_1024	238	1			T10	3		T29	1		T24	1
auto[0]	len_1016	91	1			T29	5		T24	1		T44	3
auto[0]	len_520	86	1			T11	1		T29	2		T44	5
auto[0]	len_512	196	1			T4	1		T10	1		T29	1
auto[0]	len_504	94	1			T11	1		T24	5		T136	3
auto[0]	len_8	31	1			T47	1		T12	1		T37	1
auto[0]	len_0	3323	1			T4	55		T8	2		T10	34
auto[1]	len_2050_plus	42512	1			T3	19		T6	1		T4	67
auto[1]	len_1026_2046	2446	1			T4	2		T5	2		T10	8
auto[1]	len_514_1022	1343	1			T4	2		T5	3		T8	2
auto[1]	len_2_510	940	1			T7	4		T5	52		T8	2
auto[1]	len_2056	72	1			T29	1		T44	3		T137	4
auto[1]	len_2048	109	1			T3	1		T44	2		T45	2
auto[1]	len_2040	118	1			T24	8		T136	2		T87	4
auto[1]	len_1032	71	1			T44	2		T138	2		T139	3
auto[1]	len_1024	1530	1			T3	2		T19	112		T8	1
auto[1]	len_1016	94	1			T29	1		T44	1		T87	1
auto[1]	len_520	69	1			T29	3		T89	1		T137	1
auto[1]	len_512	116	1			T4	1		T10	2		T24	2
auto[1]	len_504	68	1			T24	4		T44	3		T87	1
auto[1]	len_8	1005	1			T3	7		T22	10		T85	4
auto[1]	len_0	5970	1			T3	2		T11	1		T8	4

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

57

1

T10

2

T42

2

T87

2

auto[1]

len_upper

56

1

T3

2

T45

1

T85

2