Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4304568

1

T3

23069

T6

982

T4

444

auto[1]

2574809

1

T3

10359

T6

392

T4

361

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2547448

1

T3

10420

T6

474

T4

269

auto[1]

4331929

1

T3

23008

T6

900

T4

536

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3121764

1

T6

759

T4

536

T7

5566

auto[1]

3757613

1

T3

33428

T6

615

T4

269

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4242179

1

T3

19213

T6

522

T4

519

auto[1]

2637198

1

T3

14215

T6

852

T4

286

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6234175	1			T3	31289		T6	1325		T4	730
fifo_depth[1]	114387	1			T3	305		T6	24		T4	12
fifo_depth[2]	89186	1			T3	314		T6	21		T4	14
fifo_depth[3]	72625	1			T3	351		T6	4		T4	7
fifo_depth[4]	64817	1			T3	317		T4	33		T19	28
fifo_depth[5]	51611	1			T3	290		T4	1		T19	3
fifo_depth[6]	40439	1			T3	229		T4	4		T5	15
fifo_depth[7]	26712	1			T3	176		T4	3		T5	6

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645202

1

T3

2139

T6

49

T4

75

auto[1]

6234175

1

T3

31289

T6

1325

T4

730

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6873003

1

T3

33428

T6

1374

T4

805

auto[1]

6374

1

T25

108

T26

821

T27

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

21886

1

T4

26

T7

14

T8

410

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25352

1

T6

24

T7

15

T5

59

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

29131

1

T7

12

T5

21

T10

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31602

1

T7

25

T5

104

T8

94

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

160561

1

T6

25

T8

303

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32514

1

T7

23

T10

10

T24

23

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23064

1

T7

1

T8

397

T10

19

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26501

1

T7

10

T8

430

T10

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

32595

1

T3

15

T7

25

T5

53

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

32551

1

T3

436

T5

9

T8

62

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40486

1

T3

149

T8

8

T24

56

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

39715

1

T3

697

T7

1

T8

75

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44127

1

T3

643

T4

9

T7

27

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

40529

1

T4

40

T7

16

T10

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32450

1

T5

33

T8

431

T10

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32138

1

T3

199

T8

361

T10

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

147602

1

T6

14

T4

149

T7

976

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

154155

1

T6

436

T7

670

T5

562

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

150358

1

T7

571

T11

11

T5

80

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

156898

1

T4

94

T7

898

T5

2687

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1688498

1

T6

260

T7

486

T8

2908

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

159936

1

T7

1328

T11

1

T10

798

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

147558

1

T4

267

T7

19

T11

31

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

166148

1

T7

518

T5

13

T8

1790

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

400869

1

T3

4631

T7

1028

T5

73

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

396662

1

T3

2304

T7

438

T11

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

423683

1

T3

627

T7

785

T8

738

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

463903

1

T3

1561

T7

463

T5

153

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

487748

1

T3

8527

T6

223

T4

68

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

478983

1

T3

6513

T4

152

T7

1015

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

411563

1

T3

4621

T7

730

T5

151

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

399611

1

T3

2505

T6

392

T7

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

169250

1

T6

14

T4

175

T7

990

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

178918

1

T6

460

T7

685

T5

621

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

179161

1

T7

583

T11

11

T5

101

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

187313

1

T4

94

T7

923

T5

2791

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1848793

1

T6

285

T7

486

T8

3211

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

192080

1

T7

1351

T11

1

T10

808

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

170376

1

T4

267

T7

20

T11

31

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

192246

1

T7

528

T5

13

T8

2220

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

432741

1

T3

4646

T7

1053

T5

126

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

428984

1

T3

2740

T7

438

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

463724

1

T3

776

T7

785

T8

746

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

503365

1

T3

2258

T7

464

T5

153

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

531726

1

T3

9170

T6

223

T4

77

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

519300

1

T3

6513

T4

192

T7

1031

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

443721

1

T3

4621

T7

730

T5

184

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

431305

1

T3

2704

T6

392

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

238

1

T25

108

T27

1

T40

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

589

1

T92

85

T140

5

T141

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

328

1

T26

35

T27

1

T32

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1187

1

T26

616

T92

3

T40

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

266

1

T32

26

T40

155

T142

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

370

1

T92

5

T40

22

T143

21

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

246

1

T92

56

T143

107

T142

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

403

1

T26

1

T32

7

T143

13

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

723

1

T40

30

T144

64

T28

489

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

229

1

T26

3

T142

1

T145

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

445

1

T26

82

T92

241

T40

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

253

1

T26

32

T141

66

T146

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

149

1

T142

20

T60

1

T147

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

212

1

T142

136

T141

14

T145

30

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

292

1

T26

52

T32

1

T92

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

444

1

T40

1

T142

64

T148

6

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

147602

1

T6

14

T4

149

T7

976

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

154155

1

T6

436

T7

670

T5

562

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

150358

1

T7

571

T11

11

T5

80

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

156898

1

T4

94

T7

898

T5

2687

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1688498

1

T6

260

T7

486

T8

2908

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

159936

1

T7

1328

T11

1

T10

798

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

147558

1

T4

267

T7

19

T11

31

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

166148

1

T7

518

T5

13

T8

1790

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

400869

1

T3

4631

T7

1028

T5

73

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

396662

1

T3

2304

T7

438

T11

1

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

423683

1

T3

627

T7

785

T8

738

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

463903

1

T3

1561

T7

463

T5

153

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

487748

1

T3

8527

T6

223

T4

68

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

478983

1

T3

6513

T4

152

T7

1015

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

411563

1

T3

4621

T7

730

T5

151

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

399611

1

T3

2505

T6

392

T7

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

2912

1

T7

7

T8

51

T10

2

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3093

1

T6

9

T7

13

T5

16

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3508

1

T7

7

T5

2

T24

46

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

2882

1

T7

17

T8

14

T24

14

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

44062

1

T6

15

T8

48

T10

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3374

1

T7

17

T10

4

T24

13

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3287

1

T8

67

T10

3

T24

21

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3484

1

T7

8

T8

64

T24

9

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5462

1

T3

2

T7

24

T5

9

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5045

1

T3

60

T5

1

T8

5

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

4842

1

T3

18

T8

1

T24

20

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6160

1

T3

110

T7

1

T8

13

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8348

1

T3

83

T7

20

T19

164

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6847

1

T4

12

T7

10

T24

9

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5688

1

T5

1

T8

62

T10

3

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5393

1

T3

32

T8

54

T29

1

fifo_depth[2]

auto[0]

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5

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7