Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16800454	1			T3	67297		T6	2767		T4	490
all_pins[1]	16800454	1			T3	67297		T6	2767		T4	490
all_pins[2]	16800454	1			T3	67297		T6	2767		T4	490

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43155429	1			T3	163843		T6	7380		T4	1461
values[0x1]	7245933	1			T3	38048		T6	921		T4	9
transitions[0x0=>0x1]	7245812	1			T3	38048		T6	921		T4	9
transitions[0x1=>0x0]	7245821	1			T3	38048		T6	921		T4	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16781315	1			T3	67275		T6	2763		T4	481
all_pins[0]	values[0x1]	19139	1			T3	22		T6	4		T4	9
all_pins[0]	transitions[0x0=>0x1]	19094	1			T3	22		T6	4		T4	9
all_pins[0]	transitions[0x1=>0x0]	7226496	1			T3	38026		T6	917		T7	9366
all_pins[1]	values[0x0]	16800192	1			T3	67297		T6	2767		T4	490
all_pins[1]	values[0x1]	262	1			T24	3		T44	1		T45	1
all_pins[1]	transitions[0x0=>0x1]	229	1			T24	2		T44	1		T45	1
all_pins[1]	transitions[0x1=>0x0]	19106	1			T3	22		T6	4		T4	9
all_pins[2]	values[0x0]	9573922	1			T3	29271		T6	1850		T4	490
all_pins[2]	values[0x1]	7226532	1			T3	38026		T6	917		T7	9366
all_pins[2]	transitions[0x0=>0x1]	7226489	1			T3	38026		T6	917		T7	9366
all_pins[2]	transitions[0x1=>0x0]	219	1			T24	3		T44	1		T45	1