Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 783 1 T24 14 T44 24 T45 7
all_values[1] 783 1 T24 14 T44 24 T45 7
all_values[2] 783 1 T24 14 T44 24 T45 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1246 1 T24 22 T44 44 T45 13
auto[1] 1103 1 T24 20 T44 28 T45 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 929 1 T24 24 T44 30 T45 8
auto[1] 1420 1 T24 18 T44 42 T45 13


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1411 1 T24 29 T44 46 T45 11
auto[1] 938 1 T24 13 T44 26 T45 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 204 1 T24 4 T44 5 T45 3
all_values[0] auto[0] auto[0] auto[1] 76 1 T44 3 T125 1 T13 2
all_values[0] auto[0] auto[1] auto[0] 157 1 T24 4 T44 5 T45 1
all_values[0] auto[0] auto[1] auto[1] 61 1 T24 1 T44 2 T124 1
all_values[0] auto[1] auto[0] auto[1] 149 1 T24 4 T44 6 T45 2
all_values[0] auto[1] auto[1] auto[1] 136 1 T24 1 T44 3 T45 1
all_values[1] auto[0] auto[0] auto[0] 120 1 T24 2 T44 4 T45 1
all_values[1] auto[0] auto[0] auto[1] 109 1 T24 3 T44 6 T45 2
all_values[1] auto[0] auto[1] auto[0] 118 1 T24 2 T44 4 T125 1
all_values[1] auto[0] auto[1] auto[1] 94 1 T24 1 T44 2 T124 1
all_values[1] auto[1] auto[0] auto[1] 193 1 T24 3 T44 6 T45 2
all_values[1] auto[1] auto[1] auto[1] 149 1 T24 3 T44 2 T45 2
all_values[2] auto[0] auto[0] auto[0] 171 1 T24 6 T44 6 T45 2
all_values[2] auto[0] auto[0] auto[1] 66 1 T44 1 T32 1 T12 1
all_values[2] auto[0] auto[1] auto[0] 159 1 T24 6 T44 6 T45 1
all_values[2] auto[0] auto[1] auto[1] 76 1 T44 2 T45 1 T125 1
all_values[2] auto[1] auto[0] auto[1] 158 1 T44 7 T45 1 T124 3
all_values[2] auto[1] auto[1] auto[1] 153 1 T24 2 T44 2 T45 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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