Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3662	1			T3	8		T6	2		T4	1
sha2_none	3697	1			T3	6		T7	10		T5	9
sha2_512	7049	1			T3	8		T6	1		T7	7
sha2_384	6962	1			T3	10		T6	1		T7	13
sha2_256	5711	1			T3	10		T6	1		T4	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17515

1

T3

25

T6

4

T4

6

auto[1]

9901

1

T3

19

T6

1

T4

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9905

1

T3

19

T6

2

T4

4

auto[1]

17511

1

T3

25

T6

3

T4

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14208

1

T3

44

T6

2

T4

3

disabled

13208

1

T6

3

T4

5

T7

22

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4120	1			T3	7		T6	2		T4	3
key_none	7506	1			T3	8		T4	1		T7	8
key_1024	4035	1			T3	7		T7	5		T19	225
key_512	3435	1			T3	4		T6	1		T4	1
key_384	3047	1			T3	8		T6	1		T7	2
key_256	2629	1			T3	5		T6	1		T4	2
key_128	2566	1			T3	5		T4	1		T7	9

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17425

1

T3

23

T6

3

T4

5

auto[1]

9991

1

T3

21

T6

2

T4

3

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27241

1

T3

44

T6

5

T4

8

disabled

175

1

T43

1

T44

2

T45

7

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1432

1

T3

5

T7

5

T5

1

enabled

auto[0]

auto[0]

auto[1]

1402

1

T3

3

T7

1

T11

1

enabled

auto[0]

auto[1]

auto[0]

1418

1

T3

5

T7

3

T8

4

enabled

auto[0]

auto[1]

auto[1]

1484

1

T3

6

T7

2

T5

1

enabled

auto[1]

auto[0]

auto[0]

4155

1

T3

9

T6

1

T4

2

enabled

auto[1]

auto[0]

auto[1]

1457

1

T3

8

T4

1

T7

5

enabled

auto[1]

auto[1]

auto[0]

1470

1

T3

4

T7

3

T5

2

enabled

auto[1]

auto[1]

auto[1]

1390

1

T3

4

T6

1

T7

1

disabled

auto[0]

auto[0]

auto[0]

1045

1

T6

1

T4

2

T7

6

disabled

auto[0]

auto[0]

auto[1]

1078

1

T6

1

T4

1

T7

2

disabled

auto[0]

auto[1]

auto[0]

1026

1

T7

3

T11

1

T5

1

disabled

auto[0]

auto[1]

auto[1]

1020

1

T4

1

T7

2

T5

2

disabled

auto[1]

auto[0]

auto[0]

5882

1

T6

1

T7

1

T8

3

disabled

auto[1]

auto[0]

auto[1]

1064

1

T7

5

T11

1

T10

4

disabled

auto[1]

auto[1]

auto[0]

997

1

T4

1

T7

1

T11

2

disabled

auto[1]

auto[1]

auto[1]

1096

1

T7

2

T5

1

T8

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14138

1

T3

44

T6

2

T4

3

enabled

disabled

70

1

T44

1

T45

2

T135

1

disabled

disabled

105

1

T43

1

T44

1

T45

5

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13103

1

T6

3

T4

5

T7

22

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	963	1			T3	2		T6	1		T4	1
key_invalid	sha2_none	787	1			T3	2		T7	4		T5	1
key_invalid	sha2_512	767	1			T3	1		T6	1		T8	2
key_invalid	sha2_384	749	1			T3	1		T7	5		T8	1
key_invalid	sha2_256	750	1			T3	1		T4	2		T10	3
key_none	sha2_invalid	456	1			T3	1		T7	2		T8	1
key_none	sha2_none	491	1			T8	1		T10	2		T29	1
key_none	sha2_512	2446	1			T3	2		T7	2		T5	1
key_none	sha2_384	2539	1			T3	2		T7	1		T11	1
key_none	sha2_256	1529	1			T3	2		T4	1		T7	3
key_1024	sha2_invalid	436	1			T7	1		T8	2		T10	2
key_1024	sha2_none	493	1			T3	3		T7	1		T10	2
key_1024	sha2_512	1653	1			T19	225		T8	1		T29	1
key_1024	sha2_384	878	1			T3	2		T7	1		T8	1
key_512	sha2_invalid	463	1			T3	1		T8	1		T10	2
key_512	sha2_none	503	1			T3	1		T7	3		T5	4
key_512	sha2_512	546	1			T7	1		T8	1		T24	7
key_512	sha2_384	1144	1			T3	1		T7	1		T5	1
key_512	sha2_256	740	1			T3	1		T6	1		T4	1
key_384	sha2_invalid	466	1			T3	2		T6	1		T8	2
key_384	sha2_none	478	1			T5	1		T8	1		T10	2
key_384	sha2_512	538	1			T3	1		T7	1		T11	1
key_384	sha2_384	549	1			T3	3		T7	1		T8	1
key_384	sha2_256	980	1			T3	1		T8	1		T10	1
key_256	sha2_invalid	430	1			T3	1		T24	5		T43	1
key_256	sha2_none	427	1			T5	2		T10	1		T24	3
key_256	sha2_512	595	1			T3	2		T7	1		T5	1
key_256	sha2_384	536	1			T6	1		T7	2		T8	1
key_256	sha2_256	600	1			T3	2		T4	2		T7	1
key_128	sha2_invalid	434	1			T3	1		T7	1		T10	1
key_128	sha2_none	499	1			T7	2		T5	1		T10	2
key_128	sha2_512	489	1			T3	2		T7	2		T11	1
key_128	sha2_384	556	1			T3	1		T7	2		T8	1
key_128	sha2_256	551	1			T3	1		T4	1		T7	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

543

1

T3

2

T7

1

T8

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	963	1			T3	2		T6	1		T4	1
key_invalid	sha2_none	787	1			T3	2		T7	4		T5	1
key_invalid	sha2_512	767	1			T3	1		T6	1		T8	2
key_invalid	sha2_384	749	1			T3	1		T7	5		T8	1
key_invalid	sha2_256	750	1			T3	1		T4	2		T10	3
key_none	sha2_invalid	456	1			T3	1		T7	2		T8	1
key_none	sha2_none	491	1			T8	1		T10	2		T29	1
key_none	sha2_512	2446	1			T3	2		T7	2		T5	1
key_none	sha2_384	2539	1			T3	2		T7	1		T11	1
key_none	sha2_256	1529	1			T3	2		T4	1		T7	3
key_1024	sha2_invalid	436	1			T7	1		T8	2		T10	2
key_1024	sha2_none	493	1			T3	3		T7	1		T10	2
key_1024	sha2_512	1653	1			T19	225		T8	1		T29	1
key_1024	sha2_384	878	1			T3	2		T7	1		T8	1
key_1024	sha2_256	543	1			T3	2		T7	1		T8	2
key_512	sha2_invalid	463	1			T3	1		T8	1		T10	2
key_512	sha2_none	503	1			T3	1		T7	3		T5	4
key_512	sha2_512	546	1			T7	1		T8	1		T24	7
key_512	sha2_384	1144	1			T3	1		T7	1		T5	1
key_512	sha2_256	740	1			T3	1		T6	1		T4	1
key_384	sha2_invalid	466	1			T3	2		T6	1		T8	2
key_384	sha2_none	478	1			T5	1		T8	1		T10	2
key_384	sha2_512	538	1			T3	1		T7	1		T11	1
key_384	sha2_384	549	1			T3	3		T7	1		T8	1
key_384	sha2_256	980	1			T3	1		T8	1		T10	1
key_256	sha2_invalid	430	1			T3	1		T24	5		T43	1
key_256	sha2_none	427	1			T5	2		T10	1		T24	3
key_256	sha2_512	595	1			T3	2		T7	1		T5	1
key_256	sha2_384	536	1			T6	1		T7	2		T8	1
key_256	sha2_256	600	1			T3	2		T4	2		T7	1
key_128	sha2_invalid	434	1			T3	1		T7	1		T10	1
key_128	sha2_none	499	1			T7	2		T5	1		T10	2
key_128	sha2_512	489	1			T3	2		T7	2		T11	1
key_128	sha2_384	556	1			T3	1		T7	2		T8	1
key_128	sha2_256	551	1			T3	1		T4	1		T7	2