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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85


Total test records in report: 655
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T126 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4219833766 Aug 12 05:19:44 PM PDT 24 Aug 12 05:19:47 PM PDT 24 376680096 ps
T532 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3946030636 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:32 PM PDT 24 208687086 ps
T111 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3657273750 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:33 PM PDT 24 214949069 ps
T112 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1566206699 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:31 PM PDT 24 179612079 ps
T113 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2371672981 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:26 PM PDT 24 121734779 ps
T533 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1360917475 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:29 PM PDT 24 76721199 ps
T534 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3990322110 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:29 PM PDT 24 178726636 ps
T535 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4094989000 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:29 PM PDT 24 253650493 ps
T536 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2763468363 Aug 12 05:19:11 PM PDT 24 Aug 12 05:19:13 PM PDT 24 278919068 ps
T537 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1983474397 Aug 12 05:19:47 PM PDT 24 Aug 12 05:19:48 PM PDT 24 45579102 ps
T132 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4245329502 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:29 PM PDT 24 553336733 ps
T114 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3699760685 Aug 12 05:19:15 PM PDT 24 Aug 12 05:19:17 PM PDT 24 395244772 ps
T538 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1267013396 Aug 12 05:19:45 PM PDT 24 Aug 12 05:19:46 PM PDT 24 182994345 ps
T115 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.888703646 Aug 12 05:19:16 PM PDT 24 Aug 12 05:19:17 PM PDT 24 318980212 ps
T116 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.747401391 Aug 12 05:19:25 PM PDT 24 Aug 12 05:19:27 PM PDT 24 232861345 ps
T539 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2832237038 Aug 12 05:19:26 PM PDT 24 Aug 12 05:19:28 PM PDT 24 35883029 ps
T540 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1315837170 Aug 12 05:19:08 PM PDT 24 Aug 12 05:19:13 PM PDT 24 381697717 ps
T99 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1746574471 Aug 12 05:19:09 PM PDT 24 Aug 12 05:19:13 PM PDT 24 57088839 ps
T117 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1824280445 Aug 12 05:19:14 PM PDT 24 Aug 12 05:19:16 PM PDT 24 144312284 ps
T127 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2773479445 Aug 12 05:19:21 PM PDT 24 Aug 12 05:19:25 PM PDT 24 965317379 ps
T541 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3129089715 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:31 PM PDT 24 303942826 ps
T118 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3632089343 Aug 12 05:19:12 PM PDT 24 Aug 12 05:19:15 PM PDT 24 87445846 ps
T542 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.199275005 Aug 12 05:19:16 PM PDT 24 Aug 12 05:19:18 PM PDT 24 376177557 ps
T543 /workspace/coverage/cover_reg_top/2.hmac_intr_test.406271324 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:28 PM PDT 24 158775915 ps
T544 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1164506359 Aug 12 05:19:22 PM PDT 24 Aug 12 05:19:25 PM PDT 24 1174968537 ps
T119 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2006071736 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:30 PM PDT 24 51294352 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2444182114 Aug 12 05:19:20 PM PDT 24 Aug 12 05:19:34 PM PDT 24 313754310 ps
T545 /workspace/coverage/cover_reg_top/45.hmac_intr_test.59156451 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:29 PM PDT 24 63567528 ps
T128 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3556627015 Aug 12 05:19:23 PM PDT 24 Aug 12 05:19:26 PM PDT 24 327930110 ps
T546 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.940938296 Aug 12 05:19:36 PM PDT 24 Aug 12 05:30:39 PM PDT 24 50801863414 ps
T547 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2092126749 Aug 12 05:19:43 PM PDT 24 Aug 12 05:19:44 PM PDT 24 50432210 ps
T548 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2490728754 Aug 12 05:19:20 PM PDT 24 Aug 12 05:19:21 PM PDT 24 28317723 ps
T120 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.476583526 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:26 PM PDT 24 75717032 ps
T130 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1629684583 Aug 12 05:19:21 PM PDT 24 Aug 12 05:19:26 PM PDT 24 268462831 ps
T549 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.471818592 Aug 12 05:19:22 PM PDT 24 Aug 12 05:19:24 PM PDT 24 140551052 ps
T550 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3930200151 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:30 PM PDT 24 13326468 ps
T101 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4034660213 Aug 12 05:19:20 PM PDT 24 Aug 12 05:19:30 PM PDT 24 2369152681 ps
T551 /workspace/coverage/cover_reg_top/24.hmac_intr_test.176455159 Aug 12 05:19:41 PM PDT 24 Aug 12 05:19:41 PM PDT 24 11986947 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2349299884 Aug 12 05:19:32 PM PDT 24 Aug 12 05:19:41 PM PDT 24 546738485 ps
T552 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2416190310 Aug 12 05:19:30 PM PDT 24 Aug 12 05:19:31 PM PDT 24 46621863 ps
T553 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.884860933 Aug 12 05:19:23 PM PDT 24 Aug 12 05:19:24 PM PDT 24 66336922 ps
T554 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3834521628 Aug 12 05:19:18 PM PDT 24 Aug 12 05:19:23 PM PDT 24 114276037 ps
T555 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2690434213 Aug 12 05:19:26 PM PDT 24 Aug 12 05:19:27 PM PDT 24 69581102 ps
T556 /workspace/coverage/cover_reg_top/4.hmac_intr_test.691666912 Aug 12 05:19:18 PM PDT 24 Aug 12 05:19:19 PM PDT 24 14340316 ps
T557 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2718690304 Aug 12 05:19:12 PM PDT 24 Aug 12 05:19:15 PM PDT 24 523230798 ps
T558 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3516522640 Aug 12 05:19:40 PM PDT 24 Aug 12 05:19:40 PM PDT 24 75630603 ps
T559 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3026950978 Aug 12 05:19:23 PM PDT 24 Aug 12 05:19:26 PM PDT 24 125556220 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.249528646 Aug 12 05:19:13 PM PDT 24 Aug 12 05:19:14 PM PDT 24 20545363 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3775873304 Aug 12 05:19:26 PM PDT 24 Aug 12 05:19:28 PM PDT 24 373229413 ps
T561 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2755781351 Aug 12 05:19:16 PM PDT 24 Aug 12 05:19:17 PM PDT 24 51094477 ps
T131 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1277678784 Aug 12 05:19:22 PM PDT 24 Aug 12 05:19:26 PM PDT 24 145981312 ps
T133 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3844592383 Aug 12 05:19:32 PM PDT 24 Aug 12 05:19:35 PM PDT 24 672917179 ps
T562 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2621104412 Aug 12 05:19:30 PM PDT 24 Aug 12 05:19:31 PM PDT 24 12571112 ps
T563 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2189108658 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:25 PM PDT 24 11462050 ps
T104 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3431115288 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:30 PM PDT 24 17053250 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.18545038 Aug 12 05:19:16 PM PDT 24 Aug 12 05:19:18 PM PDT 24 198770448 ps
T565 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.502345561 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:25 PM PDT 24 427399218 ps
T566 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1474278412 Aug 12 05:19:22 PM PDT 24 Aug 12 05:19:23 PM PDT 24 13470338 ps
T567 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2302817638 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:25 PM PDT 24 16183188 ps
T568 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3926936349 Aug 12 05:19:36 PM PDT 24 Aug 12 05:19:37 PM PDT 24 17780049 ps
T569 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2953259118 Aug 12 05:19:15 PM PDT 24 Aug 12 05:19:18 PM PDT 24 47740429 ps
T570 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1202118198 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:26 PM PDT 24 40876381 ps
T571 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.383908443 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:27 PM PDT 24 183463455 ps
T572 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2561578028 Aug 12 05:19:40 PM PDT 24 Aug 12 05:19:43 PM PDT 24 581830416 ps
T573 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2811854008 Aug 12 05:19:15 PM PDT 24 Aug 12 05:19:16 PM PDT 24 32263875 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1863756653 Aug 12 05:19:12 PM PDT 24 Aug 12 05:19:15 PM PDT 24 96592972 ps
T575 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.624812112 Aug 12 05:19:15 PM PDT 24 Aug 12 05:19:17 PM PDT 24 406561894 ps
T105 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2282031432 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:28 PM PDT 24 29567571 ps
T576 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2759743761 Aug 12 05:19:13 PM PDT 24 Aug 12 05:19:14 PM PDT 24 12333057 ps
T577 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2957170464 Aug 12 05:19:19 PM PDT 24 Aug 12 05:19:23 PM PDT 24 241620923 ps
T578 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2765322765 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:32 PM PDT 24 15484361 ps
T579 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3628903366 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:32 PM PDT 24 1238381612 ps
T580 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3971155238 Aug 12 05:19:44 PM PDT 24 Aug 12 05:19:44 PM PDT 24 23647501 ps
T106 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1578418445 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:28 PM PDT 24 59403113 ps
T581 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3137807128 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:24 PM PDT 24 39676186 ps
T582 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2016854205 Aug 12 05:19:23 PM PDT 24 Aug 12 05:19:25 PM PDT 24 26735437 ps
T583 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2702492758 Aug 12 05:19:14 PM PDT 24 Aug 12 05:19:15 PM PDT 24 43538768 ps
T584 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2696714101 Aug 12 05:19:36 PM PDT 24 Aug 12 05:19:38 PM PDT 24 1349703348 ps
T585 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3165271145 Aug 12 05:19:37 PM PDT 24 Aug 12 05:19:38 PM PDT 24 18452107 ps
T586 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1940118738 Aug 12 05:19:26 PM PDT 24 Aug 12 05:19:27 PM PDT 24 18487964 ps
T587 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1556152539 Aug 12 05:19:17 PM PDT 24 Aug 12 05:19:18 PM PDT 24 353053232 ps
T588 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2989458616 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:29 PM PDT 24 16609156 ps
T589 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3419721189 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:30 PM PDT 24 149264341 ps
T590 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.392058661 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:30 PM PDT 24 261779175 ps
T591 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2722118578 Aug 12 05:19:13 PM PDT 24 Aug 12 05:19:16 PM PDT 24 634092814 ps
T592 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1016611398 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:29 PM PDT 24 61780088 ps
T593 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1394321442 Aug 12 05:19:41 PM PDT 24 Aug 12 05:19:44 PM PDT 24 54088630 ps
T594 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4146526680 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:30 PM PDT 24 285474971 ps
T595 /workspace/coverage/cover_reg_top/22.hmac_intr_test.700852080 Aug 12 05:19:48 PM PDT 24 Aug 12 05:19:48 PM PDT 24 14444756 ps
T596 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1849015801 Aug 12 05:19:35 PM PDT 24 Aug 12 05:19:36 PM PDT 24 41797399 ps
T597 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2158786467 Aug 12 05:19:13 PM PDT 24 Aug 12 05:19:13 PM PDT 24 222179087 ps
T598 /workspace/coverage/cover_reg_top/29.hmac_intr_test.233952727 Aug 12 05:19:32 PM PDT 24 Aug 12 05:19:33 PM PDT 24 14333254 ps
T599 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4273739363 Aug 12 05:19:41 PM PDT 24 Aug 12 05:19:41 PM PDT 24 45671887 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3285192985 Aug 12 05:19:13 PM PDT 24 Aug 12 05:19:15 PM PDT 24 19777410 ps
T600 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1336430598 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:29 PM PDT 24 38645830 ps
T601 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4040782179 Aug 12 05:19:17 PM PDT 24 Aug 12 05:19:34 PM PDT 24 4359509727 ps
T107 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2779534228 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:29 PM PDT 24 281188220 ps
T602 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4055510143 Aug 12 05:19:23 PM PDT 24 Aug 12 05:19:24 PM PDT 24 31931697 ps
T603 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3890523583 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:29 PM PDT 24 11840670 ps
T604 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.177781840 Aug 12 05:19:18 PM PDT 24 Aug 12 05:19:19 PM PDT 24 680769799 ps
T605 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2290513452 Aug 12 05:19:18 PM PDT 24 Aug 12 05:19:18 PM PDT 24 37340822 ps
T606 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.668767921 Aug 12 05:19:34 PM PDT 24 Aug 12 05:19:37 PM PDT 24 140619570 ps
T607 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1447962029 Aug 12 05:19:33 PM PDT 24 Aug 12 05:19:34 PM PDT 24 33899407 ps
T109 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2048211374 Aug 12 05:19:14 PM PDT 24 Aug 12 05:19:15 PM PDT 24 44231748 ps
T608 /workspace/coverage/cover_reg_top/41.hmac_intr_test.4094251217 Aug 12 05:19:40 PM PDT 24 Aug 12 05:19:40 PM PDT 24 20785009 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1739456371 Aug 12 05:19:07 PM PDT 24 Aug 12 05:19:10 PM PDT 24 104234864 ps
T610 /workspace/coverage/cover_reg_top/44.hmac_intr_test.832936720 Aug 12 05:19:37 PM PDT 24 Aug 12 05:19:38 PM PDT 24 46152736 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1373554072 Aug 12 05:19:14 PM PDT 24 Aug 12 05:19:15 PM PDT 24 22962612 ps
T611 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3557469545 Aug 12 05:19:22 PM PDT 24 Aug 12 05:19:23 PM PDT 24 46541886 ps
T612 /workspace/coverage/cover_reg_top/46.hmac_intr_test.425395478 Aug 12 05:19:46 PM PDT 24 Aug 12 05:19:47 PM PDT 24 56469822 ps
T613 /workspace/coverage/cover_reg_top/21.hmac_intr_test.706079803 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:30 PM PDT 24 48598198 ps
T614 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1017642293 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:27 PM PDT 24 639983054 ps
T615 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2023562271 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:30 PM PDT 24 17861906 ps
T616 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2083227091 Aug 12 05:19:28 PM PDT 24 Aug 12 05:19:29 PM PDT 24 18272846 ps
T617 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1626715264 Aug 12 05:19:16 PM PDT 24 Aug 12 05:19:19 PM PDT 24 170283637 ps
T618 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.582260192 Aug 12 05:19:44 PM PDT 24 Aug 12 05:19:45 PM PDT 24 20391957 ps
T619 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2346476643 Aug 12 05:19:21 PM PDT 24 Aug 12 05:19:22 PM PDT 24 17520507 ps
T620 /workspace/coverage/cover_reg_top/28.hmac_intr_test.471139562 Aug 12 05:19:33 PM PDT 24 Aug 12 05:19:34 PM PDT 24 36756978 ps
T621 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4111683222 Aug 12 05:19:21 PM PDT 24 Aug 12 05:19:23 PM PDT 24 314620056 ps
T622 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2966658038 Aug 12 05:19:09 PM PDT 24 Aug 12 05:19:10 PM PDT 24 49417449 ps
T623 /workspace/coverage/cover_reg_top/36.hmac_intr_test.850889583 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:30 PM PDT 24 13245839 ps
T624 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.581176512 Aug 12 05:19:15 PM PDT 24 Aug 12 05:19:16 PM PDT 24 86969987 ps
T625 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3243564109 Aug 12 05:19:30 PM PDT 24 Aug 12 05:19:31 PM PDT 24 35388501 ps
T626 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.557491287 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:25 PM PDT 24 61537261 ps
T627 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.22881306 Aug 12 05:19:32 PM PDT 24 Aug 12 05:19:33 PM PDT 24 417838274 ps
T628 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3612989677 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:27 PM PDT 24 512958311 ps
T629 /workspace/coverage/cover_reg_top/27.hmac_intr_test.4141421782 Aug 12 05:19:46 PM PDT 24 Aug 12 05:19:47 PM PDT 24 39512453 ps
T630 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2131052005 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:32 PM PDT 24 34870395 ps
T631 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1895190030 Aug 12 05:19:23 PM PDT 24 Aug 12 05:19:24 PM PDT 24 46016819 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2114349866 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:33 PM PDT 24 80328336 ps
T633 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.328153572 Aug 12 05:19:42 PM PDT 24 Aug 12 05:19:45 PM PDT 24 35548483 ps
T634 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4055169842 Aug 12 05:19:22 PM PDT 24 Aug 12 05:20:05 PM PDT 24 7575443449 ps
T635 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1677999744 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:32 PM PDT 24 149323647 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_intr_test.80129351 Aug 12 05:19:21 PM PDT 24 Aug 12 05:19:22 PM PDT 24 38539746 ps
T134 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2609110929 Aug 12 05:19:32 PM PDT 24 Aug 12 05:19:35 PM PDT 24 160728140 ps
T637 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4008086235 Aug 12 05:19:16 PM PDT 24 Aug 12 05:19:20 PM PDT 24 108852549 ps
T638 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2039579255 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:32 PM PDT 24 42481641 ps
T639 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3955103755 Aug 12 05:19:29 PM PDT 24 Aug 12 05:19:31 PM PDT 24 328821145 ps
T640 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.34219166 Aug 12 05:19:22 PM PDT 24 Aug 12 05:19:27 PM PDT 24 340894129 ps
T641 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3474351925 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:32 PM PDT 24 78117826 ps
T642 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2245509439 Aug 12 05:19:40 PM PDT 24 Aug 12 05:19:41 PM PDT 24 31419335 ps
T643 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2390505603 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:28 PM PDT 24 60915516 ps
T644 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.660928360 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:26 PM PDT 24 53507255 ps
T645 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1442680371 Aug 12 05:19:24 PM PDT 24 Aug 12 05:19:26 PM PDT 24 140498976 ps
T646 /workspace/coverage/cover_reg_top/23.hmac_intr_test.908224240 Aug 12 05:19:30 PM PDT 24 Aug 12 05:19:30 PM PDT 24 57206778 ps
T647 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.97856553 Aug 12 05:19:14 PM PDT 24 Aug 12 05:19:17 PM PDT 24 207260270 ps
T648 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3175163632 Aug 12 05:19:20 PM PDT 24 Aug 12 05:19:24 PM PDT 24 1456278981 ps
T64 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2342249189 Aug 12 05:19:39 PM PDT 24 Aug 12 05:19:43 PM PDT 24 928637619 ps
T649 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4071322049 Aug 12 05:19:17 PM PDT 24 Aug 12 05:19:18 PM PDT 24 30110671 ps
T650 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.124369856 Aug 12 05:19:15 PM PDT 24 Aug 12 05:19:21 PM PDT 24 113066028 ps
T651 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4043245739 Aug 12 05:19:26 PM PDT 24 Aug 12 05:19:28 PM PDT 24 362195218 ps
T652 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2822129751 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:29 PM PDT 24 285002648 ps
T653 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1645089433 Aug 12 05:19:05 PM PDT 24 Aug 12 05:19:06 PM PDT 24 29826661 ps
T654 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2598371605 Aug 12 05:19:31 PM PDT 24 Aug 12 05:19:32 PM PDT 24 19046107 ps
T655 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3675509568 Aug 12 05:19:27 PM PDT 24 Aug 12 05:19:29 PM PDT 24 132113718 ps

Test location /workspace/coverage/default/48.hmac_long_msg.79995352
Short name T8
Test name
Test status
Simulation time 11943940196 ps
CPU time 171.54 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:27:25 PM PDT 24
Peak memory 200644 kb
Host smart-04574788-623d-4efa-9a11-b8a4adb0b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79995352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.79995352
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1866884972
Short name T45
Test name
Test status
Simulation time 206246342670 ps
CPU time 914.4 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:39:02 PM PDT 24
Peak memory 209036 kb
Host smart-705d456d-77a4-461f-82e9-08629b5feeab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866884972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1866884972
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.362531635
Short name T23
Test name
Test status
Simulation time 3726557728 ps
CPU time 290.06 seconds
Started Aug 12 05:23:26 PM PDT 24
Finished Aug 12 05:28:16 PM PDT 24
Peak memory 580800 kb
Host smart-3e837c32-06d6-4ed7-9893-eb7742964ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362531635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.362531635
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1178174675
Short name T24
Test name
Test status
Simulation time 41124600806 ps
CPU time 497.93 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:32:37 PM PDT 24
Peak memory 200716 kb
Host smart-98194e40-025e-48f6-a053-477b50b7dfab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178174675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1178174675
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3763064292
Short name T129
Test name
Test status
Simulation time 159502386 ps
CPU time 3.85 seconds
Started Aug 12 05:19:35 PM PDT 24
Finished Aug 12 05:19:39 PM PDT 24
Peak memory 199712 kb
Host smart-23fcb888-98bc-4654-ab18-2bcc3c4df3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763064292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3763064292
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3310386103
Short name T15
Test name
Test status
Simulation time 13747973542 ps
CPU time 1428.79 seconds
Started Aug 12 05:23:37 PM PDT 24
Finished Aug 12 05:47:26 PM PDT 24
Peak memory 697272 kb
Host smart-342aabb7-c832-4154-8379-70dc33ab7cab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310386103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3310386103
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2415903845
Short name T79
Test name
Test status
Simulation time 157642767 ps
CPU time 0.59 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:23:50 PM PDT 24
Peak memory 196688 kb
Host smart-87170cb2-6f60-434d-8f63-9dbc9a8a6ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415903845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2415903845
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.205255506
Short name T83
Test name
Test status
Simulation time 9605627526 ps
CPU time 109.18 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 200824 kb
Host smart-da51d4ce-b9eb-416e-8a01-4f86cdc5e55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205255506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.205255506
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3870154118
Short name T142
Test name
Test status
Simulation time 6374830252 ps
CPU time 334.83 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:29:36 PM PDT 24
Peak memory 199248 kb
Host smart-5f1942b8-cd88-4229-a757-0554aae12b08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870154118 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3870154118
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1746574471
Short name T99
Test name
Test status
Simulation time 57088839 ps
CPU time 3.26 seconds
Started Aug 12 05:19:09 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 199632 kb
Host smart-ee01f621-39a0-4569-b194-9292e84e5e6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746574471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1746574471
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2727651923
Short name T48
Test name
Test status
Simulation time 482331254 ps
CPU time 1.04 seconds
Started Aug 12 05:23:25 PM PDT 24
Finished Aug 12 05:23:26 PM PDT 24
Peak memory 220132 kb
Host smart-c749d1ec-ddf5-47f8-a0e0-9d1ce4fe6103
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727651923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2727651923
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2531306451
Short name T139
Test name
Test status
Simulation time 1242847079 ps
CPU time 14.28 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:23:59 PM PDT 24
Peak memory 200832 kb
Host smart-9cba898e-7225-4659-b38b-69e372c5a871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531306451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2531306451
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3556627015
Short name T128
Test name
Test status
Simulation time 327930110 ps
CPU time 2.99 seconds
Started Aug 12 05:19:23 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199848 kb
Host smart-c6f98f20-fa48-4544-8336-430f2159e230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556627015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3556627015
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1663940094
Short name T92
Test name
Test status
Simulation time 19955907145 ps
CPU time 213.1 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:27:35 PM PDT 24
Peak memory 200700 kb
Host smart-b57367c8-aedc-458d-9871-571b2c25ec26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663940094 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1663940094
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2013133905
Short name T124
Test name
Test status
Simulation time 711426059982 ps
CPU time 3740.86 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 06:26:09 PM PDT 24
Peak memory 848464 kb
Host smart-126f6b71-393d-47c3-8f45-2e2d957828fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013133905 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2013133905
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2342249189
Short name T64
Test name
Test status
Simulation time 928637619 ps
CPU time 4.21 seconds
Started Aug 12 05:19:39 PM PDT 24
Finished Aug 12 05:19:43 PM PDT 24
Peak memory 199800 kb
Host smart-e3bc023f-8f85-47f5-a9e1-e2c0bb3113be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342249189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2342249189
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.116654781
Short name T431
Test name
Test status
Simulation time 1028126487 ps
CPU time 55.78 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:52 PM PDT 24
Peak memory 200764 kb
Host smart-2964bcc3-ad0e-4671-9e36-cb0e9edcc29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116654781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.116654781
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3632089343
Short name T118
Test name
Test status
Simulation time 87445846 ps
CPU time 1.9 seconds
Started Aug 12 05:19:12 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 199776 kb
Host smart-b8366899-0f49-4b06-96a6-6015f591984e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632089343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3632089343
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1571127136
Short name T47
Test name
Test status
Simulation time 181931498395 ps
CPU time 660.62 seconds
Started Aug 12 05:23:19 PM PDT 24
Finished Aug 12 05:34:20 PM PDT 24
Peak memory 200772 kb
Host smart-3862882f-7be1-45ae-9bdd-54aaecba632f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1571127136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1571127136
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1957199634
Short name T95
Test name
Test status
Simulation time 131293642964 ps
CPU time 1389.58 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:47:11 PM PDT 24
Peak memory 528592 kb
Host smart-76da8553-ea6b-4863-8a88-91cbdb4670c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957199634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1957199634
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2612080327
Short name T40
Test name
Test status
Simulation time 2369140524 ps
CPU time 67.94 seconds
Started Aug 12 05:23:17 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 200620 kb
Host smart-259f242a-83f9-4dc2-a1b5-e02c0d5de10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612080327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2612080327
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.469590626
Short name T18
Test name
Test status
Simulation time 1819778900 ps
CPU time 28 seconds
Started Aug 12 05:23:21 PM PDT 24
Finished Aug 12 05:23:50 PM PDT 24
Peak memory 201408 kb
Host smart-5cf5b5e6-11e7-4709-abb5-dfc4007ae3bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469590626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.469590626
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1315837170
Short name T540
Test name
Test status
Simulation time 381697717 ps
CPU time 5.45 seconds
Started Aug 12 05:19:08 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 199748 kb
Host smart-5d5f1c45-17e5-444f-926e-4d18cd4075e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315837170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1315837170
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1645089433
Short name T653
Test name
Test status
Simulation time 29826661 ps
CPU time 0.86 seconds
Started Aug 12 05:19:05 PM PDT 24
Finished Aug 12 05:19:06 PM PDT 24
Peak memory 199200 kb
Host smart-09504985-f7bf-46d3-a9d4-d2502784ca8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645089433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1645089433
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1739456371
Short name T609
Test name
Test status
Simulation time 104234864 ps
CPU time 2.25 seconds
Started Aug 12 05:19:07 PM PDT 24
Finished Aug 12 05:19:10 PM PDT 24
Peak memory 199820 kb
Host smart-97b37c80-b803-4909-91f3-8028961b666a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739456371 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1739456371
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2811854008
Short name T573
Test name
Test status
Simulation time 32263875 ps
CPU time 0.92 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:16 PM PDT 24
Peak memory 199592 kb
Host smart-52fe5592-cd83-427c-814a-d5de5d44357c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811854008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2811854008
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2966658038
Short name T622
Test name
Test status
Simulation time 49417449 ps
CPU time 0.65 seconds
Started Aug 12 05:19:09 PM PDT 24
Finished Aug 12 05:19:10 PM PDT 24
Peak memory 194964 kb
Host smart-a626a66a-2305-4856-b2e0-6e55a8fc2a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966658038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2966658038
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2718690304
Short name T557
Test name
Test status
Simulation time 523230798 ps
CPU time 2.94 seconds
Started Aug 12 05:19:12 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 199700 kb
Host smart-9a7376d6-548d-4f78-b75f-b4b6ef1cb2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718690304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2718690304
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1049946933
Short name T81
Test name
Test status
Simulation time 167690035 ps
CPU time 1.84 seconds
Started Aug 12 05:19:11 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 199776 kb
Host smart-8c6bb013-44d6-48af-a697-769221c8649c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049946933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1049946933
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4116352191
Short name T98
Test name
Test status
Simulation time 2016281723 ps
CPU time 9.09 seconds
Started Aug 12 05:19:18 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 199788 kb
Host smart-8bbe1be1-e174-4146-b099-bedc94e657cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116352191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4116352191
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.124369856
Short name T650
Test name
Test status
Simulation time 113066028 ps
CPU time 5.37 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:21 PM PDT 24
Peak memory 199816 kb
Host smart-cf9af788-f1f4-4fa5-bc3b-d7efc07d48de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124369856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.124369856
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.249528646
Short name T560
Test name
Test status
Simulation time 20545363 ps
CPU time 0.74 seconds
Started Aug 12 05:19:13 PM PDT 24
Finished Aug 12 05:19:14 PM PDT 24
Peak memory 197892 kb
Host smart-aac1fd78-9959-491a-8062-b212c8ef8911
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249528646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.249528646
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4043245739
Short name T651
Test name
Test status
Simulation time 362195218 ps
CPU time 2.27 seconds
Started Aug 12 05:19:26 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 199824 kb
Host smart-cbdce505-5624-4ab4-96e3-33c4ee999ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043245739 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4043245739
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.581176512
Short name T624
Test name
Test status
Simulation time 86969987 ps
CPU time 0.84 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:16 PM PDT 24
Peak memory 198956 kb
Host smart-834fc946-8552-4e7a-a9d4-176e1cb2c087
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581176512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.581176512
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2759743761
Short name T576
Test name
Test status
Simulation time 12333057 ps
CPU time 0.59 seconds
Started Aug 12 05:19:13 PM PDT 24
Finished Aug 12 05:19:14 PM PDT 24
Peak memory 194864 kb
Host smart-8031c4d2-e6a9-451f-a914-2cdc629fb034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759743761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2759743761
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3675509568
Short name T655
Test name
Test status
Simulation time 132113718 ps
CPU time 1.61 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199688 kb
Host smart-cff5d8a7-766a-4725-abb3-9f99bcbb01e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675509568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3675509568
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1863756653
Short name T574
Test name
Test status
Simulation time 96592972 ps
CPU time 2.45 seconds
Started Aug 12 05:19:12 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 199756 kb
Host smart-36569664-a9c3-4af2-a1ba-4896e4993992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863756653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1863756653
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.421502752
Short name T63
Test name
Test status
Simulation time 666989458 ps
CPU time 3.02 seconds
Started Aug 12 05:19:08 PM PDT 24
Finished Aug 12 05:19:11 PM PDT 24
Peak memory 199808 kb
Host smart-a883db8d-28a5-4cc9-9eae-f01ac077cefa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421502752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.421502752
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1360917475
Short name T533
Test name
Test status
Simulation time 76721199 ps
CPU time 1.32 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199836 kb
Host smart-2a5207f4-acb0-49e6-952c-2715470f53db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360917475 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1360917475
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3557469545
Short name T611
Test name
Test status
Simulation time 46541886 ps
CPU time 0.8 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 199000 kb
Host smart-47994afc-18a3-48bc-96dc-64488583a0c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557469545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3557469545
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3990322110
Short name T534
Test name
Test status
Simulation time 178726636 ps
CPU time 0.6 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 194900 kb
Host smart-26856597-523b-42ef-b378-6f8d9c4740bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990322110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3990322110
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4146526680
Short name T594
Test name
Test status
Simulation time 285474971 ps
CPU time 2.26 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 199764 kb
Host smart-b5c4c621-86bc-4586-a988-d24241ebbaeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146526680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4146526680
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1016611398
Short name T592
Test name
Test status
Simulation time 61780088 ps
CPU time 1.69 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199840 kb
Host smart-b3e0020d-9432-4dff-bf79-c3bb703a41b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016611398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1016611398
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.557491287
Short name T626
Test name
Test status
Simulation time 61537261 ps
CPU time 1.67 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 199832 kb
Host smart-e479ffb0-91a7-4ea3-86ba-cbea65b08d2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557491287 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.557491287
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2490728754
Short name T548
Test name
Test status
Simulation time 28317723 ps
CPU time 0.8 seconds
Started Aug 12 05:19:20 PM PDT 24
Finished Aug 12 05:19:21 PM PDT 24
Peak memory 199344 kb
Host smart-25ff3774-a2a8-4733-adae-2b10c948bf6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490728754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2490728754
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2765322765
Short name T578
Test name
Test status
Simulation time 15484361 ps
CPU time 0.61 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 194848 kb
Host smart-540a6763-c8ba-440a-9ec6-5649723b5d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765322765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2765322765
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.476583526
Short name T120
Test name
Test status
Simulation time 75717032 ps
CPU time 1.61 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199840 kb
Host smart-d4e88360-7be6-45ed-bf9d-5b1f073ef131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476583526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.476583526
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1017642293
Short name T614
Test name
Test status
Simulation time 639983054 ps
CPU time 2.71 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 199756 kb
Host smart-b90afa84-83e1-4652-9cc3-f0f1a52762af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017642293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1017642293
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1277678784
Short name T131
Test name
Test status
Simulation time 145981312 ps
CPU time 3.92 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199760 kb
Host smart-ac448958-5e18-442a-b801-c1327d8570c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277678784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1277678784
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4055169842
Short name T634
Test name
Test status
Simulation time 7575443449 ps
CPU time 42.48 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:20:05 PM PDT 24
Peak memory 215564 kb
Host smart-d2eee8cd-f9d2-42a5-99a7-6a625c7db4d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055169842 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4055169842
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2346476643
Short name T619
Test name
Test status
Simulation time 17520507 ps
CPU time 0.79 seconds
Started Aug 12 05:19:21 PM PDT 24
Finished Aug 12 05:19:22 PM PDT 24
Peak memory 199332 kb
Host smart-14605f80-c64b-4aeb-b92d-8842d5017e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346476643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2346476643
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2989458616
Short name T588
Test name
Test status
Simulation time 16609156 ps
CPU time 0.6 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 194896 kb
Host smart-4b3cbb84-6ce8-4d62-912f-4d07e157022d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989458616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2989458616
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1442680371
Short name T645
Test name
Test status
Simulation time 140498976 ps
CPU time 2.22 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199780 kb
Host smart-64796013-812c-465e-8aaf-b106135b9ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442680371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1442680371
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2957170464
Short name T577
Test name
Test status
Simulation time 241620923 ps
CPU time 4 seconds
Started Aug 12 05:19:19 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 199700 kb
Host smart-47f3cc60-1301-41ff-97d0-1f3d5616aa5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957170464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2957170464
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1629684583
Short name T130
Test name
Test status
Simulation time 268462831 ps
CPU time 4.52 seconds
Started Aug 12 05:19:21 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199796 kb
Host smart-f71ab499-665e-4a66-be36-31b117e34d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629684583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1629684583
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2016854205
Short name T582
Test name
Test status
Simulation time 26735437 ps
CPU time 1.57 seconds
Started Aug 12 05:19:23 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 199864 kb
Host smart-42b2b86c-2c4e-4ed3-b79f-7071284d12f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016854205 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2016854205
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.22881306
Short name T627
Test name
Test status
Simulation time 417838274 ps
CPU time 0.96 seconds
Started Aug 12 05:19:32 PM PDT 24
Finished Aug 12 05:19:33 PM PDT 24
Peak memory 199608 kb
Host smart-f6d34d81-a989-49ec-880b-30fabee262b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.22881306
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3137807128
Short name T581
Test name
Test status
Simulation time 39676186 ps
CPU time 0.57 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 194860 kb
Host smart-62d33e3b-5007-483f-a8b8-0fe8a788f858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137807128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3137807128
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1566206699
Short name T112
Test name
Test status
Simulation time 179612079 ps
CPU time 2.22 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:31 PM PDT 24
Peak memory 199784 kb
Host smart-3df63a0c-9259-49a4-8de3-fd46b5758cbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566206699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1566206699
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.383908443
Short name T571
Test name
Test status
Simulation time 183463455 ps
CPU time 2.8 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 199776 kb
Host smart-0b15b08c-bcd5-48af-ba9d-1ddf3d8903e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383908443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.383908443
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3175163632
Short name T648
Test name
Test status
Simulation time 1456278981 ps
CPU time 4.15 seconds
Started Aug 12 05:19:20 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 199744 kb
Host smart-a0eeede0-a798-4995-8fc3-beddda0cfd0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175163632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3175163632
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3474351925
Short name T641
Test name
Test status
Simulation time 78117826 ps
CPU time 1.26 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 199780 kb
Host smart-6f63dde8-8e0a-4479-9775-cecc3478873c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474351925 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3474351925
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2598371605
Short name T654
Test name
Test status
Simulation time 19046107 ps
CPU time 0.94 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 199596 kb
Host smart-37e22fe2-da08-4b88-aea9-9bca953086c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598371605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2598371605
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2189108658
Short name T563
Test name
Test status
Simulation time 11462050 ps
CPU time 0.57 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 194808 kb
Host smart-bf6928a9-c7e1-4286-a10c-e05a447f5a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189108658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2189108658
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3955103755
Short name T639
Test name
Test status
Simulation time 328821145 ps
CPU time 1.75 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:31 PM PDT 24
Peak memory 199780 kb
Host smart-c12b5811-18df-41b2-bef4-176c1796ded1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955103755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3955103755
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.660928360
Short name T644
Test name
Test status
Simulation time 53507255 ps
CPU time 1.51 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199804 kb
Host smart-68055a44-9ab2-4e05-8220-9ad42eb7fad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660928360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.660928360
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.4245329502
Short name T132
Test name
Test status
Simulation time 553336733 ps
CPU time 1.76 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199804 kb
Host smart-237d2f45-9897-4e20-8dbf-91eafe344f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245329502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.4245329502
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.884860933
Short name T553
Test name
Test status
Simulation time 66336922 ps
CPU time 1.11 seconds
Started Aug 12 05:19:23 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 199664 kb
Host smart-4c0a8b4a-bb30-45bd-b4e1-bbe4cf5ab5c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884860933 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.884860933
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1418363756
Short name T97
Test name
Test status
Simulation time 39269465 ps
CPU time 0.69 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 197920 kb
Host smart-8d5624c9-aed6-4b7f-afc1-9e64bd7cd939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418363756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1418363756
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1474278412
Short name T566
Test name
Test status
Simulation time 13470338 ps
CPU time 0.58 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 194796 kb
Host smart-4459ad7b-818a-455a-8198-bf4891bf4960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474278412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1474278412
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4111683222
Short name T621
Test name
Test status
Simulation time 314620056 ps
CPU time 2.13 seconds
Started Aug 12 05:19:21 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 199668 kb
Host smart-5e056c64-e7bb-4828-94dd-c35a37c2a760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111683222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4111683222
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2102361920
Short name T66
Test name
Test status
Simulation time 88713694 ps
CPU time 1.92 seconds
Started Aug 12 05:19:37 PM PDT 24
Finished Aug 12 05:19:40 PM PDT 24
Peak memory 199824 kb
Host smart-6251f19c-598a-4698-aa18-2e80698b79e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102361920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2102361920
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2609110929
Short name T134
Test name
Test status
Simulation time 160728140 ps
CPU time 2.95 seconds
Started Aug 12 05:19:32 PM PDT 24
Finished Aug 12 05:19:35 PM PDT 24
Peak memory 199796 kb
Host smart-e9e68faf-ea3f-40a3-8b92-5290b313ad01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609110929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2609110929
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2822129751
Short name T652
Test name
Test status
Simulation time 285002648 ps
CPU time 1.78 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199796 kb
Host smart-96c0d593-ca8e-4833-aa9d-bbef66b0f291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822129751 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2822129751
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1578418445
Short name T106
Test name
Test status
Simulation time 59403113 ps
CPU time 0.68 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 197748 kb
Host smart-d441f67c-f772-4c15-8902-7a10e598af6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578418445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1578418445
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.80129351
Short name T636
Test name
Test status
Simulation time 38539746 ps
CPU time 0.64 seconds
Started Aug 12 05:19:21 PM PDT 24
Finished Aug 12 05:19:22 PM PDT 24
Peak memory 194980 kb
Host smart-7e32539b-a869-41e7-8cd6-bf55384ebb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80129351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.80129351
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.502345561
Short name T565
Test name
Test status
Simulation time 427399218 ps
CPU time 1.12 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 199736 kb
Host smart-2e42dcc7-f994-4699-9458-12f23ea84a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502345561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.502345561
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1164506359
Short name T544
Test name
Test status
Simulation time 1174968537 ps
CPU time 3.63 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 199672 kb
Host smart-2a10018f-02c0-40b5-a6f6-bf085e32ca2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164506359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1164506359
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2426411582
Short name T61
Test name
Test status
Simulation time 168925871 ps
CPU time 2.82 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 199756 kb
Host smart-d828d71a-343d-4cfe-acb0-d85d50ee4cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426411582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2426411582
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4172948365
Short name T531
Test name
Test status
Simulation time 39417514288 ps
CPU time 576.82 seconds
Started Aug 12 05:19:38 PM PDT 24
Finished Aug 12 05:29:15 PM PDT 24
Peak memory 216400 kb
Host smart-a6a2ea24-6a28-4739-a694-366391f65f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172948365 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4172948365
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2779534228
Short name T107
Test name
Test status
Simulation time 281188220 ps
CPU time 0.91 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199232 kb
Host smart-ff4ba461-c51b-449d-949e-88273a90a0b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779534228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2779534228
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1940118738
Short name T586
Test name
Test status
Simulation time 18487964 ps
CPU time 0.58 seconds
Started Aug 12 05:19:26 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 194924 kb
Host smart-3d09ca3d-06d1-44fe-985a-27ca845485b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940118738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1940118738
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.668767921
Short name T606
Test name
Test status
Simulation time 140619570 ps
CPU time 2.32 seconds
Started Aug 12 05:19:34 PM PDT 24
Finished Aug 12 05:19:37 PM PDT 24
Peak memory 199736 kb
Host smart-351ea030-d59e-48b7-8741-8e51235f94e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668767921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.668767921
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3612989677
Short name T628
Test name
Test status
Simulation time 512958311 ps
CPU time 2.63 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 199752 kb
Host smart-66946716-eda0-433e-9960-371b84028b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612989677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3612989677
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2561578028
Short name T572
Test name
Test status
Simulation time 581830416 ps
CPU time 3.03 seconds
Started Aug 12 05:19:40 PM PDT 24
Finished Aug 12 05:19:43 PM PDT 24
Peak memory 199840 kb
Host smart-bf126d87-a454-48b6-b094-492339c13e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561578028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2561578028
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.328153572
Short name T633
Test name
Test status
Simulation time 35548483 ps
CPU time 2.15 seconds
Started Aug 12 05:19:42 PM PDT 24
Finished Aug 12 05:19:45 PM PDT 24
Peak memory 215488 kb
Host smart-7a6d953b-04d8-4f6d-9066-a67cadf37d7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328153572 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.328153572
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.582260192
Short name T618
Test name
Test status
Simulation time 20391957 ps
CPU time 0.69 seconds
Started Aug 12 05:19:44 PM PDT 24
Finished Aug 12 05:19:45 PM PDT 24
Peak memory 197484 kb
Host smart-e9a99a4e-6075-4255-b60c-0595ea3e5753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582260192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.582260192
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3930200151
Short name T550
Test name
Test status
Simulation time 13326468 ps
CPU time 0.64 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 194904 kb
Host smart-1f038090-38a9-43f3-9977-5a879f759598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930200151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3930200151
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2006071736
Short name T119
Test name
Test status
Simulation time 51294352 ps
CPU time 1.13 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 199716 kb
Host smart-dc1f0cc4-ee77-40a4-a5b9-7e7470588c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006071736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2006071736
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1394321442
Short name T593
Test name
Test status
Simulation time 54088630 ps
CPU time 2.74 seconds
Started Aug 12 05:19:41 PM PDT 24
Finished Aug 12 05:19:44 PM PDT 24
Peak memory 199920 kb
Host smart-e4c41809-21bf-4476-8acd-b88631ae16a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394321442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1394321442
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1677999744
Short name T635
Test name
Test status
Simulation time 149323647 ps
CPU time 2.59 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 208056 kb
Host smart-4a196d39-cd02-4152-8f93-bfe730fb2513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677999744 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1677999744
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3243564109
Short name T625
Test name
Test status
Simulation time 35388501 ps
CPU time 0.88 seconds
Started Aug 12 05:19:30 PM PDT 24
Finished Aug 12 05:19:31 PM PDT 24
Peak memory 199384 kb
Host smart-72fc745f-9cad-43e6-ba33-b19ad4e47609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243564109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3243564109
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2039579255
Short name T638
Test name
Test status
Simulation time 42481641 ps
CPU time 0.63 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 194916 kb
Host smart-8f609081-17e1-4001-8275-0a727fdfe367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039579255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2039579255
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2696714101
Short name T584
Test name
Test status
Simulation time 1349703348 ps
CPU time 2.41 seconds
Started Aug 12 05:19:36 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 199796 kb
Host smart-6b3d0422-62bb-4c34-b99b-6e35918fc599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696714101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2696714101
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3628903366
Short name T579
Test name
Test status
Simulation time 1238381612 ps
CPU time 2.75 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 199788 kb
Host smart-4b37d35a-f9b5-43f0-9462-beccd259f380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628903366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3628903366
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4219833766
Short name T126
Test name
Test status
Simulation time 376680096 ps
CPU time 3.12 seconds
Started Aug 12 05:19:44 PM PDT 24
Finished Aug 12 05:19:47 PM PDT 24
Peak memory 199780 kb
Host smart-f6ffde24-5adb-4953-b790-e403017a7117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219833766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4219833766
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4034660213
Short name T101
Test name
Test status
Simulation time 2369152681 ps
CPU time 9.37 seconds
Started Aug 12 05:19:20 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 199920 kb
Host smart-8963c158-0d47-428b-bf85-313483698709
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034660213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4034660213
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3834521628
Short name T554
Test name
Test status
Simulation time 114276037 ps
CPU time 5.15 seconds
Started Aug 12 05:19:18 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 198528 kb
Host smart-abcffe8f-7d59-4073-828a-b7d3a214ef56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834521628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3834521628
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1556152539
Short name T587
Test name
Test status
Simulation time 353053232 ps
CPU time 0.89 seconds
Started Aug 12 05:19:17 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 199580 kb
Host smart-252edf8f-6fad-4c86-aa14-d0696ce135d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556152539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1556152539
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.97856553
Short name T647
Test name
Test status
Simulation time 207260270 ps
CPU time 3.08 seconds
Started Aug 12 05:19:14 PM PDT 24
Finished Aug 12 05:19:17 PM PDT 24
Peak memory 208152 kb
Host smart-dfe38f74-d676-45cb-8892-8ac1e1c1f619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97856553 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.97856553
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2048211374
Short name T109
Test name
Test status
Simulation time 44231748 ps
CPU time 0.85 seconds
Started Aug 12 05:19:14 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 199552 kb
Host smart-5d3ccb01-e92b-4a3a-9d82-924c99980b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048211374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2048211374
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.406271324
Short name T543
Test name
Test status
Simulation time 158775915 ps
CPU time 0.59 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 195040 kb
Host smart-39878c02-d789-4edf-922e-22b478ebe63f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406271324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.406271324
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.888703646
Short name T115
Test name
Test status
Simulation time 318980212 ps
CPU time 1.12 seconds
Started Aug 12 05:19:16 PM PDT 24
Finished Aug 12 05:19:17 PM PDT 24
Peak memory 199768 kb
Host smart-8bcf6b34-09e0-4650-aeac-ebbd77d43088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888703646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.888703646
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.4094989000
Short name T535
Test name
Test status
Simulation time 253650493 ps
CPU time 4.71 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 199784 kb
Host smart-65fba2e6-d93b-4242-aee2-5a2b792ece36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094989000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.4094989000
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.18545038
Short name T564
Test name
Test status
Simulation time 198770448 ps
CPU time 1.92 seconds
Started Aug 12 05:19:16 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 199796 kb
Host smart-7127a277-8547-4485-a72e-d688dc673e99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.18545038
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2131052005
Short name T630
Test name
Test status
Simulation time 34870395 ps
CPU time 0.61 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 194824 kb
Host smart-77e6abc4-d7ee-4564-bd72-3edb194dc55e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131052005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2131052005
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.706079803
Short name T613
Test name
Test status
Simulation time 48598198 ps
CPU time 0.66 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 194896 kb
Host smart-7a3205c0-e747-4378-87a1-e014a830c5c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706079803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.706079803
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.700852080
Short name T595
Test name
Test status
Simulation time 14444756 ps
CPU time 0.6 seconds
Started Aug 12 05:19:48 PM PDT 24
Finished Aug 12 05:19:48 PM PDT 24
Peak memory 194836 kb
Host smart-655cdd7f-75e3-44d6-bcd7-78b2ed5e3772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700852080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.700852080
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.908224240
Short name T646
Test name
Test status
Simulation time 57206778 ps
CPU time 0.59 seconds
Started Aug 12 05:19:30 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 194964 kb
Host smart-9f082b1a-c58b-4cf6-b9bb-f44f59bc4ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908224240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.908224240
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.176455159
Short name T551
Test name
Test status
Simulation time 11986947 ps
CPU time 0.55 seconds
Started Aug 12 05:19:41 PM PDT 24
Finished Aug 12 05:19:41 PM PDT 24
Peak memory 194788 kb
Host smart-5cf343dc-cd11-4e40-a101-854dad35841f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176455159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.176455159
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1849015801
Short name T596
Test name
Test status
Simulation time 41797399 ps
CPU time 0.59 seconds
Started Aug 12 05:19:35 PM PDT 24
Finished Aug 12 05:19:36 PM PDT 24
Peak memory 194776 kb
Host smart-1bf5b883-c07b-4efe-8182-21848fc77e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849015801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1849015801
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2621104412
Short name T562
Test name
Test status
Simulation time 12571112 ps
CPU time 0.63 seconds
Started Aug 12 05:19:30 PM PDT 24
Finished Aug 12 05:19:31 PM PDT 24
Peak memory 194796 kb
Host smart-a280ae69-fcb5-41b5-a5f2-f29f4eac4bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621104412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2621104412
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4141421782
Short name T629
Test name
Test status
Simulation time 39512453 ps
CPU time 0.57 seconds
Started Aug 12 05:19:46 PM PDT 24
Finished Aug 12 05:19:47 PM PDT 24
Peak memory 194828 kb
Host smart-08940384-9202-4a7e-8022-3c8088c7c806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141421782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4141421782
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.471139562
Short name T620
Test name
Test status
Simulation time 36756978 ps
CPU time 0.55 seconds
Started Aug 12 05:19:33 PM PDT 24
Finished Aug 12 05:19:34 PM PDT 24
Peak memory 194904 kb
Host smart-349db4d6-7946-4ac6-96a5-7e07b1b7b5d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471139562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.471139562
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.233952727
Short name T598
Test name
Test status
Simulation time 14333254 ps
CPU time 0.61 seconds
Started Aug 12 05:19:32 PM PDT 24
Finished Aug 12 05:19:33 PM PDT 24
Peak memory 194832 kb
Host smart-7248890c-3537-41d9-81fc-72d1abe651e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233952727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.233952727
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4008086235
Short name T637
Test name
Test status
Simulation time 108852549 ps
CPU time 3.13 seconds
Started Aug 12 05:19:16 PM PDT 24
Finished Aug 12 05:19:20 PM PDT 24
Peak memory 199740 kb
Host smart-28bf35fa-ca81-4ca7-a886-72e384778559
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008086235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4008086235
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4040782179
Short name T601
Test name
Test status
Simulation time 4359509727 ps
CPU time 16.07 seconds
Started Aug 12 05:19:17 PM PDT 24
Finished Aug 12 05:19:34 PM PDT 24
Peak memory 199904 kb
Host smart-24471d61-354a-456d-bfec-0ef7884e20ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040782179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.4040782179
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1373554072
Short name T110
Test name
Test status
Simulation time 22962612 ps
CPU time 0.76 seconds
Started Aug 12 05:19:14 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 197868 kb
Host smart-d7cfd02e-847d-4066-a45f-22f028caceec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373554072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1373554072
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.940938296
Short name T546
Test name
Test status
Simulation time 50801863414 ps
CPU time 663.24 seconds
Started Aug 12 05:19:36 PM PDT 24
Finished Aug 12 05:30:39 PM PDT 24
Peak memory 215864 kb
Host smart-495db1d0-dfd0-4c97-b2dc-e320e7e82da2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940938296 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.940938296
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1895190030
Short name T631
Test name
Test status
Simulation time 46016819 ps
CPU time 0.79 seconds
Started Aug 12 05:19:23 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 198804 kb
Host smart-69b78172-2cb7-4503-97d4-0a039f55960d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895190030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1895190030
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2158786467
Short name T597
Test name
Test status
Simulation time 222179087 ps
CPU time 0.6 seconds
Started Aug 12 05:19:13 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 194824 kb
Host smart-f406dd68-f517-4bbb-9cca-6a7fbab5be75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158786467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2158786467
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.747401391
Short name T116
Test name
Test status
Simulation time 232861345 ps
CPU time 2.29 seconds
Started Aug 12 05:19:25 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 199824 kb
Host smart-199cfe8b-a30c-4874-90a2-38d5c25e3368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747401391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.747401391
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.392058661
Short name T590
Test name
Test status
Simulation time 261779175 ps
CPU time 2.38 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 199680 kb
Host smart-cb8ff73e-a07a-40c4-a776-b106483d0919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392058661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.392058661
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.955685040
Short name T62
Test name
Test status
Simulation time 507231786 ps
CPU time 3.79 seconds
Started Aug 12 05:19:20 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 199808 kb
Host smart-adba71d9-a2da-4f51-875a-e8cbfb367541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955685040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.955685040
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3890523583
Short name T603
Test name
Test status
Simulation time 11840670 ps
CPU time 0.58 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 194852 kb
Host smart-a59b067e-1f55-452a-b01f-423979c43897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890523583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3890523583
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1336430598
Short name T600
Test name
Test status
Simulation time 38645830 ps
CPU time 0.61 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 194880 kb
Host smart-68e2fdd0-a07c-430b-a35d-cd2292c8fe3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336430598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1336430598
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3419721189
Short name T589
Test name
Test status
Simulation time 149264341 ps
CPU time 0.59 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 194832 kb
Host smart-b1c1440a-511d-4916-8ecb-1a6e6b183a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419721189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3419721189
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3971155238
Short name T580
Test name
Test status
Simulation time 23647501 ps
CPU time 0.57 seconds
Started Aug 12 05:19:44 PM PDT 24
Finished Aug 12 05:19:44 PM PDT 24
Peak memory 194912 kb
Host smart-613d50fe-0750-45e3-a3a2-fb6c5e0c081b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971155238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3971155238
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1983474397
Short name T537
Test name
Test status
Simulation time 45579102 ps
CPU time 0.58 seconds
Started Aug 12 05:19:47 PM PDT 24
Finished Aug 12 05:19:48 PM PDT 24
Peak memory 194828 kb
Host smart-5c3bf966-19ef-4890-8349-5cc0aa081b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983474397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1983474397
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3926936349
Short name T568
Test name
Test status
Simulation time 17780049 ps
CPU time 0.58 seconds
Started Aug 12 05:19:36 PM PDT 24
Finished Aug 12 05:19:37 PM PDT 24
Peak memory 194872 kb
Host smart-28e2b1e1-e5fe-483e-9a66-2c3a18ac18d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926936349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3926936349
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.850889583
Short name T623
Test name
Test status
Simulation time 13245839 ps
CPU time 0.59 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 194912 kb
Host smart-fe7c67e2-76af-4310-9150-d5e3c716f790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850889583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.850889583
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2023562271
Short name T615
Test name
Test status
Simulation time 17861906 ps
CPU time 0.58 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 194928 kb
Host smart-19628d37-1f9e-4325-91d7-ab061a6414a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023562271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2023562271
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2416190310
Short name T552
Test name
Test status
Simulation time 46621863 ps
CPU time 0.59 seconds
Started Aug 12 05:19:30 PM PDT 24
Finished Aug 12 05:19:31 PM PDT 24
Peak memory 194880 kb
Host smart-f0f64be6-0f83-4437-9f80-4bbe28425d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416190310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2416190310
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1267013396
Short name T538
Test name
Test status
Simulation time 182994345 ps
CPU time 0.62 seconds
Started Aug 12 05:19:45 PM PDT 24
Finished Aug 12 05:19:46 PM PDT 24
Peak memory 194916 kb
Host smart-f4c65cf6-3524-40ea-8296-ea6a01de1386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267013396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1267013396
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2349299884
Short name T102
Test name
Test status
Simulation time 546738485 ps
CPU time 9.18 seconds
Started Aug 12 05:19:32 PM PDT 24
Finished Aug 12 05:19:41 PM PDT 24
Peak memory 199608 kb
Host smart-a5e8beb4-5eb8-489e-95b1-a83aa7babc75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349299884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2349299884
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2444182114
Short name T100
Test name
Test status
Simulation time 313754310 ps
CPU time 14.58 seconds
Started Aug 12 05:19:20 PM PDT 24
Finished Aug 12 05:19:34 PM PDT 24
Peak memory 199744 kb
Host smart-c029561f-fd72-4ded-9254-592ad48710f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444182114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2444182114
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3285192985
Short name T108
Test name
Test status
Simulation time 19777410 ps
CPU time 0.99 seconds
Started Aug 12 05:19:13 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 199440 kb
Host smart-dc297ec7-7875-456f-ac4a-3079bd104dad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285192985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3285192985
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2763468363
Short name T536
Test name
Test status
Simulation time 278919068 ps
CPU time 2 seconds
Started Aug 12 05:19:11 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 199752 kb
Host smart-34660729-ad08-4fab-a686-63459f000a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763468363 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2763468363
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3775873304
Short name T103
Test name
Test status
Simulation time 373229413 ps
CPU time 0.92 seconds
Started Aug 12 05:19:26 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 199240 kb
Host smart-6c8ea3af-17cb-4fd9-8b53-09c56a1e565a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775873304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3775873304
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.691666912
Short name T556
Test name
Test status
Simulation time 14340316 ps
CPU time 0.68 seconds
Started Aug 12 05:19:18 PM PDT 24
Finished Aug 12 05:19:19 PM PDT 24
Peak memory 194860 kb
Host smart-a69f8396-3dfb-4dd6-ad80-a08b12007b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691666912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.691666912
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2371672981
Short name T113
Test name
Test status
Simulation time 121734779 ps
CPU time 2.39 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199684 kb
Host smart-aef44dff-82d2-497e-a96e-f194f8dd6015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371672981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2371672981
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.624812112
Short name T575
Test name
Test status
Simulation time 406561894 ps
CPU time 2.48 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:17 PM PDT 24
Peak memory 199812 kb
Host smart-a0b3ceb7-1ad8-413b-a616-74625f33786d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624812112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.624812112
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.34219166
Short name T640
Test name
Test status
Simulation time 340894129 ps
CPU time 4.34 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 199808 kb
Host smart-85eab816-44ac-4af1-9fe3-30a8bbc62fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34219166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.34219166
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3516522640
Short name T558
Test name
Test status
Simulation time 75630603 ps
CPU time 0.62 seconds
Started Aug 12 05:19:40 PM PDT 24
Finished Aug 12 05:19:40 PM PDT 24
Peak memory 194836 kb
Host smart-d518d537-3184-4063-811b-e9d925b01655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516522640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3516522640
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.4094251217
Short name T608
Test name
Test status
Simulation time 20785009 ps
CPU time 0.63 seconds
Started Aug 12 05:19:40 PM PDT 24
Finished Aug 12 05:19:40 PM PDT 24
Peak memory 195016 kb
Host smart-f909ccc9-cbcc-4ec6-954b-de6446e12056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094251217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4094251217
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2390505603
Short name T643
Test name
Test status
Simulation time 60915516 ps
CPU time 0.57 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 194804 kb
Host smart-14fd41c1-fe10-4891-9864-2970adb443cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390505603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2390505603
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3165271145
Short name T585
Test name
Test status
Simulation time 18452107 ps
CPU time 0.58 seconds
Started Aug 12 05:19:37 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 194904 kb
Host smart-11e6e107-e4b0-45a3-b874-688439081fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165271145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3165271145
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.832936720
Short name T610
Test name
Test status
Simulation time 46152736 ps
CPU time 0.62 seconds
Started Aug 12 05:19:37 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 194956 kb
Host smart-7eb87e5a-b04b-4e8f-a34b-a1b106f7307f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832936720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.832936720
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.59156451
Short name T545
Test name
Test status
Simulation time 63567528 ps
CPU time 0.58 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 194900 kb
Host smart-1c8bcc88-8289-475d-bfff-bd02475c85d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59156451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.59156451
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.425395478
Short name T612
Test name
Test status
Simulation time 56469822 ps
CPU time 0.57 seconds
Started Aug 12 05:19:46 PM PDT 24
Finished Aug 12 05:19:47 PM PDT 24
Peak memory 194804 kb
Host smart-5d4b3b71-d1a4-4954-84b7-921ba9c6a74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425395478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.425395478
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4273739363
Short name T599
Test name
Test status
Simulation time 45671887 ps
CPU time 0.63 seconds
Started Aug 12 05:19:41 PM PDT 24
Finished Aug 12 05:19:41 PM PDT 24
Peak memory 194828 kb
Host smart-603180f8-e6c6-4e04-918f-72ccd1cd5d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273739363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4273739363
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2092126749
Short name T547
Test name
Test status
Simulation time 50432210 ps
CPU time 0.61 seconds
Started Aug 12 05:19:43 PM PDT 24
Finished Aug 12 05:19:44 PM PDT 24
Peak memory 194872 kb
Host smart-a5323199-0e0e-40d7-9d86-13a6adfc995b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092126749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2092126749
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2245509439
Short name T642
Test name
Test status
Simulation time 31419335 ps
CPU time 0.62 seconds
Started Aug 12 05:19:40 PM PDT 24
Finished Aug 12 05:19:41 PM PDT 24
Peak memory 195064 kb
Host smart-76ee1b94-aa69-4c9b-82b8-4f1e0689ba98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245509439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2245509439
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.177781840
Short name T604
Test name
Test status
Simulation time 680769799 ps
CPU time 1.27 seconds
Started Aug 12 05:19:18 PM PDT 24
Finished Aug 12 05:19:19 PM PDT 24
Peak memory 198972 kb
Host smart-b4171945-e70e-423e-b791-d0cf81c3bd82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177781840 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.177781840
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2702492758
Short name T583
Test name
Test status
Simulation time 43538768 ps
CPU time 0.82 seconds
Started Aug 12 05:19:14 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 199556 kb
Host smart-c2778b1e-366a-46ba-918e-4aa0c7b1a809
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702492758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2702492758
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2755781351
Short name T561
Test name
Test status
Simulation time 51094477 ps
CPU time 0.62 seconds
Started Aug 12 05:19:16 PM PDT 24
Finished Aug 12 05:19:17 PM PDT 24
Peak memory 194968 kb
Host smart-82bae445-0e7f-4220-a3d9-b95ae847f921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755781351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2755781351
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3699760685
Short name T114
Test name
Test status
Simulation time 395244772 ps
CPU time 1.7 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:17 PM PDT 24
Peak memory 199788 kb
Host smart-f2103c11-4304-423c-883b-eac6cee32de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699760685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3699760685
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1749823978
Short name T82
Test name
Test status
Simulation time 49984092 ps
CPU time 2.53 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 199736 kb
Host smart-cce6c055-da49-4da8-9c22-0d509c760aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749823978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1749823978
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2773479445
Short name T127
Test name
Test status
Simulation time 965317379 ps
CPU time 4.37 seconds
Started Aug 12 05:19:21 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 199784 kb
Host smart-8ea48984-b0c2-4f41-abe1-9c0f865cc53d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773479445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2773479445
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1202118198
Short name T570
Test name
Test status
Simulation time 40876381 ps
CPU time 1.12 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199680 kb
Host smart-bf675265-3f3d-41d9-a1ae-34de2cb0257d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202118198 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1202118198
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2083227091
Short name T616
Test name
Test status
Simulation time 18272846 ps
CPU time 0.72 seconds
Started Aug 12 05:19:28 PM PDT 24
Finished Aug 12 05:19:29 PM PDT 24
Peak memory 197784 kb
Host smart-73ee79f3-9782-4370-bd91-0c06f816fb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083227091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2083227091
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2690434213
Short name T555
Test name
Test status
Simulation time 69581102 ps
CPU time 0.56 seconds
Started Aug 12 05:19:26 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 194820 kb
Host smart-c759b096-363a-40f8-ae2f-0adf76368bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690434213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2690434213
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2114349866
Short name T632
Test name
Test status
Simulation time 80328336 ps
CPU time 1.76 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:33 PM PDT 24
Peak memory 199780 kb
Host smart-0252207c-ca0b-4b6d-87bf-a88635da1d57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114349866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2114349866
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2722118578
Short name T591
Test name
Test status
Simulation time 634092814 ps
CPU time 2.15 seconds
Started Aug 12 05:19:13 PM PDT 24
Finished Aug 12 05:19:16 PM PDT 24
Peak memory 199736 kb
Host smart-01946ec9-b0ff-477b-ae77-71e0e47b48c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722118578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2722118578
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1626715264
Short name T617
Test name
Test status
Simulation time 170283637 ps
CPU time 3.19 seconds
Started Aug 12 05:19:16 PM PDT 24
Finished Aug 12 05:19:19 PM PDT 24
Peak memory 199676 kb
Host smart-f2b1e175-66b6-4604-a148-f189779c7248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626715264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1626715264
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3026950978
Short name T559
Test name
Test status
Simulation time 125556220 ps
CPU time 2.32 seconds
Started Aug 12 05:19:23 PM PDT 24
Finished Aug 12 05:19:26 PM PDT 24
Peak memory 199844 kb
Host smart-340a3bb6-84ed-468a-93ca-222c05fbc882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026950978 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3026950978
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4071322049
Short name T649
Test name
Test status
Simulation time 30110671 ps
CPU time 0.92 seconds
Started Aug 12 05:19:17 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 199608 kb
Host smart-5b00af72-5cec-4645-8d09-f8bac5f784f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071322049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4071322049
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2290513452
Short name T605
Test name
Test status
Simulation time 37340822 ps
CPU time 0.59 seconds
Started Aug 12 05:19:18 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 194272 kb
Host smart-c950c469-4932-4855-982f-d55c306fd713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290513452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2290513452
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1824280445
Short name T117
Test name
Test status
Simulation time 144312284 ps
CPU time 1.53 seconds
Started Aug 12 05:19:14 PM PDT 24
Finished Aug 12 05:19:16 PM PDT 24
Peak memory 199728 kb
Host smart-49f72bb0-98cf-4f77-b594-c7a26c46468c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824280445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1824280445
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2953259118
Short name T569
Test name
Test status
Simulation time 47740429 ps
CPU time 2.34 seconds
Started Aug 12 05:19:15 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 199752 kb
Host smart-90e17682-f54c-4b64-b2df-680359972fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953259118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2953259118
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.199275005
Short name T542
Test name
Test status
Simulation time 376177557 ps
CPU time 1.78 seconds
Started Aug 12 05:19:16 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 199748 kb
Host smart-aa7bf605-42d3-417f-a46e-289385392617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199275005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.199275005
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3129089715
Short name T541
Test name
Test status
Simulation time 303942826 ps
CPU time 2.28 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:31 PM PDT 24
Peak memory 216116 kb
Host smart-a82d9b2f-aef4-4280-bacf-1b7ce55f3e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129089715 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3129089715
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2282031432
Short name T105
Test name
Test status
Simulation time 29567571 ps
CPU time 0.93 seconds
Started Aug 12 05:19:27 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 199560 kb
Host smart-d454cadb-018d-493d-be07-5b9b3a7488c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282031432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2282031432
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2302817638
Short name T567
Test name
Test status
Simulation time 16183188 ps
CPU time 0.61 seconds
Started Aug 12 05:19:24 PM PDT 24
Finished Aug 12 05:19:25 PM PDT 24
Peak memory 194840 kb
Host smart-e48e3c72-e90f-49c7-90f2-5ee7a4f0b034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302817638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2302817638
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3657273750
Short name T111
Test name
Test status
Simulation time 214949069 ps
CPU time 1.22 seconds
Started Aug 12 05:19:31 PM PDT 24
Finished Aug 12 05:19:33 PM PDT 24
Peak memory 199632 kb
Host smart-02927f4f-1259-402b-9189-69d5849a8e55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657273750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3657273750
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3946030636
Short name T532
Test name
Test status
Simulation time 208687086 ps
CPU time 2.26 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:32 PM PDT 24
Peak memory 199756 kb
Host smart-b4beb4f6-eb96-4a3e-9e33-ff01914e8e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946030636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3946030636
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3844592383
Short name T133
Test name
Test status
Simulation time 672917179 ps
CPU time 3.01 seconds
Started Aug 12 05:19:32 PM PDT 24
Finished Aug 12 05:19:35 PM PDT 24
Peak memory 199732 kb
Host smart-7c50a9b8-48ff-4a40-b154-e9565cf6cd42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844592383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3844592383
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2832237038
Short name T539
Test name
Test status
Simulation time 35883029 ps
CPU time 1.11 seconds
Started Aug 12 05:19:26 PM PDT 24
Finished Aug 12 05:19:28 PM PDT 24
Peak memory 199672 kb
Host smart-5bd40b17-af3c-4180-ba97-5ae10e3ab9d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832237038 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2832237038
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3431115288
Short name T104
Test name
Test status
Simulation time 17053250 ps
CPU time 0.93 seconds
Started Aug 12 05:19:29 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 199556 kb
Host smart-59e68882-a90a-465e-8935-9b8bf264d371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431115288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3431115288
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1447962029
Short name T607
Test name
Test status
Simulation time 33899407 ps
CPU time 0.58 seconds
Started Aug 12 05:19:33 PM PDT 24
Finished Aug 12 05:19:34 PM PDT 24
Peak memory 194968 kb
Host smart-e2b1470c-e5bd-4f66-ada4-ac0a9b214ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447962029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1447962029
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.471818592
Short name T549
Test name
Test status
Simulation time 140551052 ps
CPU time 1.18 seconds
Started Aug 12 05:19:22 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 199724 kb
Host smart-fddfdf81-8843-4a91-a1d9-22d0c6a07b03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471818592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.471818592
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4055510143
Short name T602
Test name
Test status
Simulation time 31931697 ps
CPU time 1.49 seconds
Started Aug 12 05:19:23 PM PDT 24
Finished Aug 12 05:19:24 PM PDT 24
Peak memory 199832 kb
Host smart-db1cdddb-b16b-4b06-be0d-3e87ebc1eceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055510143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4055510143
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2374842640
Short name T373
Test name
Test status
Simulation time 38490996 ps
CPU time 0.57 seconds
Started Aug 12 05:23:18 PM PDT 24
Finished Aug 12 05:23:19 PM PDT 24
Peak memory 196668 kb
Host smart-edeb182c-72da-4cfa-9905-2e8308e9adab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374842640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2374842640
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3327884746
Short name T301
Test name
Test status
Simulation time 138341972 ps
CPU time 5.52 seconds
Started Aug 12 05:23:14 PM PDT 24
Finished Aug 12 05:23:20 PM PDT 24
Peak memory 200740 kb
Host smart-3c340e89-3d8a-46b1-9f7c-5aadd603d391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327884746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3327884746
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3208286299
Short name T190
Test name
Test status
Simulation time 3428021582 ps
CPU time 46.37 seconds
Started Aug 12 05:23:27 PM PDT 24
Finished Aug 12 05:24:14 PM PDT 24
Peak memory 200796 kb
Host smart-59768b37-9d64-495a-a745-37e8e7096098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208286299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3208286299
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1199037582
Short name T160
Test name
Test status
Simulation time 5062779331 ps
CPU time 947.66 seconds
Started Aug 12 05:23:27 PM PDT 24
Finished Aug 12 05:39:15 PM PDT 24
Peak memory 725776 kb
Host smart-8fc06d27-4bbd-4b77-847d-49b3b2997c2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199037582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1199037582
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1018670824
Short name T432
Test name
Test status
Simulation time 9215666665 ps
CPU time 134.19 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 200804 kb
Host smart-f2c73208-bdcb-4e44-adc7-34c35d7831f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018670824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1018670824
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2496244172
Short name T36
Test name
Test status
Simulation time 2851436132 ps
CPU time 78.39 seconds
Started Aug 12 05:23:25 PM PDT 24
Finished Aug 12 05:24:44 PM PDT 24
Peak memory 199256 kb
Host smart-9d37cefb-3534-4cc3-aba0-8b69ba090da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496244172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2496244172
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3386306778
Short name T368
Test name
Test status
Simulation time 166416699 ps
CPU time 1.58 seconds
Started Aug 12 05:23:15 PM PDT 24
Finished Aug 12 05:23:17 PM PDT 24
Peak memory 200716 kb
Host smart-ecb9ae39-78ac-45a4-af2b-803226cd0fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386306778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3386306778
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2907198780
Short name T364
Test name
Test status
Simulation time 26531954013 ps
CPU time 910.46 seconds
Started Aug 12 05:23:14 PM PDT 24
Finished Aug 12 05:38:25 PM PDT 24
Peak memory 718408 kb
Host smart-85b8a965-72c7-457e-98c6-b2c7713395d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907198780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2907198780
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3576797972
Short name T69
Test name
Test status
Simulation time 4464116012 ps
CPU time 47.27 seconds
Started Aug 12 05:23:15 PM PDT 24
Finished Aug 12 05:24:02 PM PDT 24
Peak memory 200728 kb
Host smart-a8d9a765-e0f2-4069-8893-160167b2d041
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3576797972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3576797972
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1903646999
Short name T496
Test name
Test status
Simulation time 4210892814 ps
CPU time 61.28 seconds
Started Aug 12 05:23:24 PM PDT 24
Finished Aug 12 05:24:26 PM PDT 24
Peak memory 200804 kb
Host smart-78706c27-1f0d-4c73-b8f7-8664ea5453cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1903646999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1903646999
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3158368070
Short name T516
Test name
Test status
Simulation time 4193645557 ps
CPU time 70.46 seconds
Started Aug 12 05:23:31 PM PDT 24
Finished Aug 12 05:24:42 PM PDT 24
Peak memory 200836 kb
Host smart-312254a4-3c49-448c-b32c-560d2ed64605
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3158368070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3158368070
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1538552134
Short name T416
Test name
Test status
Simulation time 140683096502 ps
CPU time 687.15 seconds
Started Aug 12 05:23:43 PM PDT 24
Finished Aug 12 05:35:16 PM PDT 24
Peak memory 200808 kb
Host smart-9242683d-ffcc-42e9-a0ea-b0b112906841
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1538552134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1538552134
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.4188264754
Short name T444
Test name
Test status
Simulation time 770887448410 ps
CPU time 2607.31 seconds
Started Aug 12 05:23:11 PM PDT 24
Finished Aug 12 06:06:39 PM PDT 24
Peak memory 216144 kb
Host smart-6067cfc5-a933-474f-a44e-94702f381fcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4188264754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.4188264754
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1100816008
Short name T354
Test name
Test status
Simulation time 546609106511 ps
CPU time 2483.15 seconds
Started Aug 12 05:23:18 PM PDT 24
Finished Aug 12 06:04:47 PM PDT 24
Peak memory 217160 kb
Host smart-74630b54-9058-4a30-85b0-84215dadce2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1100816008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1100816008
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4177803218
Short name T430
Test name
Test status
Simulation time 35209513334 ps
CPU time 103.44 seconds
Started Aug 12 05:23:30 PM PDT 24
Finished Aug 12 05:25:14 PM PDT 24
Peak memory 200784 kb
Host smart-18d46daf-a011-4b19-83c1-d2dc00a65d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177803218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4177803218
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3183973197
Short name T393
Test name
Test status
Simulation time 15107847 ps
CPU time 0.57 seconds
Started Aug 12 05:23:21 PM PDT 24
Finished Aug 12 05:23:22 PM PDT 24
Peak memory 195584 kb
Host smart-dfc26a8e-5122-46fc-9454-82bdbf099203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183973197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3183973197
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.96412554
Short name T165
Test name
Test status
Simulation time 479678267 ps
CPU time 25.3 seconds
Started Aug 12 05:23:40 PM PDT 24
Finished Aug 12 05:24:06 PM PDT 24
Peak memory 200824 kb
Host smart-06c75db8-860e-4517-a233-83436429da71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96412554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.96412554
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3729027219
Short name T481
Test name
Test status
Simulation time 9679227074 ps
CPU time 949.91 seconds
Started Aug 12 05:23:18 PM PDT 24
Finished Aug 12 05:39:08 PM PDT 24
Peak memory 743376 kb
Host smart-877afc89-33f3-47fb-845f-aca677b91f55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729027219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3729027219
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1974692329
Short name T419
Test name
Test status
Simulation time 2611794126 ps
CPU time 142.08 seconds
Started Aug 12 05:23:16 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 200840 kb
Host smart-cf76d227-bbc7-4325-a296-3e8d31eecee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974692329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1974692329
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2354759370
Short name T509
Test name
Test status
Simulation time 5862913011 ps
CPU time 78.14 seconds
Started Aug 12 05:23:24 PM PDT 24
Finished Aug 12 05:24:43 PM PDT 24
Peak memory 200764 kb
Host smart-6094be65-39a7-4354-a1a5-1e1f71eb827f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354759370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2354759370
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1459034669
Short name T49
Test name
Test status
Simulation time 100919480 ps
CPU time 1.08 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:23:24 PM PDT 24
Peak memory 220180 kb
Host smart-14746018-0633-4098-b66b-782d18d3905f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459034669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1459034669
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.177103167
Short name T472
Test name
Test status
Simulation time 370888817 ps
CPU time 1.42 seconds
Started Aug 12 05:23:19 PM PDT 24
Finished Aug 12 05:23:20 PM PDT 24
Peak memory 200816 kb
Host smart-a9c3ac9e-9667-451c-9825-b76100824553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177103167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.177103167
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2115077103
Short name T463
Test name
Test status
Simulation time 113517111330 ps
CPU time 2484.39 seconds
Started Aug 12 05:23:24 PM PDT 24
Finished Aug 12 06:04:48 PM PDT 24
Peak memory 796224 kb
Host smart-f6a69a00-4675-4a94-9e68-c427625f0576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115077103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2115077103
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1466760945
Short name T14
Test name
Test status
Simulation time 2980834893 ps
CPU time 139.25 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:25:57 PM PDT 24
Peak memory 217328 kb
Host smart-23882bb1-6e09-4f29-be95-d906de8ead29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466760945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1466760945
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.721134747
Short name T315
Test name
Test status
Simulation time 3300692282 ps
CPU time 68.72 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:24:31 PM PDT 24
Peak memory 200816 kb
Host smart-089ad200-ab1a-47ee-b32e-c6442e83eb96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=721134747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.721134747
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2350441186
Short name T487
Test name
Test status
Simulation time 1676019881 ps
CPU time 51.21 seconds
Started Aug 12 05:23:30 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 200788 kb
Host smart-b45bea46-42f2-425d-8d96-1636c3c57f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2350441186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2350441186
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.674698360
Short name T157
Test name
Test status
Simulation time 29044881467 ps
CPU time 86.98 seconds
Started Aug 12 05:23:29 PM PDT 24
Finished Aug 12 05:24:56 PM PDT 24
Peak memory 200824 kb
Host smart-fbf4bdc7-6beb-491a-aa86-884c20754a82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=674698360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.674698360
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2827673341
Short name T289
Test name
Test status
Simulation time 44138617609 ps
CPU time 2311.12 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 06:01:54 PM PDT 24
Peak memory 216852 kb
Host smart-3a9537e7-39dd-4bf3-ad2a-3e259105ceaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2827673341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2827673341
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2315766359
Short name T495
Test name
Test status
Simulation time 217780491675 ps
CPU time 2694.86 seconds
Started Aug 12 05:23:19 PM PDT 24
Finished Aug 12 06:08:15 PM PDT 24
Peak memory 216112 kb
Host smart-0c7860c2-6947-4974-9ea4-8ab43a96436d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2315766359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2315766359
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3662126978
Short name T446
Test name
Test status
Simulation time 496486255 ps
CPU time 21.58 seconds
Started Aug 12 05:23:27 PM PDT 24
Finished Aug 12 05:23:49 PM PDT 24
Peak memory 200728 kb
Host smart-e0b9837b-237f-464f-b2ef-8202fb870df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662126978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3662126978
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.627353526
Short name T90
Test name
Test status
Simulation time 13557383 ps
CPU time 0.58 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:23:39 PM PDT 24
Peak memory 196736 kb
Host smart-7df6dfab-076e-4204-88bb-45cc00bf9573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627353526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.627353526
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.497145521
Short name T398
Test name
Test status
Simulation time 1357048764 ps
CPU time 31.27 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:24:16 PM PDT 24
Peak memory 200776 kb
Host smart-6da51408-1055-4052-8688-257e37484aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497145521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.497145521
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.78712518
Short name T500
Test name
Test status
Simulation time 2689913051 ps
CPU time 33.74 seconds
Started Aug 12 05:23:40 PM PDT 24
Finished Aug 12 05:24:14 PM PDT 24
Peak memory 200812 kb
Host smart-09b747fd-0a50-4d3e-9377-a0c9e5636ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78712518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.78712518
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2162537647
Short name T523
Test name
Test status
Simulation time 12853834 ps
CPU time 0.66 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:23:48 PM PDT 24
Peak memory 198956 kb
Host smart-56364fba-1ca7-4e85-bf10-7fcbcc905de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162537647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2162537647
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.72836945
Short name T367
Test name
Test status
Simulation time 2507788323 ps
CPU time 44.27 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:24:29 PM PDT 24
Peak memory 200760 kb
Host smart-59c522e8-2818-4e2a-a03d-85f725c4821c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72836945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.72836945
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3959036153
Short name T249
Test name
Test status
Simulation time 3940260429 ps
CPU time 17.21 seconds
Started Aug 12 05:23:36 PM PDT 24
Finished Aug 12 05:23:54 PM PDT 24
Peak memory 200784 kb
Host smart-fb2e3d92-2205-42d7-b81c-169119b17e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959036153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3959036153
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2196059143
Short name T530
Test name
Test status
Simulation time 490711472 ps
CPU time 8.27 seconds
Started Aug 12 05:23:37 PM PDT 24
Finished Aug 12 05:23:45 PM PDT 24
Peak memory 200716 kb
Host smart-fba6c9f4-99f0-4b64-a8de-a04a59689bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196059143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2196059143
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2085156896
Short name T194
Test name
Test status
Simulation time 87981475135 ps
CPU time 187.06 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:26:58 PM PDT 24
Peak memory 200832 kb
Host smart-2ef2a7ab-1d31-4247-a5ef-763bfee4fae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085156896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2085156896
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.729307331
Short name T253
Test name
Test status
Simulation time 2324764012 ps
CPU time 99.9 seconds
Started Aug 12 05:23:43 PM PDT 24
Finished Aug 12 05:25:23 PM PDT 24
Peak memory 200616 kb
Host smart-070b3741-2242-4772-83a0-1b63a1f2a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729307331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.729307331
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1303074306
Short name T347
Test name
Test status
Simulation time 10663951 ps
CPU time 0.59 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:23:47 PM PDT 24
Peak memory 195696 kb
Host smart-334ddc7e-0024-4f89-b24a-3f5307c2dfd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303074306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1303074306
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3466054123
Short name T17
Test name
Test status
Simulation time 15552644183 ps
CPU time 73.3 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:24:55 PM PDT 24
Peak memory 200884 kb
Host smart-9a6a3e02-d40b-4a05-8eb2-749e5085e62a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466054123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3466054123
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2811193108
Short name T420
Test name
Test status
Simulation time 4508754032 ps
CPU time 63.31 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:24:37 PM PDT 24
Peak memory 200980 kb
Host smart-b74a34c2-de02-4588-b817-f7cc832e73c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811193108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2811193108
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.697175553
Short name T270
Test name
Test status
Simulation time 8805732208 ps
CPU time 754.95 seconds
Started Aug 12 05:23:39 PM PDT 24
Finished Aug 12 05:36:14 PM PDT 24
Peak memory 714740 kb
Host smart-d8e2a96d-958b-4db4-a038-371e38009f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697175553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.697175553
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1803118569
Short name T212
Test name
Test status
Simulation time 5558652594 ps
CPU time 45.9 seconds
Started Aug 12 05:23:36 PM PDT 24
Finished Aug 12 05:24:22 PM PDT 24
Peak memory 200756 kb
Host smart-1f39a6e1-9e45-4df9-bc19-c47ac12398f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803118569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1803118569
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3052838075
Short name T206
Test name
Test status
Simulation time 12827655584 ps
CPU time 154.77 seconds
Started Aug 12 05:23:34 PM PDT 24
Finished Aug 12 05:26:09 PM PDT 24
Peak memory 200808 kb
Host smart-e9303e46-c3f4-4aea-8519-b68b5ac9740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052838075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3052838075
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3508286907
Short name T168
Test name
Test status
Simulation time 39545608 ps
CPU time 1.48 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:24:06 PM PDT 24
Peak memory 200628 kb
Host smart-fd29e037-95d0-4332-91f4-78c3a1a936a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508286907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3508286907
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2091185483
Short name T123
Test name
Test status
Simulation time 4033345120 ps
CPU time 100.26 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:25:38 PM PDT 24
Peak memory 200880 kb
Host smart-1882afc1-acfa-4825-b697-165a96dbed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091185483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2091185483
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.311840700
Short name T526
Test name
Test status
Simulation time 59711125 ps
CPU time 0.56 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:23:48 PM PDT 24
Peak memory 196528 kb
Host smart-88a68978-25c9-4a8b-9716-5a359fd7eeb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311840700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.311840700
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3597650934
Short name T41
Test name
Test status
Simulation time 9276235325 ps
CPU time 97.06 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:24:59 PM PDT 24
Peak memory 201004 kb
Host smart-9249df0f-1b51-407a-9b9d-0a787c08a413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597650934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3597650934
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2199891563
Short name T27
Test name
Test status
Simulation time 7415507490 ps
CPU time 25.11 seconds
Started Aug 12 05:24:11 PM PDT 24
Finished Aug 12 05:24:36 PM PDT 24
Peak memory 200692 kb
Host smart-9e7b8b23-bd16-4863-9c5d-1bae05eb9f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199891563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2199891563
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3591800383
Short name T344
Test name
Test status
Simulation time 3440154930 ps
CPU time 561.73 seconds
Started Aug 12 05:23:44 PM PDT 24
Finished Aug 12 05:33:05 PM PDT 24
Peak memory 671452 kb
Host smart-758c0790-c9df-43ea-a156-9ad129bff1ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591800383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3591800383
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1346422264
Short name T167
Test name
Test status
Simulation time 8242629559 ps
CPU time 100.66 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:25:23 PM PDT 24
Peak memory 200844 kb
Host smart-c8c0febb-dcc9-4ef7-9f1c-d069783b2c8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346422264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1346422264
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1845745330
Short name T507
Test name
Test status
Simulation time 2450907397 ps
CPU time 8.44 seconds
Started Aug 12 05:23:34 PM PDT 24
Finished Aug 12 05:23:43 PM PDT 24
Peak memory 200756 kb
Host smart-1e049b59-f0bb-4aeb-bf60-c0b34a259510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845745330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1845745330
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1043071287
Short name T316
Test name
Test status
Simulation time 877563301 ps
CPU time 9.98 seconds
Started Aug 12 05:23:24 PM PDT 24
Finished Aug 12 05:23:34 PM PDT 24
Peak memory 200776 kb
Host smart-37358368-15cb-4cb7-bd08-8cb04d66aca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043071287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1043071287
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3049875448
Short name T381
Test name
Test status
Simulation time 72128072205 ps
CPU time 1711.08 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:52:22 PM PDT 24
Peak memory 680340 kb
Host smart-e2ca57d7-656a-4413-9563-7a2f9bc963ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049875448 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3049875448
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2037485280
Short name T275
Test name
Test status
Simulation time 13455091279 ps
CPU time 58.04 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:24:20 PM PDT 24
Peak memory 200760 kb
Host smart-070113d6-5359-4cc8-adb6-9d0ef776ce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037485280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2037485280
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1098193226
Short name T238
Test name
Test status
Simulation time 14606747 ps
CPU time 0.58 seconds
Started Aug 12 05:23:32 PM PDT 24
Finished Aug 12 05:23:33 PM PDT 24
Peak memory 196368 kb
Host smart-bffccd88-c21c-46cd-81e9-ec1f608e845d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098193226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1098193226
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.449939427
Short name T251
Test name
Test status
Simulation time 1000048859 ps
CPU time 13.99 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:23:47 PM PDT 24
Peak memory 200700 kb
Host smart-0aa1f725-9c13-4b07-b6de-0c27c282212c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449939427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.449939427
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.170670125
Short name T457
Test name
Test status
Simulation time 1006890015 ps
CPU time 13.77 seconds
Started Aug 12 05:23:52 PM PDT 24
Finished Aug 12 05:24:06 PM PDT 24
Peak memory 200788 kb
Host smart-6e4f89b8-e00e-4028-ab40-447402c07f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170670125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.170670125
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1413503085
Short name T242
Test name
Test status
Simulation time 5885699162 ps
CPU time 1425.41 seconds
Started Aug 12 05:23:34 PM PDT 24
Finished Aug 12 05:47:19 PM PDT 24
Peak memory 758300 kb
Host smart-230cfdf9-da3e-4d4f-a471-1931dad51e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413503085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1413503085
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1783272598
Short name T504
Test name
Test status
Simulation time 1863898795 ps
CPU time 50.49 seconds
Started Aug 12 05:23:29 PM PDT 24
Finished Aug 12 05:24:20 PM PDT 24
Peak memory 200444 kb
Host smart-4e597d9a-2d1e-45f1-9e22-d686a7e86abd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783272598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1783272598
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3583938787
Short name T38
Test name
Test status
Simulation time 1743293089 ps
CPU time 101.8 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:25:24 PM PDT 24
Peak memory 200752 kb
Host smart-1894047d-96d2-49b2-b349-022280f20afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583938787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3583938787
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2536515608
Short name T380
Test name
Test status
Simulation time 205514073 ps
CPU time 3.7 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:23:49 PM PDT 24
Peak memory 200800 kb
Host smart-6a442e94-4cc3-4af8-b3f1-d02c71ad4d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536515608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2536515608
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.300370994
Short name T74
Test name
Test status
Simulation time 480337412557 ps
CPU time 4709.73 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 06:42:16 PM PDT 24
Peak memory 872116 kb
Host smart-ced8b53a-2952-44b0-9c9f-46a0081d4f78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300370994 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.300370994
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3568747845
Short name T291
Test name
Test status
Simulation time 61987423515 ps
CPU time 143.95 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:26:17 PM PDT 24
Peak memory 200824 kb
Host smart-2b3c322c-9dc0-4b20-9ebe-6cd066b6c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568747845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3568747845
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2418823078
Short name T440
Test name
Test status
Simulation time 39883040 ps
CPU time 0.6 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:23:48 PM PDT 24
Peak memory 196700 kb
Host smart-264227fa-1861-4109-bb99-a73a4096b1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418823078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2418823078
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1793931962
Short name T229
Test name
Test status
Simulation time 5189457282 ps
CPU time 78.32 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 200832 kb
Host smart-56fed6fc-f462-41a7-ac2c-b7e4736a279a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793931962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1793931962
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.977612207
Short name T144
Test name
Test status
Simulation time 3093242658 ps
CPU time 27.99 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:24:37 PM PDT 24
Peak memory 200832 kb
Host smart-b0df3e06-4a80-4f57-851e-b7d380cad3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977612207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.977612207
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2311074488
Short name T525
Test name
Test status
Simulation time 1404907328 ps
CPU time 127.78 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:26:23 PM PDT 24
Peak memory 400064 kb
Host smart-52691829-b46d-436c-a641-cc2a6da538b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311074488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2311074488
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.7769235
Short name T527
Test name
Test status
Simulation time 112437908977 ps
CPU time 184.02 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:27:07 PM PDT 24
Peak memory 200796 kb
Host smart-fbc83cf1-ddef-402f-b102-c03b349662b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7769235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.7769235
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.83367960
Short name T84
Test name
Test status
Simulation time 2970014135 ps
CPU time 84.12 seconds
Started Aug 12 05:24:22 PM PDT 24
Finished Aug 12 05:25:46 PM PDT 24
Peak memory 200768 kb
Host smart-555decfc-77b4-4e23-ae4b-f0f850c3757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83367960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.83367960
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1392463712
Short name T328
Test name
Test status
Simulation time 259996573 ps
CPU time 11.62 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:24:00 PM PDT 24
Peak memory 200748 kb
Host smart-42c798f8-3d0d-42a4-b793-14773a1b994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392463712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1392463712
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2083530017
Short name T399
Test name
Test status
Simulation time 45056827026 ps
CPU time 1062.01 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:41:27 PM PDT 24
Peak memory 727100 kb
Host smart-48dbd29a-1065-401e-8e53-9fa4007e2dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083530017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2083530017
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1179050523
Short name T338
Test name
Test status
Simulation time 13584145443 ps
CPU time 18.13 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:24:37 PM PDT 24
Peak memory 200632 kb
Host smart-1b0e2a58-27c9-44db-a9e2-78b69d3c1e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179050523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1179050523
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3311649095
Short name T172
Test name
Test status
Simulation time 4644116043 ps
CPU time 59.26 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:24:48 PM PDT 24
Peak memory 200872 kb
Host smart-03e80dbd-3ee2-43d9-902d-05e82c9bce40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311649095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3311649095
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2766095179
Short name T243
Test name
Test status
Simulation time 334302174 ps
CPU time 6.56 seconds
Started Aug 12 05:23:44 PM PDT 24
Finished Aug 12 05:23:51 PM PDT 24
Peak memory 200828 kb
Host smart-7138bec4-5a76-442e-a78a-a6f4e56f8707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766095179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2766095179
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3665542524
Short name T227
Test name
Test status
Simulation time 16083909844 ps
CPU time 1724.83 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:52:42 PM PDT 24
Peak memory 779700 kb
Host smart-d90d8a9a-33b5-4638-8149-3d45cb9d0933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665542524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3665542524
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3901886467
Short name T320
Test name
Test status
Simulation time 8714643100 ps
CPU time 157.8 seconds
Started Aug 12 05:23:43 PM PDT 24
Finished Aug 12 05:26:20 PM PDT 24
Peak memory 200852 kb
Host smart-18b11c95-f2d5-4fe2-ba85-13977aea83fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901886467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3901886467
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.243697947
Short name T77
Test name
Test status
Simulation time 346646599 ps
CPU time 4.91 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:12 PM PDT 24
Peak memory 200700 kb
Host smart-696fc956-54b2-42fd-8526-74f447771e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243697947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.243697947
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3253479185
Short name T305
Test name
Test status
Simulation time 721623829 ps
CPU time 6.08 seconds
Started Aug 12 05:23:51 PM PDT 24
Finished Aug 12 05:23:58 PM PDT 24
Peak memory 200760 kb
Host smart-8d7f7f64-70be-49ab-95cf-246cff93dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253479185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3253479185
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1002922853
Short name T250
Test name
Test status
Simulation time 108094681653 ps
CPU time 363.19 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:29:58 PM PDT 24
Peak memory 209028 kb
Host smart-3e82fde3-f45d-4313-a65d-3691967deaf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002922853 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1002922853
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2018813782
Short name T355
Test name
Test status
Simulation time 4769212279 ps
CPU time 80.75 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 200776 kb
Host smart-75935d23-f47c-4b75-a7a5-73e6e9dad720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018813782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2018813782
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2923475982
Short name T233
Test name
Test status
Simulation time 96605585 ps
CPU time 0.6 seconds
Started Aug 12 05:23:37 PM PDT 24
Finished Aug 12 05:23:38 PM PDT 24
Peak memory 196728 kb
Host smart-79cd2945-20a6-45f0-9b3b-94d5f74377e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923475982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2923475982
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3457690633
Short name T59
Test name
Test status
Simulation time 673504264 ps
CPU time 34.62 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:24:29 PM PDT 24
Peak memory 200796 kb
Host smart-3d5ad7e2-b818-4a29-9ab9-e67b8f949245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457690633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3457690633
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1929280786
Short name T395
Test name
Test status
Simulation time 1039087853 ps
CPU time 13.33 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:09 PM PDT 24
Peak memory 200648 kb
Host smart-10244d0e-946b-4be5-a986-25c4679b74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929280786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1929280786
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3022364796
Short name T3
Test name
Test status
Simulation time 21133124937 ps
CPU time 844.16 seconds
Started Aug 12 05:24:00 PM PDT 24
Finished Aug 12 05:38:04 PM PDT 24
Peak memory 509068 kb
Host smart-44c565c5-e5e2-4b89-9576-e13eca7c0e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022364796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3022364796
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3166557965
Short name T158
Test name
Test status
Simulation time 8747750849 ps
CPU time 60.66 seconds
Started Aug 12 05:23:52 PM PDT 24
Finished Aug 12 05:24:52 PM PDT 24
Peak memory 200892 kb
Host smart-46bccc45-805c-41ed-82e7-f572f278da9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166557965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3166557965
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1995716649
Short name T161
Test name
Test status
Simulation time 5486588788 ps
CPU time 143.98 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:26:17 PM PDT 24
Peak memory 200820 kb
Host smart-2cbdde0e-0a07-40f6-97d4-a0ede5834c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995716649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1995716649
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3511640758
Short name T520
Test name
Test status
Simulation time 278205215 ps
CPU time 12.86 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:24:16 PM PDT 24
Peak memory 200772 kb
Host smart-35b3630c-7c82-4f60-a907-759bccd0fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511640758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3511640758
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1464743765
Short name T480
Test name
Test status
Simulation time 2153566464 ps
CPU time 48.71 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:24:36 PM PDT 24
Peak memory 200832 kb
Host smart-01dd62fd-1cb4-4300-878d-8bc3270cad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464743765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1464743765
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2520711692
Short name T514
Test name
Test status
Simulation time 15806575 ps
CPU time 0.58 seconds
Started Aug 12 05:24:06 PM PDT 24
Finished Aug 12 05:24:07 PM PDT 24
Peak memory 195628 kb
Host smart-b757a378-b50b-4194-82d8-232ff81a4c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520711692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2520711692
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3028465587
Short name T20
Test name
Test status
Simulation time 1512038827 ps
CPU time 82.84 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 200764 kb
Host smart-fc228ef6-fae3-438f-8d41-18005a6da722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028465587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3028465587
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1935958927
Short name T25
Test name
Test status
Simulation time 1397482929 ps
CPU time 30.31 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:24:20 PM PDT 24
Peak memory 200672 kb
Host smart-f5b70790-3f9d-42fd-9f61-9f52039b3833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935958927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1935958927
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2861595871
Short name T294
Test name
Test status
Simulation time 12356440637 ps
CPU time 1242.8 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 05:44:29 PM PDT 24
Peak memory 769356 kb
Host smart-092b0e57-aaae-43ce-bc9d-4d9dba1e34ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861595871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2861595871
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.376328431
Short name T299
Test name
Test status
Simulation time 7586357612 ps
CPU time 212.72 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:27:42 PM PDT 24
Peak memory 200816 kb
Host smart-9d6a601a-8674-4c57-b448-a38ad57406dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376328431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.376328431
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.635758299
Short name T58
Test name
Test status
Simulation time 2087117598 ps
CPU time 24.66 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:24:18 PM PDT 24
Peak memory 200716 kb
Host smart-b7f4c2d6-75aa-47e9-bb74-4cc37305832d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635758299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.635758299
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.464013405
Short name T324
Test name
Test status
Simulation time 363811462 ps
CPU time 3.25 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 05:23:49 PM PDT 24
Peak memory 200780 kb
Host smart-a668872f-74fd-4c6c-94a1-33538b72fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464013405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.464013405
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.414432975
Short name T311
Test name
Test status
Simulation time 35850185474 ps
CPU time 1143.98 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:43:06 PM PDT 24
Peak memory 731444 kb
Host smart-955b0412-909a-4fca-882a-61fb7e8fd647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414432975 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.414432975
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3858130784
Short name T297
Test name
Test status
Simulation time 8583309724 ps
CPU time 64.15 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:25:06 PM PDT 24
Peak memory 200828 kb
Host smart-717eacc3-f24c-4ba5-845b-bfe8b9bca8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858130784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3858130784
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3975381797
Short name T164
Test name
Test status
Simulation time 36239861 ps
CPU time 0.58 seconds
Started Aug 12 05:23:43 PM PDT 24
Finished Aug 12 05:23:44 PM PDT 24
Peak memory 195704 kb
Host smart-ff06c1a9-2a08-408c-af89-1a150f52f6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975381797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3975381797
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.160803575
Short name T351
Test name
Test status
Simulation time 1467754295 ps
CPU time 88.87 seconds
Started Aug 12 05:23:59 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 200716 kb
Host smart-64099f0b-67f0-476f-8073-259f333ea250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160803575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.160803575
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1236185377
Short name T331
Test name
Test status
Simulation time 172125991 ps
CPU time 2.18 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:23:51 PM PDT 24
Peak memory 200680 kb
Host smart-0ace54b0-240a-497b-9c73-3e35282845c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236185377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1236185377
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2903334924
Short name T169
Test name
Test status
Simulation time 5823622663 ps
CPU time 1026.75 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:41:01 PM PDT 24
Peak memory 697568 kb
Host smart-62996047-f693-433a-ab8d-b8ea58609ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903334924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2903334924
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.55227831
Short name T43
Test name
Test status
Simulation time 49650278566 ps
CPU time 159.19 seconds
Started Aug 12 05:23:35 PM PDT 24
Finished Aug 12 05:26:15 PM PDT 24
Peak memory 200968 kb
Host smart-28b40ef8-ec2f-4be7-9c3c-fbded0fc9fbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55227831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.55227831
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3160474842
Short name T286
Test name
Test status
Simulation time 10952104459 ps
CPU time 32.63 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:24:31 PM PDT 24
Peak memory 200836 kb
Host smart-031aca4e-27ba-420a-a6be-2c2066cee74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160474842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3160474842
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.253933500
Short name T89
Test name
Test status
Simulation time 10847957434 ps
CPU time 10.19 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:24:03 PM PDT 24
Peak memory 200876 kb
Host smart-b6c34e8e-9eb0-4a6b-938a-1ae6059a026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253933500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.253933500
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1660498554
Short name T312
Test name
Test status
Simulation time 26174976197 ps
CPU time 2069.18 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:58:26 PM PDT 24
Peak memory 731968 kb
Host smart-bf88bced-1853-4af0-ae43-1f12003a58d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660498554 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1660498554
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2048166674
Short name T280
Test name
Test status
Simulation time 11186509730 ps
CPU time 49.44 seconds
Started Aug 12 05:23:51 PM PDT 24
Finished Aug 12 05:24:41 PM PDT 24
Peak memory 200768 kb
Host smart-801a230f-e681-4d4d-a8ce-23277a67b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048166674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2048166674
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3542519511
Short name T483
Test name
Test status
Simulation time 54029630 ps
CPU time 0.56 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:23:46 PM PDT 24
Peak memory 196348 kb
Host smart-544443b6-35ac-4d51-b59d-3d6458088433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542519511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3542519511
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2225788341
Short name T219
Test name
Test status
Simulation time 3141167933 ps
CPU time 51.42 seconds
Started Aug 12 05:23:39 PM PDT 24
Finished Aug 12 05:24:31 PM PDT 24
Peak memory 200856 kb
Host smart-a9dd2683-a265-45a3-aa11-5207b35d81ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225788341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2225788341
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1968471546
Short name T4
Test name
Test status
Simulation time 1003083195 ps
CPU time 14.9 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:24:05 PM PDT 24
Peak memory 200768 kb
Host smart-4cbc549f-77e5-4936-9d7e-0d29f8ffec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968471546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1968471546
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.279021274
Short name T281
Test name
Test status
Simulation time 9439764131 ps
CPU time 231.83 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:27:41 PM PDT 24
Peak memory 599752 kb
Host smart-94d8e4db-c394-4b58-8452-f7b67f047753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279021274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.279021274
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4226644490
Short name T384
Test name
Test status
Simulation time 5626789350 ps
CPU time 73.13 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:25:14 PM PDT 24
Peak memory 200836 kb
Host smart-5b6086ea-bd0b-458e-b71f-22eb17ca3f6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226644490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4226644490
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1768505444
Short name T268
Test name
Test status
Simulation time 27079385691 ps
CPU time 106.05 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:25:43 PM PDT 24
Peak memory 200748 kb
Host smart-b8993358-6c84-4e3e-adf3-3a5f80e49cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768505444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1768505444
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3487154426
Short name T512
Test name
Test status
Simulation time 553941188 ps
CPU time 4.14 seconds
Started Aug 12 05:23:51 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 200708 kb
Host smart-413644c2-148d-425d-8f37-ca27e97373c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487154426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3487154426
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2305724237
Short name T278
Test name
Test status
Simulation time 19852904317 ps
CPU time 1643.44 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:51:12 PM PDT 24
Peak memory 648624 kb
Host smart-f80633e7-1dd1-4019-9901-11245005d5a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305724237 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2305724237
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1413821804
Short name T497
Test name
Test status
Simulation time 3567278668 ps
CPU time 47.08 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:24:50 PM PDT 24
Peak memory 200796 kb
Host smart-0d629fb9-9590-48ff-8659-4f5192cc706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413821804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1413821804
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3744883434
Short name T30
Test name
Test status
Simulation time 10646358 ps
CPU time 0.56 seconds
Started Aug 12 05:23:14 PM PDT 24
Finished Aug 12 05:23:15 PM PDT 24
Peak memory 195680 kb
Host smart-2b457bb1-313a-4fd4-9842-150d49ce9d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744883434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3744883434
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3209758156
Short name T494
Test name
Test status
Simulation time 3901260838 ps
CPU time 57.97 seconds
Started Aug 12 05:23:28 PM PDT 24
Finished Aug 12 05:24:26 PM PDT 24
Peak memory 200884 kb
Host smart-2bb51933-890e-4e45-8eac-70a95118de58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209758156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3209758156
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3020037750
Short name T140
Test name
Test status
Simulation time 382605339 ps
CPU time 20.9 seconds
Started Aug 12 05:23:20 PM PDT 24
Finished Aug 12 05:23:41 PM PDT 24
Peak memory 200756 kb
Host smart-fdccee76-c680-4103-a80b-7009de4291ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020037750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3020037750
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1379192468
Short name T230
Test name
Test status
Simulation time 486835886 ps
CPU time 51.28 seconds
Started Aug 12 05:23:19 PM PDT 24
Finished Aug 12 05:24:11 PM PDT 24
Peak memory 323768 kb
Host smart-ad10a564-03ab-47ee-88c7-d1debedcbe90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379192468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1379192468
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2594239635
Short name T70
Test name
Test status
Simulation time 34372288739 ps
CPU time 136.9 seconds
Started Aug 12 05:23:20 PM PDT 24
Finished Aug 12 05:25:37 PM PDT 24
Peak memory 200740 kb
Host smart-be1fdcf0-c4a8-4fcc-b706-b24bc67a68ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594239635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2594239635
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2511744070
Short name T202
Test name
Test status
Simulation time 928549931 ps
CPU time 40.2 seconds
Started Aug 12 05:23:20 PM PDT 24
Finished Aug 12 05:24:00 PM PDT 24
Peak memory 200740 kb
Host smart-98bb635a-24f7-40f2-b4b3-e2cf7c974d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511744070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2511744070
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1468638204
Short name T52
Test name
Test status
Simulation time 117791378 ps
CPU time 0.91 seconds
Started Aug 12 05:23:19 PM PDT 24
Finished Aug 12 05:23:20 PM PDT 24
Peak memory 219080 kb
Host smart-59b51906-16b9-4586-ad33-619dab3f375b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468638204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1468638204
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.618321971
Short name T528
Test name
Test status
Simulation time 471416755 ps
CPU time 10.75 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:23:44 PM PDT 24
Peak memory 200644 kb
Host smart-ed4368d8-1b14-4ce4-b81b-cb392b577a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618321971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.618321971
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1530948604
Short name T236
Test name
Test status
Simulation time 19236061010 ps
CPU time 906.53 seconds
Started Aug 12 05:23:28 PM PDT 24
Finished Aug 12 05:38:34 PM PDT 24
Peak memory 643752 kb
Host smart-626ffe18-34dd-477a-9dd9-bdaffa5c525f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530948604 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1530948604
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1019263488
Short name T309
Test name
Test status
Simulation time 7519152277 ps
CPU time 68.51 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:24:31 PM PDT 24
Peak memory 200856 kb
Host smart-ea16f53d-b1c2-4755-a314-df210a167a48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1019263488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1019263488
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.2750261422
Short name T193
Test name
Test status
Simulation time 5216771439 ps
CPU time 58.65 seconds
Started Aug 12 05:23:37 PM PDT 24
Finished Aug 12 05:24:35 PM PDT 24
Peak memory 200868 kb
Host smart-16baead8-a05b-4595-9ef7-b3673d642f58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2750261422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2750261422
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1035898697
Short name T19
Test name
Test status
Simulation time 4888869508 ps
CPU time 71.36 seconds
Started Aug 12 05:23:30 PM PDT 24
Finished Aug 12 05:24:41 PM PDT 24
Peak memory 200692 kb
Host smart-9ff11940-dc64-4b3a-8e94-974e26b432ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1035898697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1035898697
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.204562279
Short name T307
Test name
Test status
Simulation time 36531111797 ps
CPU time 623.8 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:33:47 PM PDT 24
Peak memory 200764 kb
Host smart-d3ef13fd-4180-4ea6-a16a-f5feb4992b95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=204562279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.204562279
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3311226381
Short name T518
Test name
Test status
Simulation time 748634225755 ps
CPU time 2579.4 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 06:06:42 PM PDT 24
Peak memory 216800 kb
Host smart-074bc68a-adb1-4f86-b788-8d93f5290198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3311226381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3311226381
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2847452288
Short name T37
Test name
Test status
Simulation time 182210770375 ps
CPU time 2353.92 seconds
Started Aug 12 05:23:28 PM PDT 24
Finished Aug 12 06:02:43 PM PDT 24
Peak memory 216560 kb
Host smart-f6662811-b59b-4a5c-abf9-f35459a051ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2847452288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2847452288
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1588833011
Short name T241
Test name
Test status
Simulation time 6749529170 ps
CPU time 117.7 seconds
Started Aug 12 05:23:11 PM PDT 24
Finished Aug 12 05:25:09 PM PDT 24
Peak memory 200824 kb
Host smart-cbf32777-dba2-4f70-96c9-98e75d8fcb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588833011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1588833011
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.47655695
Short name T54
Test name
Test status
Simulation time 13560724 ps
CPU time 0.58 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:23:58 PM PDT 24
Peak memory 196656 kb
Host smart-4ed80c9c-2080-496f-b158-290856722ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47655695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.47655695
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1294898730
Short name T459
Test name
Test status
Simulation time 1565836121 ps
CPU time 16.19 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:24 PM PDT 24
Peak memory 200812 kb
Host smart-19350c2e-d19f-4afc-80ff-52fcdfe94174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294898730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1294898730
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3698775993
Short name T5
Test name
Test status
Simulation time 3496707289 ps
CPU time 30.93 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:24:19 PM PDT 24
Peak memory 200880 kb
Host smart-ce6c30a4-373b-4d56-88c1-377d6d037a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698775993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3698775993
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.87482031
Short name T55
Test name
Test status
Simulation time 7652530058 ps
CPU time 1165.34 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:43:23 PM PDT 24
Peak memory 724860 kb
Host smart-51f29426-bb86-4d54-bc40-232add4e6ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87482031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.87482031
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.657552402
Short name T271
Test name
Test status
Simulation time 27376661671 ps
CPU time 118.12 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 200832 kb
Host smart-57526e75-45e1-42fd-b3ae-83362ed2a963
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657552402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.657552402
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2340137299
Short name T502
Test name
Test status
Simulation time 10900121652 ps
CPU time 133.64 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:26:10 PM PDT 24
Peak memory 208988 kb
Host smart-91b657bb-83f9-44f2-a44b-43f5a208a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340137299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2340137299
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.178549881
Short name T329
Test name
Test status
Simulation time 135657800 ps
CPU time 1.78 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 05:23:48 PM PDT 24
Peak memory 200796 kb
Host smart-d7694c7d-5f8d-44b7-97d3-0ac0a0afbd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178549881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.178549881
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1174969217
Short name T72
Test name
Test status
Simulation time 46874219671 ps
CPU time 979.55 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:40:04 PM PDT 24
Peak memory 650152 kb
Host smart-c47600d0-6b6b-4262-b9eb-16d70693e7ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174969217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1174969217
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1149302875
Short name T175
Test name
Test status
Simulation time 1253952158 ps
CPU time 33.53 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:30 PM PDT 24
Peak memory 200732 kb
Host smart-7763d938-2251-4ed7-aae2-02a8fa574ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149302875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1149302875
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.677805312
Short name T273
Test name
Test status
Simulation time 13941912 ps
CPU time 0.58 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 196352 kb
Host smart-f4026eea-7a0d-4786-b5c1-c7a03cc26666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677805312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.677805312
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3570113401
Short name T454
Test name
Test status
Simulation time 7429074398 ps
CPU time 106.83 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:25:41 PM PDT 24
Peak memory 200828 kb
Host smart-1cf50c90-00ad-47a9-bcd3-380bf642634d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570113401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3570113401
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.347189031
Short name T259
Test name
Test status
Simulation time 4006837465 ps
CPU time 18.33 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:24:07 PM PDT 24
Peak memory 200892 kb
Host smart-bbfe89ae-a1cc-4f30-b94a-2da53f452a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347189031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.347189031
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4155864630
Short name T350
Test name
Test status
Simulation time 17865809488 ps
CPU time 832.38 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:37:48 PM PDT 24
Peak memory 753896 kb
Host smart-e8007b97-196d-4b31-988d-44809771cd57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155864630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4155864630
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.826990732
Short name T439
Test name
Test status
Simulation time 1808398502 ps
CPU time 24.24 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:24:34 PM PDT 24
Peak memory 200596 kb
Host smart-f8261e04-9df9-4ce1-991f-20a240b62617
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826990732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.826990732
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2307335452
Short name T322
Test name
Test status
Simulation time 2505098150 ps
CPU time 142.02 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:26:37 PM PDT 24
Peak memory 200812 kb
Host smart-5bce7678-5673-40d5-998c-835ab6f4a701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307335452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2307335452
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2108094721
Short name T191
Test name
Test status
Simulation time 1071139600 ps
CPU time 3.18 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:23:45 PM PDT 24
Peak memory 200628 kb
Host smart-25f14bfc-cdda-4b0a-94df-695606756a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108094721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2108094721
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3082086984
Short name T517
Test name
Test status
Simulation time 268400199705 ps
CPU time 870.41 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:38:35 PM PDT 24
Peak memory 217168 kb
Host smart-ed6a36cd-1dc0-4241-928b-67dec56e9878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082086984 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3082086984
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3158439436
Short name T7
Test name
Test status
Simulation time 44953280051 ps
CPU time 121.71 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:25:58 PM PDT 24
Peak memory 200972 kb
Host smart-4e08fb05-c993-471d-80ec-ec1a2895aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158439436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3158439436
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3393807490
Short name T402
Test name
Test status
Simulation time 13058606 ps
CPU time 0.6 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:23:58 PM PDT 24
Peak memory 196360 kb
Host smart-b4ed20e2-db29-43ad-9148-41f18135dbcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393807490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3393807490
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2862415664
Short name T371
Test name
Test status
Simulation time 524663985 ps
CPU time 15.03 seconds
Started Aug 12 05:23:51 PM PDT 24
Finished Aug 12 05:24:06 PM PDT 24
Peak memory 200672 kb
Host smart-44f5a8e1-0cb7-4a78-8ea1-923242796346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862415664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2862415664
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2474725049
Short name T146
Test name
Test status
Simulation time 242586847 ps
CPU time 11.22 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:24:05 PM PDT 24
Peak memory 200672 kb
Host smart-8838b8f3-46a7-43cf-99f6-1d13bb580af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474725049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2474725049
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.488826441
Short name T204
Test name
Test status
Simulation time 374192762 ps
CPU time 41.09 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:24:40 PM PDT 24
Peak memory 256392 kb
Host smart-556d698c-bb1d-4bbf-9cc0-5bee844fbb76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488826441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.488826441
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3592855685
Short name T276
Test name
Test status
Simulation time 1088465749 ps
CPU time 68.17 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:25:03 PM PDT 24
Peak memory 200564 kb
Host smart-54340f4f-4d0b-4dd0-9520-39918045675a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592855685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3592855685
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1035381136
Short name T498
Test name
Test status
Simulation time 15019527144 ps
CPU time 205.73 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:27:15 PM PDT 24
Peak memory 200804 kb
Host smart-e2b0a35a-5385-47e3-8960-b34cd9baf05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035381136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1035381136
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.837960816
Short name T269
Test name
Test status
Simulation time 487763035 ps
CPU time 11.45 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:23:59 PM PDT 24
Peak memory 200784 kb
Host smart-e29db8b0-d846-49a4-8a53-6ff2f382a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837960816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.837960816
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2919839656
Short name T73
Test name
Test status
Simulation time 111269174828 ps
CPU time 109.73 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 216444 kb
Host smart-278f44ad-3afb-4a9d-bc3d-a57d5c47c501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919839656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2919839656
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1298606509
Short name T313
Test name
Test status
Simulation time 44130599569 ps
CPU time 145.01 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:26:24 PM PDT 24
Peak memory 200896 kb
Host smart-cad0f571-eb58-48c4-8896-2f30655746be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298606509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1298606509
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3767932961
Short name T306
Test name
Test status
Simulation time 14353626 ps
CPU time 0.6 seconds
Started Aug 12 05:23:44 PM PDT 24
Finished Aug 12 05:23:44 PM PDT 24
Peak memory 196604 kb
Host smart-faa75e2b-4a12-45dd-84f8-0ec001f4acbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767932961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3767932961
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.130617478
Short name T462
Test name
Test status
Simulation time 6619480951 ps
CPU time 80.67 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 200692 kb
Host smart-0300f7c4-62e5-4f2f-9ed7-11739cf93eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130617478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.130617478
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1456316788
Short name T78
Test name
Test status
Simulation time 1869266299 ps
CPU time 4.09 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:23:54 PM PDT 24
Peak memory 200904 kb
Host smart-2e588f4d-6463-4478-adab-6bc36dd2c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456316788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1456316788
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.871910946
Short name T476
Test name
Test status
Simulation time 3651885259 ps
CPU time 386.83 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:30:14 PM PDT 24
Peak memory 679876 kb
Host smart-c378317c-7656-4615-9926-1b4e74aadd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871910946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.871910946
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2169831267
Short name T208
Test name
Test status
Simulation time 10287326723 ps
CPU time 129.51 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:26:29 PM PDT 24
Peak memory 200804 kb
Host smart-3d0ccbd9-2c60-4f1d-b2a3-825e273cd6ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169831267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2169831267
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2824270310
Short name T379
Test name
Test status
Simulation time 8758818046 ps
CPU time 124.61 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:26:03 PM PDT 24
Peak memory 201044 kb
Host smart-a0d7cd9f-e6d8-45d5-b8f6-2b42d50393ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824270310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2824270310
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2584041964
Short name T200
Test name
Test status
Simulation time 19565674 ps
CPU time 1.07 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:23:51 PM PDT 24
Peak memory 200544 kb
Host smart-5641bdab-fdc2-42be-8374-37d36d37c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584041964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2584041964
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3240551042
Short name T406
Test name
Test status
Simulation time 15055093273 ps
CPU time 319.6 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:29:10 PM PDT 24
Peak memory 347936 kb
Host smart-27893ad4-c95d-4677-9940-773a2b5b3d3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240551042 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3240551042
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.25128622
Short name T94
Test name
Test status
Simulation time 2902374650 ps
CPU time 76.86 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:25:06 PM PDT 24
Peak memory 200800 kb
Host smart-51258fec-af0c-43b7-a61e-aa81988e3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25128622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.25128622
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3294084440
Short name T187
Test name
Test status
Simulation time 23024298 ps
CPU time 0.57 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:23:49 PM PDT 24
Peak memory 196360 kb
Host smart-6183f52d-4052-4429-88bf-faa8ef8caecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294084440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3294084440
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1166245347
Short name T222
Test name
Test status
Simulation time 1634659670 ps
CPU time 82.11 seconds
Started Aug 12 05:23:51 PM PDT 24
Finished Aug 12 05:25:13 PM PDT 24
Peak memory 200744 kb
Host smart-4991cee2-e744-4ec3-901a-81e4cf938af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166245347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1166245347
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.83275223
Short name T143
Test name
Test status
Simulation time 951419433 ps
CPU time 50.14 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:24:39 PM PDT 24
Peak memory 200756 kb
Host smart-242a1322-564a-469c-b46e-d189779c1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83275223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.83275223
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2432706950
Short name T287
Test name
Test status
Simulation time 1497009328 ps
CPU time 232.44 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:27:51 PM PDT 24
Peak memory 577744 kb
Host smart-6740f1f2-f8ed-4651-a6a6-9e819875200d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432706950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2432706950
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3514966974
Short name T411
Test name
Test status
Simulation time 59267944173 ps
CPU time 190.91 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:27:01 PM PDT 24
Peak memory 200808 kb
Host smart-53b5685d-0a1e-488a-83e4-c04cfb0bc73f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514966974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3514966974
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2959036732
Short name T201
Test name
Test status
Simulation time 23463207093 ps
CPU time 79.88 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 200824 kb
Host smart-a30a057d-3563-4d97-8867-36aa2698ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959036732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2959036732
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.591352629
Short name T335
Test name
Test status
Simulation time 1106018653 ps
CPU time 14.23 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:24:03 PM PDT 24
Peak memory 200800 kb
Host smart-ef464bf7-0511-4bdf-85ed-12cfd5e167df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591352629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.591352629
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.351353232
Short name T240
Test name
Test status
Simulation time 1536108455 ps
CPU time 69.47 seconds
Started Aug 12 05:24:03 PM PDT 24
Finished Aug 12 05:25:12 PM PDT 24
Peak memory 200752 kb
Host smart-78a2eb17-b940-4a5c-8eb9-ce7590dad728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351353232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.351353232
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4202950782
Short name T266
Test name
Test status
Simulation time 13655509 ps
CPU time 0.62 seconds
Started Aug 12 05:23:51 PM PDT 24
Finished Aug 12 05:23:51 PM PDT 24
Peak memory 196748 kb
Host smart-897ab0f1-6a95-4cfd-97c9-c760a9f19b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202950782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4202950782
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3449298803
Short name T317
Test name
Test status
Simulation time 922880697 ps
CPU time 49.04 seconds
Started Aug 12 05:24:03 PM PDT 24
Finished Aug 12 05:24:52 PM PDT 24
Peak memory 200656 kb
Host smart-6ac3fa1f-031f-421d-8006-c2356fc2ef90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449298803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3449298803
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3592723823
Short name T422
Test name
Test status
Simulation time 8562515482 ps
CPU time 43.16 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:24:40 PM PDT 24
Peak memory 217256 kb
Host smart-6a5d9a65-8ce9-4601-abc3-e53e371e6168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592723823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3592723823
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.697779348
Short name T503
Test name
Test status
Simulation time 5729296329 ps
CPU time 876.4 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 05:38:25 PM PDT 24
Peak memory 721396 kb
Host smart-dab869d9-534d-4e61-b327-e1d5c318addc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697779348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.697779348
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2452965805
Short name T234
Test name
Test status
Simulation time 10664258990 ps
CPU time 172.48 seconds
Started Aug 12 05:24:06 PM PDT 24
Finished Aug 12 05:26:59 PM PDT 24
Peak memory 200824 kb
Host smart-a14c022c-6827-4ffe-8282-73d995eb4a82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452965805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2452965805
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.317215639
Short name T244
Test name
Test status
Simulation time 9104346034 ps
CPU time 122.92 seconds
Started Aug 12 05:24:03 PM PDT 24
Finished Aug 12 05:26:06 PM PDT 24
Peak memory 200812 kb
Host smart-88818ab4-de5e-4834-9015-2d21637979db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317215639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.317215639
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3661850720
Short name T345
Test name
Test status
Simulation time 255718072 ps
CPU time 5.32 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:12 PM PDT 24
Peak memory 200676 kb
Host smart-7f2d9467-a236-4dc4-b346-288951357115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661850720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3661850720
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3276590138
Short name T76
Test name
Test status
Simulation time 102890771913 ps
CPU time 2899.07 seconds
Started Aug 12 05:23:49 PM PDT 24
Finished Aug 12 06:12:09 PM PDT 24
Peak memory 760284 kb
Host smart-6fad595e-8f75-4ecd-9b75-9ba85131b8ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276590138 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3276590138
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3272287997
Short name T186
Test name
Test status
Simulation time 23780460884 ps
CPU time 102.31 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 200732 kb
Host smart-5923d704-ee64-4d5b-88fe-698348074df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272287997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3272287997
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2060917016
Short name T218
Test name
Test status
Simulation time 29816088 ps
CPU time 0.57 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 195596 kb
Host smart-60b00449-70b6-4042-879a-4a27f99d1aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060917016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2060917016
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2857802059
Short name T438
Test name
Test status
Simulation time 2842912582 ps
CPU time 37.92 seconds
Started Aug 12 05:24:06 PM PDT 24
Finished Aug 12 05:24:44 PM PDT 24
Peak memory 200768 kb
Host smart-8d28a3a6-621b-4100-8839-4d473cb5238f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857802059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2857802059
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1971014550
Short name T182
Test name
Test status
Simulation time 93030554 ps
CPU time 2.15 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:23:57 PM PDT 24
Peak memory 200640 kb
Host smart-4d2c2c97-8a9b-445f-b55d-088ec3ad47b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971014550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1971014550
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4232752953
Short name T394
Test name
Test status
Simulation time 25346756446 ps
CPU time 1259.91 seconds
Started Aug 12 05:23:52 PM PDT 24
Finished Aug 12 05:44:52 PM PDT 24
Peak memory 735392 kb
Host smart-798dcd3a-54c0-416f-8c46-6d3b77bb669a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232752953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4232752953
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1918581505
Short name T239
Test name
Test status
Simulation time 10003300628 ps
CPU time 125.62 seconds
Started Aug 12 05:24:29 PM PDT 24
Finished Aug 12 05:26:35 PM PDT 24
Peak memory 200876 kb
Host smart-27145529-7311-4a9e-b57a-d8d7b1659d66
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918581505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1918581505
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.303707893
Short name T455
Test name
Test status
Simulation time 1960317395 ps
CPU time 108.13 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:25:41 PM PDT 24
Peak memory 200764 kb
Host smart-f587b6c6-9b97-48df-889f-a2af65c4c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303707893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.303707893
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.790430581
Short name T88
Test name
Test status
Simulation time 714409132 ps
CPU time 3.22 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:10 PM PDT 24
Peak memory 200752 kb
Host smart-f80b0e68-9562-4cd8-b762-648c1a219306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790430581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.790430581
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.850945256
Short name T32
Test name
Test status
Simulation time 25150596285 ps
CPU time 1497.17 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:49:03 PM PDT 24
Peak memory 739376 kb
Host smart-e36d31ec-d41a-446a-bae6-dbef1f8e8218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850945256 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.850945256
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1990623681
Short name T447
Test name
Test status
Simulation time 1008691910 ps
CPU time 49.23 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:24:54 PM PDT 24
Peak memory 200764 kb
Host smart-ff0ea912-f278-4964-8452-c74964c7bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990623681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1990623681
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.363498121
Short name T468
Test name
Test status
Simulation time 13567024 ps
CPU time 0.58 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:23:54 PM PDT 24
Peak memory 196324 kb
Host smart-988bcd6d-2c8d-4e18-8d8b-1063e01554f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363498121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.363498121
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.968012841
Short name T427
Test name
Test status
Simulation time 287647429 ps
CPU time 16.13 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:24:29 PM PDT 24
Peak memory 200768 kb
Host smart-884bac28-d52c-40ca-85e9-5fc414aefd08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968012841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.968012841
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.803017707
Short name T141
Test name
Test status
Simulation time 4593431503 ps
CPU time 61.77 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:25:06 PM PDT 24
Peak memory 217156 kb
Host smart-be487939-f4a5-4db7-8bbc-217ba00fd5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803017707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.803017707
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1998358906
Short name T511
Test name
Test status
Simulation time 7131505951 ps
CPU time 619.13 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:34:23 PM PDT 24
Peak memory 670940 kb
Host smart-a2aa6253-52f3-4885-b017-b5ac0c77bdda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998358906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1998358906
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.493753882
Short name T224
Test name
Test status
Simulation time 3807352520 ps
CPU time 207.01 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:27:35 PM PDT 24
Peak memory 200836 kb
Host smart-b0a2f195-5a78-4f99-9ea8-4f9554c00067
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493753882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.493753882
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2718627983
Short name T163
Test name
Test status
Simulation time 18038027307 ps
CPU time 234.58 seconds
Started Aug 12 05:24:10 PM PDT 24
Finished Aug 12 05:28:04 PM PDT 24
Peak memory 200880 kb
Host smart-83e5a580-51dc-4a8c-965f-7006ea88e701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718627983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2718627983
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2971080747
Short name T513
Test name
Test status
Simulation time 45517545 ps
CPU time 1.05 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:09 PM PDT 24
Peak memory 200436 kb
Host smart-fe03dd3b-4951-4463-92ac-5f64ac9c3d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971080747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2971080747
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2038550467
Short name T75
Test name
Test status
Simulation time 556383227488 ps
CPU time 4035.45 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 06:31:20 PM PDT 24
Peak memory 829920 kb
Host smart-8f2cf0cd-3e98-492b-baec-a7656cf38076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038550467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2038550467
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.404775477
Short name T93
Test name
Test status
Simulation time 124422266862 ps
CPU time 146.1 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:26:24 PM PDT 24
Peak memory 200824 kb
Host smart-a92c5785-70c8-4c6c-a686-c0c4d056c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404775477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.404775477
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.980885126
Short name T216
Test name
Test status
Simulation time 18207169 ps
CPU time 0.57 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:08 PM PDT 24
Peak memory 195676 kb
Host smart-0e376ffa-2be3-4351-b36b-ac72a7a6a6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980885126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.980885126
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.935957723
Short name T246
Test name
Test status
Simulation time 1355508746 ps
CPU time 24.46 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:24:22 PM PDT 24
Peak memory 200804 kb
Host smart-ae660a29-673c-4b49-90ce-011b97e586ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935957723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.935957723
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1976624012
Short name T363
Test name
Test status
Simulation time 9263637047 ps
CPU time 27.9 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:24:33 PM PDT 24
Peak memory 200800 kb
Host smart-625ebe7c-d3e5-4ec1-a910-b0bb258c3f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976624012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1976624012
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3159501824
Short name T285
Test name
Test status
Simulation time 6705376872 ps
CPU time 658.28 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:34:53 PM PDT 24
Peak memory 635164 kb
Host smart-875bca3d-c543-4152-9227-0d7460750c94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159501824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3159501824
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3873809661
Short name T348
Test name
Test status
Simulation time 3865115459 ps
CPU time 14.44 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:10 PM PDT 24
Peak memory 200720 kb
Host smart-89851c00-93c4-4a17-bbc7-565114889b92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873809661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3873809661
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1369519141
Short name T365
Test name
Test status
Simulation time 6682748064 ps
CPU time 30.49 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:24:24 PM PDT 24
Peak memory 200780 kb
Host smart-d75bcfe2-2e61-4944-bf4c-960e5025c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369519141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1369519141
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.395285480
Short name T336
Test name
Test status
Simulation time 295985998 ps
CPU time 13.2 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:24:15 PM PDT 24
Peak memory 200792 kb
Host smart-f9af18bc-6668-4822-8e45-b9ae030de6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395285480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.395285480
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3113660159
Short name T145
Test name
Test status
Simulation time 14675087465 ps
CPU time 1213.72 seconds
Started Aug 12 05:24:00 PM PDT 24
Finished Aug 12 05:44:14 PM PDT 24
Peak memory 703984 kb
Host smart-63530853-2b35-4937-b6c6-d173a77d1c51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113660159 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3113660159
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1813447041
Short name T80
Test name
Test status
Simulation time 4408035448 ps
CPU time 77.56 seconds
Started Aug 12 05:24:21 PM PDT 24
Finished Aug 12 05:25:38 PM PDT 24
Peak memory 200800 kb
Host smart-f99cf28b-16dd-4fa8-b7af-e1d2a522d5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813447041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1813447041
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1693145399
Short name T429
Test name
Test status
Simulation time 40359362 ps
CPU time 0.59 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:23:57 PM PDT 24
Peak memory 196716 kb
Host smart-937053f4-b75b-42b4-9507-588a452c2721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693145399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1693145399
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1791596423
Short name T378
Test name
Test status
Simulation time 215103366 ps
CPU time 11.82 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:08 PM PDT 24
Peak memory 200704 kb
Host smart-cb5b7ca2-3334-4c84-8808-b353650d9ace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791596423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1791596423
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1451844519
Short name T26
Test name
Test status
Simulation time 668064809 ps
CPU time 34.17 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:24:33 PM PDT 24
Peak memory 200728 kb
Host smart-a173ed76-7c99-45f2-aba5-7ebaceba8d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451844519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1451844519
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.779374991
Short name T226
Test name
Test status
Simulation time 2496288420 ps
CPU time 391.03 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:30:39 PM PDT 24
Peak memory 460232 kb
Host smart-8dc65854-c696-418b-b267-6362df1a203d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=779374991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.779374991
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.563415661
Short name T135
Test name
Test status
Simulation time 2077377361 ps
CPU time 25.94 seconds
Started Aug 12 05:23:59 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 200676 kb
Host smart-dc8a5318-513e-4b56-94ae-194f92c7bd53
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563415661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.563415661
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2779128564
Short name T456
Test name
Test status
Simulation time 21983507155 ps
CPU time 176.21 seconds
Started Aug 12 05:23:52 PM PDT 24
Finished Aug 12 05:26:48 PM PDT 24
Peak memory 209048 kb
Host smart-c8047d6a-1edb-494b-84fd-ec292c5901dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779128564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2779128564
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2911720828
Short name T35
Test name
Test status
Simulation time 3455057582 ps
CPU time 11.57 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:24:07 PM PDT 24
Peak memory 200840 kb
Host smart-1b47c5ba-0829-4bcd-a40d-d7d9b8cb6b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911720828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2911720828
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2187656093
Short name T449
Test name
Test status
Simulation time 3414843859 ps
CPU time 70.46 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:25:19 PM PDT 24
Peak memory 200696 kb
Host smart-cda1f497-5100-4a80-9ed1-695f18a9a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187656093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2187656093
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2130663172
Short name T464
Test name
Test status
Simulation time 14747437 ps
CPU time 0.62 seconds
Started Aug 12 05:23:24 PM PDT 24
Finished Aug 12 05:23:25 PM PDT 24
Peak memory 197420 kb
Host smart-99b38bdf-a764-4222-907b-213dae6eacd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130663172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2130663172
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2293943990
Short name T424
Test name
Test status
Simulation time 14146143648 ps
CPU time 64.13 seconds
Started Aug 12 05:23:27 PM PDT 24
Finished Aug 12 05:24:31 PM PDT 24
Peak memory 208840 kb
Host smart-1a57ecd4-7a86-4fff-a98d-7d9856659c5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293943990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2293943990
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.782108479
Short name T405
Test name
Test status
Simulation time 6292151946 ps
CPU time 20.22 seconds
Started Aug 12 05:23:35 PM PDT 24
Finished Aug 12 05:24:00 PM PDT 24
Peak memory 200684 kb
Host smart-c2c249a3-aded-4b11-822c-108f4664f68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782108479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.782108479
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1952039205
Short name T156
Test name
Test status
Simulation time 22050589901 ps
CPU time 1041.01 seconds
Started Aug 12 05:23:29 PM PDT 24
Finished Aug 12 05:40:50 PM PDT 24
Peak memory 734296 kb
Host smart-ee61276e-986b-48cf-bd6c-d505a164061b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952039205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1952039205
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.970410441
Short name T310
Test name
Test status
Simulation time 3280898401 ps
CPU time 187.66 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:26:41 PM PDT 24
Peak memory 200828 kb
Host smart-ce9c0935-0bbb-4239-90de-c7df4e3adf75
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970410441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.970410441
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2386772360
Short name T478
Test name
Test status
Simulation time 12316640099 ps
CPU time 76.74 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:24:55 PM PDT 24
Peak memory 200888 kb
Host smart-e0382ecb-b35b-48be-8c11-fffe6875efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386772360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2386772360
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2806662157
Short name T50
Test name
Test status
Simulation time 198968584 ps
CPU time 0.96 seconds
Started Aug 12 05:23:28 PM PDT 24
Finished Aug 12 05:23:29 PM PDT 24
Peak memory 220140 kb
Host smart-b43234f2-94be-4f50-ad2c-8b1790489a8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806662157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2806662157
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.74343950
Short name T264
Test name
Test status
Simulation time 309572362 ps
CPU time 6.03 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:23:39 PM PDT 24
Peak memory 200616 kb
Host smart-edd17ba0-77d9-4bb8-9483-0f402ac5f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74343950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.74343950
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2957090855
Short name T39
Test name
Test status
Simulation time 48566760422 ps
CPU time 912.41 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:38:46 PM PDT 24
Peak memory 664596 kb
Host smart-0512da58-397a-4296-a80b-71b720b90cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957090855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2957090855
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1947287025
Short name T414
Test name
Test status
Simulation time 17330185023 ps
CPU time 52.79 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:49 PM PDT 24
Peak memory 200784 kb
Host smart-7c1b4b8b-2b1b-47b0-877e-8ae55509af51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1947287025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1947287025
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1069712878
Short name T361
Test name
Test status
Simulation time 21932962018 ps
CPU time 111.75 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:25:25 PM PDT 24
Peak memory 200888 kb
Host smart-20256479-e26f-4f8c-b1f7-72706888f12c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1069712878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1069712878
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3469424930
Short name T159
Test name
Test status
Simulation time 46115334245 ps
CPU time 129.89 seconds
Started Aug 12 05:23:35 PM PDT 24
Finished Aug 12 05:25:45 PM PDT 24
Peak memory 200816 kb
Host smart-b5791b4e-280d-4e10-aa68-986678777bb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3469424930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3469424930
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2522834003
Short name T441
Test name
Test status
Simulation time 9208168897 ps
CPU time 516.53 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:32:21 PM PDT 24
Peak memory 200492 kb
Host smart-a0c5e4f6-0a6b-4dff-a0ca-a76b189a2237
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2522834003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2522834003
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.722704044
Short name T53
Test name
Test status
Simulation time 76016504462 ps
CPU time 2119.79 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:59:02 PM PDT 24
Peak memory 216288 kb
Host smart-3eb0c2dd-ccc8-4e22-9c4f-eedf1ef2a627
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=722704044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.722704044
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3044681320
Short name T360
Test name
Test status
Simulation time 41414581072 ps
CPU time 2157.2 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:59:20 PM PDT 24
Peak memory 217100 kb
Host smart-061be95e-46f6-427b-9c93-a9e20adba3c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3044681320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3044681320
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3285947585
Short name T302
Test name
Test status
Simulation time 1833837434 ps
CPU time 33.76 seconds
Started Aug 12 05:23:16 PM PDT 24
Finished Aug 12 05:23:50 PM PDT 24
Peak memory 200764 kb
Host smart-c9b7ead7-5df4-4732-9fb1-aabea0110ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285947585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3285947585
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2358302156
Short name T2
Test name
Test status
Simulation time 21810291 ps
CPU time 0.58 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:23:57 PM PDT 24
Peak memory 196688 kb
Host smart-4bbd84a0-9a57-490d-8990-535c0d3db56d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358302156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2358302156
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1199814157
Short name T262
Test name
Test status
Simulation time 1227828384 ps
CPU time 70.41 seconds
Started Aug 12 05:23:52 PM PDT 24
Finished Aug 12 05:25:02 PM PDT 24
Peak memory 200916 kb
Host smart-dbd50660-d188-4644-ab01-1b28a9691262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199814157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1199814157
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3500618342
Short name T308
Test name
Test status
Simulation time 71168889048 ps
CPU time 48.52 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:25:00 PM PDT 24
Peak memory 208940 kb
Host smart-770fe827-2aa9-4091-bd8e-51f0424f8c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500618342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3500618342
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1862384191
Short name T434
Test name
Test status
Simulation time 2151972173 ps
CPU time 475.65 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:31:57 PM PDT 24
Peak memory 701792 kb
Host smart-ba6a173a-c4ef-43f7-835f-fc9e98a56d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862384191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1862384191
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1007403934
Short name T173
Test name
Test status
Simulation time 3859990571 ps
CPU time 103.31 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:25:46 PM PDT 24
Peak memory 200796 kb
Host smart-572fd274-31cd-4002-96e8-bcc65225da25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007403934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1007403934
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1469439593
Short name T407
Test name
Test status
Simulation time 111447875372 ps
CPU time 135.69 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:26:12 PM PDT 24
Peak memory 200872 kb
Host smart-eb74e9a0-d6f5-44a9-88a9-94dda50717a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469439593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1469439593
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1726526495
Short name T137
Test name
Test status
Simulation time 1643910005 ps
CPU time 5.15 seconds
Started Aug 12 05:24:16 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 200760 kb
Host smart-11fe23cd-065b-4bae-b537-a81854368b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726526495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1726526495
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2593250572
Short name T388
Test name
Test status
Simulation time 22757597664 ps
CPU time 410.28 seconds
Started Aug 12 05:23:59 PM PDT 24
Finished Aug 12 05:30:50 PM PDT 24
Peak memory 632956 kb
Host smart-a4960819-3521-4c4a-ba6d-c73b3b32e36a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593250572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2593250572
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3776944505
Short name T258
Test name
Test status
Simulation time 3674555164 ps
CPU time 16.94 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:13 PM PDT 24
Peak memory 200820 kb
Host smart-fafa34ce-0a7f-496e-8723-dab911c6afe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776944505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3776944505
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.241668831
Short name T279
Test name
Test status
Simulation time 12689290 ps
CPU time 0.6 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:23:56 PM PDT 24
Peak memory 196716 kb
Host smart-14e1a952-31a5-4dd5-824d-ab14a2903a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241668831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.241668831
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2262457818
Short name T488
Test name
Test status
Simulation time 690164032 ps
CPU time 37.95 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 200788 kb
Host smart-0c853339-0c76-4db5-9d30-96be9f2cdfa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262457818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2262457818
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.998244922
Short name T425
Test name
Test status
Simulation time 9102790007 ps
CPU time 44.1 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:24:46 PM PDT 24
Peak memory 200852 kb
Host smart-1c9c6a03-df8f-407c-b1a1-479d8f95458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998244922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.998244922
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1746589985
Short name T433
Test name
Test status
Simulation time 28868502986 ps
CPU time 496.34 seconds
Started Aug 12 05:24:11 PM PDT 24
Finished Aug 12 05:32:28 PM PDT 24
Peak memory 689832 kb
Host smart-87126116-38b9-4c6c-ba69-1730903430b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746589985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1746589985
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.211869131
Short name T255
Test name
Test status
Simulation time 17767137704 ps
CPU time 154.71 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:26:37 PM PDT 24
Peak memory 200944 kb
Host smart-43466ff7-964f-4af2-8472-5516e5e21a73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211869131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.211869131
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3253799778
Short name T282
Test name
Test status
Simulation time 772283808 ps
CPU time 43.64 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:24:41 PM PDT 24
Peak memory 200752 kb
Host smart-9834432f-458c-48e4-857e-40e2b0e90556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253799778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3253799778
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1604389895
Short name T11
Test name
Test status
Simulation time 201718544 ps
CPU time 1.52 seconds
Started Aug 12 05:24:20 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 200796 kb
Host smart-dad5e068-a123-4756-ae1d-d586496d65c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604389895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1604389895
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4204798524
Short name T210
Test name
Test status
Simulation time 46907737033 ps
CPU time 2053.72 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:58:21 PM PDT 24
Peak memory 786336 kb
Host smart-84152d3e-5bd1-4456-8e03-cd275eb83acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204798524 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4204798524
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.79182829
Short name T57
Test name
Test status
Simulation time 12023447821 ps
CPU time 76.58 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:25:25 PM PDT 24
Peak memory 200792 kb
Host smart-8c5a68c7-976c-47c8-b7bf-df4dc9238943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79182829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.79182829
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1427533217
Short name T86
Test name
Test status
Simulation time 12474578 ps
CPU time 0.61 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:08 PM PDT 24
Peak memory 196072 kb
Host smart-fd15242a-15df-443a-86dd-26d2096d1c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427533217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1427533217
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1532498731
Short name T162
Test name
Test status
Simulation time 240118805 ps
CPU time 14.25 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:24:18 PM PDT 24
Peak memory 200704 kb
Host smart-23228e0f-9098-462d-95db-6effe3ca98eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532498731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1532498731
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1036025109
Short name T68
Test name
Test status
Simulation time 7867383012 ps
CPU time 673.89 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:35:23 PM PDT 24
Peak memory 711820 kb
Host smart-ccd9a66c-7467-4c8f-943c-a612ec9dc22b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036025109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1036025109
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.946063971
Short name T319
Test name
Test status
Simulation time 6331577177 ps
CPU time 73.98 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:25:29 PM PDT 24
Peak memory 200812 kb
Host smart-c34f5342-c9d3-4032-bedc-33c8a2a19e94
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946063971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.946063971
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3826764280
Short name T404
Test name
Test status
Simulation time 3065380907 ps
CPU time 87.26 seconds
Started Aug 12 05:23:59 PM PDT 24
Finished Aug 12 05:25:26 PM PDT 24
Peak memory 200884 kb
Host smart-c8780b5b-aa80-40a6-9130-fbf36ce48d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826764280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3826764280
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4067422538
Short name T321
Test name
Test status
Simulation time 1225112782 ps
CPU time 15.38 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:24:27 PM PDT 24
Peak memory 200828 kb
Host smart-74d127c0-b5a7-4725-9f09-65c106cb5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067422538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4067422538
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.4270069853
Short name T71
Test name
Test status
Simulation time 169069841850 ps
CPU time 1974.71 seconds
Started Aug 12 05:24:00 PM PDT 24
Finished Aug 12 05:56:55 PM PDT 24
Peak memory 749568 kb
Host smart-2ca89f26-941c-4b90-8f0f-c741453362af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270069853 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4270069853
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3007761833
Short name T374
Test name
Test status
Simulation time 633249296 ps
CPU time 23.94 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:24:33 PM PDT 24
Peak memory 200720 kb
Host smart-6c5fd2a6-2c3f-4d37-928e-dccb5bd7a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007761833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3007761833
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2618268468
Short name T214
Test name
Test status
Simulation time 17316159 ps
CPU time 0.58 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:24:13 PM PDT 24
Peak memory 197376 kb
Host smart-dc6949c6-649f-4059-bb51-07fdc2b17749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618268468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2618268468
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3843107972
Short name T290
Test name
Test status
Simulation time 691647293 ps
CPU time 44.84 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:52 PM PDT 24
Peak memory 200752 kb
Host smart-da555158-74c1-4d6e-8673-b01cba73a34a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843107972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3843107972
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.371044170
Short name T510
Test name
Test status
Simulation time 27911328963 ps
CPU time 82.94 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 200772 kb
Host smart-a08f61d3-ff88-43ce-b530-88ad1b8d80b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371044170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.371044170
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3728769497
Short name T288
Test name
Test status
Simulation time 5357430990 ps
CPU time 1010.09 seconds
Started Aug 12 05:24:28 PM PDT 24
Finished Aug 12 05:41:18 PM PDT 24
Peak memory 750968 kb
Host smart-c628130f-8b12-4ba7-90e5-7545ddfe85fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728769497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3728769497
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.196290098
Short name T387
Test name
Test status
Simulation time 34214048482 ps
CPU time 105.77 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:25:50 PM PDT 24
Peak memory 200792 kb
Host smart-de04372c-c3d5-431f-ae0e-3bab8eb3fd63
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196290098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.196290098
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1153235621
Short name T421
Test name
Test status
Simulation time 2014610360 ps
CPU time 24.38 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:24:30 PM PDT 24
Peak memory 200672 kb
Host smart-0f41e92b-ad0a-4f84-9683-ac8ec49d0536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153235621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1153235621
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2680351645
Short name T330
Test name
Test status
Simulation time 7545276330 ps
CPU time 15.11 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:24:23 PM PDT 24
Peak memory 200864 kb
Host smart-b9d5167d-e2d2-4669-9e2e-09cd2ad58a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680351645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2680351645
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1130462521
Short name T332
Test name
Test status
Simulation time 1048934041 ps
CPU time 57.64 seconds
Started Aug 12 05:23:56 PM PDT 24
Finished Aug 12 05:24:54 PM PDT 24
Peak memory 200652 kb
Host smart-0c03dc8b-5643-4847-b834-f854a7f251a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130462521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1130462521
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.174859187
Short name T359
Test name
Test status
Simulation time 1374291377 ps
CPU time 60.42 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:25:13 PM PDT 24
Peak memory 200796 kb
Host smart-9c14dc4c-c1a5-497e-ba15-5ea9c6c1aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174859187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.174859187
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2424699798
Short name T396
Test name
Test status
Simulation time 30545865 ps
CPU time 0.63 seconds
Started Aug 12 05:23:57 PM PDT 24
Finished Aug 12 05:23:58 PM PDT 24
Peak memory 196720 kb
Host smart-b9b2e110-1887-4180-bd57-1f2bbb0b50d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424699798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2424699798
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3093901121
Short name T346
Test name
Test status
Simulation time 832827691 ps
CPU time 44.26 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:24:57 PM PDT 24
Peak memory 200776 kb
Host smart-8e1c85af-3441-4a36-94cc-a2e911df3123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093901121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3093901121
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.286373431
Short name T435
Test name
Test status
Simulation time 698906214 ps
CPU time 34.33 seconds
Started Aug 12 05:24:10 PM PDT 24
Finished Aug 12 05:24:49 PM PDT 24
Peak memory 200776 kb
Host smart-dd60c49c-1c0f-4b34-81cb-295bd34a4773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286373431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.286373431
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1258320430
Short name T445
Test name
Test status
Simulation time 675605425 ps
CPU time 56.13 seconds
Started Aug 12 05:24:22 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 336360 kb
Host smart-946d7d26-7a5c-4c8e-8daa-5b35c81caa47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258320430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1258320430
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.296757393
Short name T437
Test name
Test status
Simulation time 50193055130 ps
CPU time 126.72 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:26:14 PM PDT 24
Peak memory 200956 kb
Host smart-d293f5a5-24d3-4b92-a233-66bb52333263
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296757393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.296757393
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1326655982
Short name T453
Test name
Test status
Simulation time 8426398841 ps
CPU time 134.67 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:26:24 PM PDT 24
Peak memory 200580 kb
Host smart-2f65ed65-66ca-4880-9506-8048157069ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326655982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1326655982
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1012231373
Short name T136
Test name
Test status
Simulation time 435045943 ps
CPU time 6.34 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:24:19 PM PDT 24
Peak memory 200732 kb
Host smart-74324b3f-05ac-40cb-89ed-1c816d46e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012231373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1012231373
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3019145984
Short name T185
Test name
Test status
Simulation time 2339198443 ps
CPU time 127.98 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:26:16 PM PDT 24
Peak memory 200844 kb
Host smart-6db95136-718f-4994-a7e7-16b6f45e6917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019145984 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3019145984
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1229892830
Short name T237
Test name
Test status
Simulation time 20898077610 ps
CPU time 71.82 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:25:29 PM PDT 24
Peak memory 200808 kb
Host smart-9af80bfe-b343-46d1-b8e6-2feb735ee2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229892830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1229892830
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2248064198
Short name T318
Test name
Test status
Simulation time 44604753 ps
CPU time 0.59 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:24:13 PM PDT 24
Peak memory 197348 kb
Host smart-2b3e6282-c1ba-492d-9790-b516d3b4b163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248064198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2248064198
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2377925456
Short name T178
Test name
Test status
Simulation time 635994970 ps
CPU time 10.24 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 200732 kb
Host smart-ae670fb2-9823-436b-a331-8a15f893653b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377925456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2377925456
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2406287397
Short name T267
Test name
Test status
Simulation time 13007890849 ps
CPU time 42.37 seconds
Started Aug 12 05:24:02 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 200796 kb
Host smart-b7cdf089-6991-4f2b-9e0b-1caad7c143f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406287397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2406287397
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.308327856
Short name T300
Test name
Test status
Simulation time 26376106035 ps
CPU time 1058.21 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:41:57 PM PDT 24
Peak memory 769044 kb
Host smart-d9557dee-befd-4981-a2d3-a6d404dcc6ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308327856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.308327856
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.413042943
Short name T470
Test name
Test status
Simulation time 311232711 ps
CPU time 17.41 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:24:26 PM PDT 24
Peak memory 200592 kb
Host smart-8faf39ad-c1ef-4741-8f16-eeb845daa4dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413042943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.413042943
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.353807185
Short name T327
Test name
Test status
Simulation time 13710718815 ps
CPU time 89.79 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:25:31 PM PDT 24
Peak memory 216980 kb
Host smart-7f45ecb0-0b64-4b49-94f3-678622726018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353807185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.353807185
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1713937466
Short name T529
Test name
Test status
Simulation time 2549361660 ps
CPU time 14.9 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:24:32 PM PDT 24
Peak memory 200776 kb
Host smart-814e465f-aeba-4089-8579-f67874659795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713937466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1713937466
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2359752119
Short name T121
Test name
Test status
Simulation time 121029177489 ps
CPU time 927.21 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:39:46 PM PDT 24
Peak memory 688884 kb
Host smart-d38fc0d3-4dbf-415a-ac9f-924036442e5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359752119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2359752119
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.815135630
Short name T174
Test name
Test status
Simulation time 6720865655 ps
CPU time 120.39 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:26:12 PM PDT 24
Peak memory 200576 kb
Host smart-322f688c-8071-4b70-b178-7e06c04d4ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815135630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.815135630
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2630252490
Short name T292
Test name
Test status
Simulation time 14006970 ps
CPU time 0.64 seconds
Started Aug 12 05:23:55 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 196452 kb
Host smart-89ebe303-9672-4446-99b7-237e6be785dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630252490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2630252490
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1115915847
Short name T382
Test name
Test status
Simulation time 1885940166 ps
CPU time 96.13 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:25:40 PM PDT 24
Peak memory 200776 kb
Host smart-e16ed416-2c60-4e3d-86eb-fdd98912399c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115915847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1115915847
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.681468889
Short name T466
Test name
Test status
Simulation time 2468976199 ps
CPU time 8.49 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 200816 kb
Host smart-be4fba6c-c75d-40e0-91d6-82cad768b7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681468889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.681468889
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2225662006
Short name T22
Test name
Test status
Simulation time 27894314442 ps
CPU time 1270.15 seconds
Started Aug 12 05:24:03 PM PDT 24
Finished Aug 12 05:45:13 PM PDT 24
Peak memory 749316 kb
Host smart-dab8a37f-b2e0-40d2-a477-aeb50b1bf716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225662006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2225662006
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2356471046
Short name T283
Test name
Test status
Simulation time 5140223575 ps
CPU time 89.36 seconds
Started Aug 12 05:24:10 PM PDT 24
Finished Aug 12 05:25:39 PM PDT 24
Peak memory 200840 kb
Host smart-0bee1d27-289a-420a-82eb-196eeb11dbcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356471046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2356471046
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1194466612
Short name T263
Test name
Test status
Simulation time 7481297802 ps
CPU time 101.11 seconds
Started Aug 12 05:24:10 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 200844 kb
Host smart-c3814e2b-6128-4baf-8dcb-6af058a9d1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194466612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1194466612
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3217244684
Short name T325
Test name
Test status
Simulation time 321943325 ps
CPU time 4.2 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:24:13 PM PDT 24
Peak memory 200808 kb
Host smart-9bfedfd6-6061-4ccf-8064-1876b2357db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217244684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3217244684
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.981982819
Short name T465
Test name
Test status
Simulation time 140404329 ps
CPU time 0.6 seconds
Started Aug 12 05:24:01 PM PDT 24
Finished Aug 12 05:24:02 PM PDT 24
Peak memory 196472 kb
Host smart-c4025faa-44cd-4352-b014-8f250ab31089
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981982819 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.981982819
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2760093694
Short name T277
Test name
Test status
Simulation time 3053191495 ps
CPU time 77.72 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 200776 kb
Host smart-bc730fd3-7691-4b64-b104-d24dd91fd02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760093694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2760093694
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2612482573
Short name T1
Test name
Test status
Simulation time 50050487 ps
CPU time 0.59 seconds
Started Aug 12 05:24:16 PM PDT 24
Finished Aug 12 05:24:16 PM PDT 24
Peak memory 196664 kb
Host smart-0f49f84a-0a1b-4137-af9a-946bdedf265b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612482573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2612482573
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.584752682
Short name T314
Test name
Test status
Simulation time 539097542 ps
CPU time 29.41 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:24:37 PM PDT 24
Peak memory 200808 kb
Host smart-de5221e8-4004-412b-8542-65cdf7d17366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584752682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.584752682
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3612940612
Short name T482
Test name
Test status
Simulation time 1272793380 ps
CPU time 9.27 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:24:22 PM PDT 24
Peak memory 200772 kb
Host smart-7b7e806d-9b27-45ec-ab7b-65679c6d15e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612940612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3612940612
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1215983115
Short name T166
Test name
Test status
Simulation time 10158562760 ps
CPU time 428.4 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:31:15 PM PDT 24
Peak memory 637280 kb
Host smart-79fb5a2b-072a-473b-a483-f548bb82b63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215983115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1215983115
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2909672634
Short name T260
Test name
Test status
Simulation time 131521047 ps
CPU time 3.45 seconds
Started Aug 12 05:24:20 PM PDT 24
Finished Aug 12 05:24:23 PM PDT 24
Peak memory 200636 kb
Host smart-be0374bf-181a-4ab8-a5ee-fd9e06d2c908
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909672634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2909672634
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2112104800
Short name T343
Test name
Test status
Simulation time 33671631 ps
CPU time 0.77 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 198424 kb
Host smart-6c79fafd-0bdf-4675-b7bb-fe8b477694f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112104800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2112104800
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3660416218
Short name T341
Test name
Test status
Simulation time 418773197 ps
CPU time 1.47 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:24:18 PM PDT 24
Peak memory 200704 kb
Host smart-53b08cc0-f104-40b4-ad7a-4173d5dec188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660416218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3660416218
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3805254116
Short name T16
Test name
Test status
Simulation time 84232862429 ps
CPU time 987.61 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:40:42 PM PDT 24
Peak memory 688500 kb
Host smart-bced93ce-c600-44ae-9ef5-eeb22d8e85e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805254116 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3805254116
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1027792106
Short name T296
Test name
Test status
Simulation time 2352900939 ps
CPU time 47.45 seconds
Started Aug 12 05:24:29 PM PDT 24
Finished Aug 12 05:25:17 PM PDT 24
Peak memory 200808 kb
Host smart-14c7f199-2808-409d-acf5-2b1afd28aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027792106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1027792106
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2489581148
Short name T372
Test name
Test status
Simulation time 21872734 ps
CPU time 0.58 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:24:35 PM PDT 24
Peak memory 197420 kb
Host smart-5159661f-79c5-46b2-b915-6ad1160db9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489581148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2489581148
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2544046887
Short name T353
Test name
Test status
Simulation time 315304646 ps
CPU time 8.9 seconds
Started Aug 12 05:24:26 PM PDT 24
Finished Aug 12 05:24:35 PM PDT 24
Peak memory 200688 kb
Host smart-db1bbe68-5265-4d70-8cb1-2c76139f65da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544046887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2544046887
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.213868014
Short name T486
Test name
Test status
Simulation time 3199874440 ps
CPU time 43.95 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:25:01 PM PDT 24
Peak memory 200892 kb
Host smart-8434d913-8777-40b6-9a7d-b7c3b428a6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213868014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.213868014
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3889342235
Short name T460
Test name
Test status
Simulation time 61739782307 ps
CPU time 1170 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:43:45 PM PDT 24
Peak memory 744252 kb
Host smart-b8d343e6-d9b4-44f4-8597-4fb317826eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889342235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3889342235
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2928260582
Short name T352
Test name
Test status
Simulation time 114064997018 ps
CPU time 157.29 seconds
Started Aug 12 05:24:10 PM PDT 24
Finished Aug 12 05:26:48 PM PDT 24
Peak memory 200844 kb
Host smart-a01d6631-f8ec-4f41-8101-0167b0f2f540
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928260582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2928260582
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2515866801
Short name T232
Test name
Test status
Simulation time 251445637 ps
CPU time 14.46 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:24:26 PM PDT 24
Peak memory 200760 kb
Host smart-138ae0b3-fadb-47b3-91e9-ced71161334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515866801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2515866801
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.56698047
Short name T196
Test name
Test status
Simulation time 718635613 ps
CPU time 8.29 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 200772 kb
Host smart-1e36d506-dbae-4224-bb5b-e2affa51c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56698047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.56698047
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2378431288
Short name T183
Test name
Test status
Simulation time 34470858956 ps
CPU time 234.97 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:28:08 PM PDT 24
Peak memory 217220 kb
Host smart-e7b06597-8630-4d23-bff9-5b53a2a041f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378431288 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2378431288
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2527641503
Short name T426
Test name
Test status
Simulation time 7685968311 ps
CPU time 96.43 seconds
Started Aug 12 05:24:00 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 200832 kb
Host smart-94dabf3c-10ff-4e2f-ad76-4955aaecf6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527641503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2527641503
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1281717334
Short name T385
Test name
Test status
Simulation time 151462854 ps
CPU time 0.59 seconds
Started Aug 12 05:24:22 PM PDT 24
Finished Aug 12 05:24:22 PM PDT 24
Peak memory 196704 kb
Host smart-b14136a1-678a-44f0-a451-74e3d582a0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281717334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1281717334
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3926769157
Short name T304
Test name
Test status
Simulation time 620041456 ps
CPU time 18.76 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:24:24 PM PDT 24
Peak memory 200808 kb
Host smart-9804e83a-1564-42e6-97b7-5d0a4d7a3182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926769157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3926769157
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2875460226
Short name T293
Test name
Test status
Simulation time 8829208363 ps
CPU time 56.04 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:25:11 PM PDT 24
Peak memory 217208 kb
Host smart-4ac1fc68-a31a-44d0-b5e0-26d39cd50da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875460226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2875460226
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3863263344
Short name T485
Test name
Test status
Simulation time 3715596474 ps
CPU time 639.53 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:34:44 PM PDT 24
Peak memory 701796 kb
Host smart-ba1e6494-52de-4abc-b9b9-c1362405c73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863263344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3863263344
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.705146375
Short name T356
Test name
Test status
Simulation time 2949521791 ps
CPU time 14.88 seconds
Started Aug 12 05:24:20 PM PDT 24
Finished Aug 12 05:24:35 PM PDT 24
Peak memory 200708 kb
Host smart-c1d857e4-5102-4a90-ac20-101b63f09e7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705146375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.705146375
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2715710511
Short name T490
Test name
Test status
Simulation time 84695453667 ps
CPU time 163.56 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:26:51 PM PDT 24
Peak memory 200864 kb
Host smart-c2784ca6-c64a-4727-91e6-8240ce349f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715710511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2715710511
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2861987765
Short name T473
Test name
Test status
Simulation time 706785966 ps
CPU time 12.9 seconds
Started Aug 12 05:24:33 PM PDT 24
Finished Aug 12 05:24:46 PM PDT 24
Peak memory 200820 kb
Host smart-2fc52ca7-3cf7-432e-8444-65dc9909c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861987765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2861987765
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1945874946
Short name T147
Test name
Test status
Simulation time 38736536424 ps
CPU time 529.01 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:33:03 PM PDT 24
Peak memory 209012 kb
Host smart-f59e8f01-91cd-43ec-9e92-76df0f05e425
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945874946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1945874946
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2053516950
Short name T413
Test name
Test status
Simulation time 5023021816 ps
CPU time 57.45 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:25:15 PM PDT 24
Peak memory 200844 kb
Host smart-36a0d532-6506-4eb7-8844-c7de299f8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053516950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2053516950
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1111062438
Short name T448
Test name
Test status
Simulation time 12129750 ps
CPU time 0.56 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:23:23 PM PDT 24
Peak memory 195744 kb
Host smart-e237e43c-fdf2-4a10-90e2-da5443d85c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111062438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1111062438
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.784507134
Short name T436
Test name
Test status
Simulation time 6089538888 ps
CPU time 79.07 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:24:41 PM PDT 24
Peak memory 200756 kb
Host smart-68f95713-5523-4853-8959-151eaab2bc84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=784507134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.784507134
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.4192430615
Short name T471
Test name
Test status
Simulation time 5183692244 ps
CPU time 23.85 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:24:11 PM PDT 24
Peak memory 200708 kb
Host smart-97090534-7165-4921-b74d-1f2e1c04d04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192430615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4192430615
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1652929329
Short name T220
Test name
Test status
Simulation time 2974239643 ps
CPU time 481.32 seconds
Started Aug 12 05:23:25 PM PDT 24
Finished Aug 12 05:31:27 PM PDT 24
Peak memory 520044 kb
Host smart-4de95c64-7106-4839-9ef7-fe75294a40a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652929329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1652929329
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2989037182
Short name T450
Test name
Test status
Simulation time 1478488773 ps
CPU time 80.03 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:24:53 PM PDT 24
Peak memory 200636 kb
Host smart-cbbc799f-6a5f-4e33-bfe4-50470983692b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989037182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2989037182
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.326840094
Short name T519
Test name
Test status
Simulation time 157064369458 ps
CPU time 209.96 seconds
Started Aug 12 05:23:21 PM PDT 24
Finished Aug 12 05:26:52 PM PDT 24
Peak memory 201080 kb
Host smart-00422e48-669b-4762-a99b-8c9863155e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326840094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.326840094
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2219679515
Short name T51
Test name
Test status
Simulation time 39075720 ps
CPU time 0.79 seconds
Started Aug 12 05:23:25 PM PDT 24
Finished Aug 12 05:23:26 PM PDT 24
Peak memory 219092 kb
Host smart-085c67cb-ec4b-454f-884f-53cef0a4b087
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219679515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2219679515
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.771881594
Short name T467
Test name
Test status
Simulation time 231801732 ps
CPU time 10.73 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:23:53 PM PDT 24
Peak memory 200828 kb
Host smart-8a7413b6-3225-4e1d-a873-431a86cf3d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771881594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.771881594
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.831449697
Short name T451
Test name
Test status
Simulation time 82814161242 ps
CPU time 2420.16 seconds
Started Aug 12 05:23:27 PM PDT 24
Finished Aug 12 06:03:47 PM PDT 24
Peak memory 742660 kb
Host smart-837d2838-a938-4b08-bb17-1126903c159a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831449697 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.831449697
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.461820520
Short name T12
Test name
Test status
Simulation time 34159151399 ps
CPU time 116.78 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 315904 kb
Host smart-27a48eb3-b4e9-4a1b-84aa-b940fb7dbf59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461820520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.461820520
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1005917384
Short name T235
Test name
Test status
Simulation time 4358856315 ps
CPU time 51.17 seconds
Started Aug 12 05:23:32 PM PDT 24
Finished Aug 12 05:24:23 PM PDT 24
Peak memory 200852 kb
Host smart-9e5f9e1f-633b-4a12-88f4-f6e7d189d511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1005917384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1005917384
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2414803100
Short name T33
Test name
Test status
Simulation time 5231636570 ps
CPU time 60.72 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:24:24 PM PDT 24
Peak memory 200852 kb
Host smart-539713a2-f66a-44b4-8089-da2cedfc922f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2414803100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2414803100
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3822835223
Short name T295
Test name
Test status
Simulation time 20104039685 ps
CPU time 72.75 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:24:46 PM PDT 24
Peak memory 200836 kb
Host smart-28cfb370-5000-420e-a599-906db288aa1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3822835223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3822835223
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2570100157
Short name T192
Test name
Test status
Simulation time 10497713472 ps
CPU time 526.92 seconds
Started Aug 12 05:23:30 PM PDT 24
Finished Aug 12 05:32:18 PM PDT 24
Peak memory 200768 kb
Host smart-e9f34913-b935-4cad-a5a3-2d65e5e5ec98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2570100157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2570100157
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2029624904
Short name T298
Test name
Test status
Simulation time 81165497120 ps
CPU time 2204.93 seconds
Started Aug 12 05:23:35 PM PDT 24
Finished Aug 12 06:00:21 PM PDT 24
Peak memory 215728 kb
Host smart-d1638849-9e44-41d1-8771-518722ffdb52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2029624904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2029624904
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1668916176
Short name T442
Test name
Test status
Simulation time 71877746020 ps
CPU time 2188.34 seconds
Started Aug 12 05:23:20 PM PDT 24
Finished Aug 12 05:59:49 PM PDT 24
Peak memory 216252 kb
Host smart-d67c114e-c9bc-40a4-a859-9935e7899556
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1668916176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1668916176
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.878297890
Short name T474
Test name
Test status
Simulation time 18355057739 ps
CPU time 60.8 seconds
Started Aug 12 05:23:15 PM PDT 24
Finished Aug 12 05:24:16 PM PDT 24
Peak memory 200572 kb
Host smart-62f1524b-f9d5-44cf-9fb3-35c0e97470ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878297890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.878297890
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.392588034
Short name T521
Test name
Test status
Simulation time 14540841 ps
CPU time 0.58 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:24:15 PM PDT 24
Peak memory 195700 kb
Host smart-68d4abd8-a640-4088-9fa8-06bbd35e6df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392588034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.392588034
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3672674792
Short name T501
Test name
Test status
Simulation time 751615847 ps
CPU time 21.79 seconds
Started Aug 12 05:24:21 PM PDT 24
Finished Aug 12 05:24:43 PM PDT 24
Peak memory 200768 kb
Host smart-4341afc7-d738-41bc-a79e-c314def68adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672674792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3672674792
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1564714414
Short name T370
Test name
Test status
Simulation time 1271749124 ps
CPU time 12.04 seconds
Started Aug 12 05:24:22 PM PDT 24
Finished Aug 12 05:24:34 PM PDT 24
Peak memory 200632 kb
Host smart-7af932e3-5f60-456d-9edc-c870f63465e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564714414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1564714414
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.643981013
Short name T179
Test name
Test status
Simulation time 16165087447 ps
CPU time 347.31 seconds
Started Aug 12 05:24:11 PM PDT 24
Finished Aug 12 05:29:58 PM PDT 24
Peak memory 619948 kb
Host smart-6d563564-b4a8-4a09-ba1c-4be1f2e4a959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643981013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.643981013
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.177301940
Short name T469
Test name
Test status
Simulation time 3016520172 ps
CPU time 51.71 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:25:06 PM PDT 24
Peak memory 200828 kb
Host smart-db1a71c0-ede0-4885-84fd-c7e1d23ce4fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177301940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.177301940
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.867609816
Short name T170
Test name
Test status
Simulation time 3322268420 ps
CPU time 50.16 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:57 PM PDT 24
Peak memory 200828 kb
Host smart-36c4f9a7-73ba-4383-a94b-f12ccb2d2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867609816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.867609816
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1664505133
Short name T284
Test name
Test status
Simulation time 1363001001 ps
CPU time 5.81 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:24:19 PM PDT 24
Peak memory 200764 kb
Host smart-6c03e96c-c8f3-4fb7-b36e-2f355b924a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664505133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1664505133
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2558333244
Short name T60
Test name
Test status
Simulation time 24436541619 ps
CPU time 830.94 seconds
Started Aug 12 05:24:09 PM PDT 24
Finished Aug 12 05:38:00 PM PDT 24
Peak memory 420688 kb
Host smart-d2755030-69ed-4ea8-b049-d97cc1698193
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558333244 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2558333244
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1962902044
Short name T67
Test name
Test status
Simulation time 21679241254 ps
CPU time 135.26 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:26:34 PM PDT 24
Peak memory 200796 kb
Host smart-b39379ca-8325-4096-8a41-61834374e4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962902044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1962902044
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3061323372
Short name T339
Test name
Test status
Simulation time 31502192 ps
CPU time 0.61 seconds
Started Aug 12 05:24:11 PM PDT 24
Finished Aug 12 05:24:12 PM PDT 24
Peak memory 195724 kb
Host smart-6e7b97f0-db1c-4fee-991a-3b6a18a51feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061323372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3061323372
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.526289180
Short name T257
Test name
Test status
Simulation time 8574607491 ps
CPU time 93.42 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:25:42 PM PDT 24
Peak memory 200820 kb
Host smart-06492e8e-a209-4e83-9057-97f1d8a19174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526289180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.526289180
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1821493860
Short name T10
Test name
Test status
Simulation time 9477129138 ps
CPU time 61.07 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:25:13 PM PDT 24
Peak memory 209072 kb
Host smart-c3dc11f5-7914-4ad4-83da-0d2eb9ce3d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821493860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1821493860
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2369884659
Short name T524
Test name
Test status
Simulation time 7128045354 ps
CPU time 350.26 seconds
Started Aug 12 05:24:20 PM PDT 24
Finished Aug 12 05:30:10 PM PDT 24
Peak memory 607504 kb
Host smart-3cdf944f-1f9e-4a48-b686-9427362a382b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369884659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2369884659
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.893333919
Short name T184
Test name
Test status
Simulation time 2215028207 ps
CPU time 38.17 seconds
Started Aug 12 05:24:07 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 200816 kb
Host smart-7333fcbe-60d3-4acc-a34a-30b9174d42c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893333919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.893333919
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.321648013
Short name T56
Test name
Test status
Simulation time 2936163193 ps
CPU time 165.9 seconds
Started Aug 12 05:24:04 PM PDT 24
Finished Aug 12 05:26:50 PM PDT 24
Peak memory 217048 kb
Host smart-bf3b6b17-94cf-4478-af86-b72a954aa00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321648013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.321648013
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3682048015
Short name T400
Test name
Test status
Simulation time 535833119 ps
CPU time 5.44 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:24:14 PM PDT 24
Peak memory 200788 kb
Host smart-330fd841-0532-482c-9569-a9ea983fb1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682048015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3682048015
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2642607385
Short name T409
Test name
Test status
Simulation time 2253162493 ps
CPU time 114 seconds
Started Aug 12 05:24:32 PM PDT 24
Finished Aug 12 05:26:26 PM PDT 24
Peak memory 200812 kb
Host smart-9b5efb7a-7c29-4e12-a60c-dde3ae46eefa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642607385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2642607385
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.473004545
Short name T188
Test name
Test status
Simulation time 11031084377 ps
CPU time 52.01 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:25:06 PM PDT 24
Peak memory 200876 kb
Host smart-619e4a4f-fbb2-443c-b33e-bd4dbf408ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473004545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.473004545
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3365650132
Short name T412
Test name
Test status
Simulation time 45949236 ps
CPU time 0.59 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:24:15 PM PDT 24
Peak memory 196380 kb
Host smart-62e2300a-3836-47e1-b2c7-7677ca34966d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365650132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3365650132
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1836085864
Short name T21
Test name
Test status
Simulation time 1170555971 ps
CPU time 66.28 seconds
Started Aug 12 05:24:03 PM PDT 24
Finished Aug 12 05:25:09 PM PDT 24
Peak memory 200800 kb
Host smart-38d045d7-98a7-41aa-8b7f-0b410a4ab22f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836085864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1836085864
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2195232867
Short name T383
Test name
Test status
Simulation time 200058915 ps
CPU time 10.57 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 200740 kb
Host smart-7577ad0b-d835-4268-a47e-52cfc67d9254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195232867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2195232867
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2685274025
Short name T408
Test name
Test status
Simulation time 8475943801 ps
CPU time 611.57 seconds
Started Aug 12 05:24:25 PM PDT 24
Finished Aug 12 05:34:37 PM PDT 24
Peak memory 675508 kb
Host smart-a35d12d8-513c-4ba3-b86b-60e7696afb02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685274025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2685274025
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1292771507
Short name T390
Test name
Test status
Simulation time 9720707627 ps
CPU time 111.46 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:26:00 PM PDT 24
Peak memory 200832 kb
Host smart-0da073f9-dac8-4924-af62-8602167e8bb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292771507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1292771507
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4280369722
Short name T323
Test name
Test status
Simulation time 19121578202 ps
CPU time 69.22 seconds
Started Aug 12 05:24:18 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 200972 kb
Host smart-02792d5b-75e2-4328-af96-e8637a940ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280369722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4280369722
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2541294101
Short name T29
Test name
Test status
Simulation time 1177011631 ps
CPU time 14.7 seconds
Started Aug 12 05:24:22 PM PDT 24
Finished Aug 12 05:24:37 PM PDT 24
Peak memory 200728 kb
Host smart-78937f53-c6e3-4744-8e39-4a35ed4599ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541294101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2541294101
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3507348021
Short name T401
Test name
Test status
Simulation time 24215839756 ps
CPU time 87.68 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:25:47 PM PDT 24
Peak memory 217192 kb
Host smart-4daddd5d-d32b-42ba-bfec-69abad036533
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507348021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3507348021
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.927844045
Short name T91
Test name
Test status
Simulation time 96338771976 ps
CPU time 134.69 seconds
Started Aug 12 05:24:21 PM PDT 24
Finished Aug 12 05:26:35 PM PDT 24
Peak memory 200792 kb
Host smart-fc5a7fac-f266-49ae-854e-999bc2ad19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927844045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.927844045
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2745870615
Short name T479
Test name
Test status
Simulation time 11561445 ps
CPU time 0.58 seconds
Started Aug 12 05:24:24 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 195644 kb
Host smart-7f0d38e7-9a56-47a7-b619-e8bbb6f79ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745870615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2745870615
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1900983244
Short name T152
Test name
Test status
Simulation time 493303933 ps
CPU time 25.22 seconds
Started Aug 12 05:24:29 PM PDT 24
Finished Aug 12 05:24:54 PM PDT 24
Peak memory 200736 kb
Host smart-a41bca8e-c462-48db-8f04-56da93ee205b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900983244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1900983244
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2531005437
Short name T397
Test name
Test status
Simulation time 2397435626 ps
CPU time 29.98 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 200816 kb
Host smart-bfbc270b-0489-42f8-bbf6-b31b69624032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531005437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2531005437
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2750248905
Short name T362
Test name
Test status
Simulation time 4945711020 ps
CPU time 204.83 seconds
Started Aug 12 05:24:26 PM PDT 24
Finished Aug 12 05:27:51 PM PDT 24
Peak memory 479668 kb
Host smart-f398a5db-53e5-46a8-88e0-19a01d5a9b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750248905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2750248905
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2520154193
Short name T515
Test name
Test status
Simulation time 36602905218 ps
CPU time 131.71 seconds
Started Aug 12 05:24:29 PM PDT 24
Finished Aug 12 05:26:40 PM PDT 24
Peak memory 200752 kb
Host smart-8d7e7c0f-1a9d-48f5-80e3-f745aaa5b987
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520154193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2520154193
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3831414167
Short name T265
Test name
Test status
Simulation time 3858913900 ps
CPU time 48.39 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:25:07 PM PDT 24
Peak memory 200876 kb
Host smart-47199d55-f487-4c0c-92a3-f93118662bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831414167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3831414167
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2625306931
Short name T87
Test name
Test status
Simulation time 2395151256 ps
CPU time 10.47 seconds
Started Aug 12 05:24:30 PM PDT 24
Finished Aug 12 05:24:40 PM PDT 24
Peak memory 200844 kb
Host smart-3a8281d4-0026-4c61-8e2e-002c3ffe9b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625306931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2625306931
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.48968776
Short name T256
Test name
Test status
Simulation time 30665978704 ps
CPU time 133.08 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:26:27 PM PDT 24
Peak memory 200716 kb
Host smart-c3a8f8ac-e343-4816-8c81-04387ec5129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48968776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.48968776
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2136144507
Short name T349
Test name
Test status
Simulation time 29406810 ps
CPU time 0.57 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:24:18 PM PDT 24
Peak memory 195764 kb
Host smart-56aef259-75e3-4d70-ae58-5afc38140a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136144507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2136144507
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1965548726
Short name T376
Test name
Test status
Simulation time 7580621869 ps
CPU time 40.53 seconds
Started Aug 12 05:24:18 PM PDT 24
Finished Aug 12 05:24:59 PM PDT 24
Peak memory 200796 kb
Host smart-fb56911b-4265-4130-97b4-b4eb319c49e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965548726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1965548726
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2045913981
Short name T215
Test name
Test status
Simulation time 3592711957 ps
CPU time 46.5 seconds
Started Aug 12 05:24:08 PM PDT 24
Finished Aug 12 05:24:55 PM PDT 24
Peak memory 200876 kb
Host smart-4c53d364-2436-4cab-8151-0f0c1c3ede42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045913981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2045913981
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3797241099
Short name T522
Test name
Test status
Simulation time 18658319 ps
CPU time 0.85 seconds
Started Aug 12 05:24:16 PM PDT 24
Finished Aug 12 05:24:17 PM PDT 24
Peak memory 200464 kb
Host smart-46b68eb9-7c3e-4f51-b244-aef7c24786ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797241099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3797241099
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.986295541
Short name T149
Test name
Test status
Simulation time 6147988608 ps
CPU time 111.53 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:26:04 PM PDT 24
Peak memory 200824 kb
Host smart-e421a740-8b9c-495e-ae81-b9c2db050c3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986295541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.986295541
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1729519939
Short name T245
Test name
Test status
Simulation time 2274613255 ps
CPU time 40.63 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:24:55 PM PDT 24
Peak memory 200820 kb
Host smart-344b5955-1502-49c5-9c6a-b5ad7728e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729519939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1729519939
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.245379070
Short name T207
Test name
Test status
Simulation time 1057918104 ps
CPU time 12.15 seconds
Started Aug 12 05:24:18 PM PDT 24
Finished Aug 12 05:24:30 PM PDT 24
Peak memory 200816 kb
Host smart-2a9ba280-ab3e-43c8-b01b-714076c569b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245379070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.245379070
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.38089388
Short name T452
Test name
Test status
Simulation time 101887516810 ps
CPU time 3035.98 seconds
Started Aug 12 05:24:27 PM PDT 24
Finished Aug 12 06:15:03 PM PDT 24
Peak memory 828180 kb
Host smart-3067be2c-b511-4800-bb1f-8941210c6ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38089388 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.38089388
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3890724538
Short name T6
Test name
Test status
Simulation time 1820692158 ps
CPU time 14.25 seconds
Started Aug 12 05:24:32 PM PDT 24
Finished Aug 12 05:24:47 PM PDT 24
Peak memory 200696 kb
Host smart-e16e07b6-4d42-475f-93d1-f148686dd912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890724538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3890724538
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.749231230
Short name T303
Test name
Test status
Simulation time 12077056 ps
CPU time 0.62 seconds
Started Aug 12 05:24:33 PM PDT 24
Finished Aug 12 05:24:34 PM PDT 24
Peak memory 196320 kb
Host smart-d1efe844-d4df-41c3-8fdb-6cc766a1aca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749231230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.749231230
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3492356747
Short name T9
Test name
Test status
Simulation time 717196646 ps
CPU time 41.84 seconds
Started Aug 12 05:24:38 PM PDT 24
Finished Aug 12 05:25:20 PM PDT 24
Peak memory 200708 kb
Host smart-4998caca-8ce6-4920-b017-c015dacdef94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492356747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3492356747
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.4083365025
Short name T369
Test name
Test status
Simulation time 4304984307 ps
CPU time 12.96 seconds
Started Aug 12 05:24:33 PM PDT 24
Finished Aug 12 05:24:46 PM PDT 24
Peak memory 200828 kb
Host smart-fee50597-e62b-4cc8-b98f-aed188aaca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083365025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.4083365025
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2885148131
Short name T176
Test name
Test status
Simulation time 1836387440 ps
CPU time 124.91 seconds
Started Aug 12 05:24:26 PM PDT 24
Finished Aug 12 05:26:31 PM PDT 24
Peak memory 463536 kb
Host smart-f23acb87-7feb-46bd-8dba-6896dec6b569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885148131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2885148131
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.274096867
Short name T391
Test name
Test status
Simulation time 1950855868 ps
CPU time 27.68 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 200600 kb
Host smart-af1450d7-3759-4aa5-9b13-daa55f27bd82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274096867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.274096867
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.330041844
Short name T254
Test name
Test status
Simulation time 4440005341 ps
CPU time 81.99 seconds
Started Aug 12 05:24:26 PM PDT 24
Finished Aug 12 05:25:48 PM PDT 24
Peak memory 200880 kb
Host smart-a9c51e51-104e-4e96-8bb9-f7830e0fd448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330041844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.330041844
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2706277371
Short name T225
Test name
Test status
Simulation time 1051831461 ps
CPU time 3.74 seconds
Started Aug 12 05:24:33 PM PDT 24
Finished Aug 12 05:24:36 PM PDT 24
Peak memory 200724 kb
Host smart-16a11b2d-af2b-4240-98ea-3c1b4a9e7e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706277371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2706277371
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2898266677
Short name T44
Test name
Test status
Simulation time 50792123747 ps
CPU time 653.55 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:35:13 PM PDT 24
Peak memory 200832 kb
Host smart-4ead80e7-4e0c-4174-ae01-856bcce0e0b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898266677 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2898266677
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3232692137
Short name T386
Test name
Test status
Simulation time 817432180 ps
CPU time 11.54 seconds
Started Aug 12 05:24:11 PM PDT 24
Finished Aug 12 05:24:22 PM PDT 24
Peak memory 200748 kb
Host smart-9c8b81a3-33c5-4f87-b611-b713d21ab253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232692137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3232692137
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.353331497
Short name T357
Test name
Test status
Simulation time 93380693 ps
CPU time 0.58 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:24:14 PM PDT 24
Peak memory 196788 kb
Host smart-807833ef-892f-4307-a983-3786820a7634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353331497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.353331497
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.961206360
Short name T274
Test name
Test status
Simulation time 5478295834 ps
CPU time 99.7 seconds
Started Aug 12 05:24:11 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 216164 kb
Host smart-d01b4b79-603e-430e-8ace-5badd0f91be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961206360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.961206360
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3146365622
Short name T198
Test name
Test status
Simulation time 13541138134 ps
CPU time 49.41 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:25:23 PM PDT 24
Peak memory 200872 kb
Host smart-776bf277-48ed-425d-b3c8-b03b7666f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146365622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3146365622
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.447193106
Short name T423
Test name
Test status
Simulation time 3521720852 ps
CPU time 553.8 seconds
Started Aug 12 05:24:16 PM PDT 24
Finished Aug 12 05:33:30 PM PDT 24
Peak memory 663640 kb
Host smart-cbac2b0e-9010-4edb-913b-e30c2461bd64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447193106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.447193106
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2841665090
Short name T484
Test name
Test status
Simulation time 55528975 ps
CPU time 0.8 seconds
Started Aug 12 05:24:32 PM PDT 24
Finished Aug 12 05:24:33 PM PDT 24
Peak memory 197344 kb
Host smart-f29ddcb6-9953-4bb8-a934-3e6c97bc80de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841665090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2841665090
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4110722524
Short name T154
Test name
Test status
Simulation time 38835275659 ps
CPU time 156.66 seconds
Started Aug 12 05:24:14 PM PDT 24
Finished Aug 12 05:26:50 PM PDT 24
Peak memory 200860 kb
Host smart-11ed4382-5df8-413f-b4c3-5018693ed65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110722524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4110722524
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2382688791
Short name T221
Test name
Test status
Simulation time 123757323 ps
CPU time 5.14 seconds
Started Aug 12 05:24:26 PM PDT 24
Finished Aug 12 05:24:31 PM PDT 24
Peak memory 200748 kb
Host smart-a5773cc6-6a86-4f88-8167-ac76db5ad895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382688791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2382688791
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3374732809
Short name T475
Test name
Test status
Simulation time 133826356801 ps
CPU time 584.3 seconds
Started Aug 12 05:24:27 PM PDT 24
Finished Aug 12 05:34:11 PM PDT 24
Peak memory 320820 kb
Host smart-7f08c349-4c02-40be-9503-adcd1c56efc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374732809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3374732809
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1898174567
Short name T493
Test name
Test status
Simulation time 7945923218 ps
CPU time 70.57 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:25:29 PM PDT 24
Peak memory 200912 kb
Host smart-bd49ef14-0ee8-4825-a076-ed8f4f80664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898174567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1898174567
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2574709246
Short name T342
Test name
Test status
Simulation time 24703350 ps
CPU time 0.59 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:24:35 PM PDT 24
Peak memory 195504 kb
Host smart-0d5cf6fc-75f1-4097-9376-a83afb04c160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574709246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2574709246
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3454090761
Short name T231
Test name
Test status
Simulation time 2559712015 ps
CPU time 47.4 seconds
Started Aug 12 05:24:13 PM PDT 24
Finished Aug 12 05:25:00 PM PDT 24
Peak memory 200852 kb
Host smart-d2c92e09-b147-43d5-8512-0256eaf82fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3454090761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3454090761
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4047508011
Short name T272
Test name
Test status
Simulation time 4899407869 ps
CPU time 787.99 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:37:20 PM PDT 24
Peak memory 707068 kb
Host smart-5b1215b5-40f6-43ad-9fdd-98e10c6b5554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047508011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4047508011
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4065021998
Short name T46
Test name
Test status
Simulation time 3717520162 ps
CPU time 35.96 seconds
Started Aug 12 05:24:25 PM PDT 24
Finished Aug 12 05:25:01 PM PDT 24
Peak memory 200820 kb
Host smart-226b77af-3744-435e-bc48-e6fd157e494b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065021998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4065021998
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2460353139
Short name T203
Test name
Test status
Simulation time 8474721751 ps
CPU time 143.26 seconds
Started Aug 12 05:24:30 PM PDT 24
Finished Aug 12 05:26:53 PM PDT 24
Peak memory 200780 kb
Host smart-4a0c1b3d-7b9b-4d2f-aa9f-1ae449772042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460353139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2460353139
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.340496870
Short name T195
Test name
Test status
Simulation time 849628215 ps
CPU time 14.3 seconds
Started Aug 12 05:24:29 PM PDT 24
Finished Aug 12 05:24:43 PM PDT 24
Peak memory 200764 kb
Host smart-29b505d0-8292-4cdf-a9ed-ee8f4c847c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340496870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.340496870
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3073678896
Short name T418
Test name
Test status
Simulation time 40200898100 ps
CPU time 527.69 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:33:22 PM PDT 24
Peak memory 200816 kb
Host smart-7c6bcd1d-d825-422c-b4cf-1d7a09e3b7ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073678896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3073678896
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2840261312
Short name T228
Test name
Test status
Simulation time 6250160192 ps
CPU time 81.23 seconds
Started Aug 12 05:24:33 PM PDT 24
Finished Aug 12 05:25:54 PM PDT 24
Peak memory 200836 kb
Host smart-e430c501-ce39-4f82-88ae-1e3ba2faef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840261312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2840261312
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.42820905
Short name T150
Test name
Test status
Simulation time 14808519 ps
CPU time 0.61 seconds
Started Aug 12 05:24:16 PM PDT 24
Finished Aug 12 05:24:17 PM PDT 24
Peak memory 197364 kb
Host smart-ee4e4692-10ae-42be-bf60-8790712153da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42820905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.42820905
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2419009279
Short name T443
Test name
Test status
Simulation time 3931845356 ps
CPU time 58.65 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:25:16 PM PDT 24
Peak memory 200700 kb
Host smart-6610a9b4-3199-4338-b5fd-97c1a70dd719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419009279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2419009279
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3604255538
Short name T138
Test name
Test status
Simulation time 6629991613 ps
CPU time 22.12 seconds
Started Aug 12 05:24:26 PM PDT 24
Finished Aug 12 05:24:48 PM PDT 24
Peak memory 200864 kb
Host smart-1314c358-1452-4001-9fcc-a092c86fb1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604255538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3604255538
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3993599457
Short name T209
Test name
Test status
Simulation time 26002434807 ps
CPU time 782.69 seconds
Started Aug 12 05:24:18 PM PDT 24
Finished Aug 12 05:37:21 PM PDT 24
Peak memory 688180 kb
Host smart-e13ebf5e-f625-414b-8a06-623463a13828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993599457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3993599457
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3991831861
Short name T499
Test name
Test status
Simulation time 2234962918 ps
CPU time 39.44 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:24:58 PM PDT 24
Peak memory 200884 kb
Host smart-31ca5a92-ff9c-4199-9bba-4670a3557bf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991831861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3991831861
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_smoke.1809875182
Short name T199
Test name
Test status
Simulation time 645737180 ps
CPU time 10.86 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 200748 kb
Host smart-48c8a7cb-c015-4bc4-babf-3b0787d916a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809875182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1809875182
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1862892969
Short name T326
Test name
Test status
Simulation time 12872971432 ps
CPU time 227.98 seconds
Started Aug 12 05:24:19 PM PDT 24
Finished Aug 12 05:28:07 PM PDT 24
Peak memory 200876 kb
Host smart-223f54fe-21dc-4890-abf9-1afabcdaf871
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862892969 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1862892969
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3737665447
Short name T340
Test name
Test status
Simulation time 767064929 ps
CPU time 42.09 seconds
Started Aug 12 05:24:17 PM PDT 24
Finished Aug 12 05:24:59 PM PDT 24
Peak memory 200828 kb
Host smart-c946c3a1-33ee-4dab-ad1a-fc912a7e184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737665447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3737665447
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1205351066
Short name T377
Test name
Test status
Simulation time 40241550 ps
CPU time 0.59 seconds
Started Aug 12 05:24:20 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 196456 kb
Host smart-c9ad92f5-a718-41dc-904b-b5c62719801b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205351066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1205351066
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.391291093
Short name T477
Test name
Test status
Simulation time 1289803346 ps
CPU time 68.16 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:25:23 PM PDT 24
Peak memory 200756 kb
Host smart-578aee29-8b2c-4b43-ac8e-a5fa2f447cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391291093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.391291093
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.260279419
Short name T148
Test name
Test status
Simulation time 2408920632 ps
CPU time 20.68 seconds
Started Aug 12 05:24:36 PM PDT 24
Finished Aug 12 05:24:57 PM PDT 24
Peak memory 200836 kb
Host smart-2e149c23-1b16-452f-beb7-cc1d2dfd1cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260279419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.260279419
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1468462041
Short name T358
Test name
Test status
Simulation time 3727977115 ps
CPU time 605.14 seconds
Started Aug 12 05:24:32 PM PDT 24
Finished Aug 12 05:34:37 PM PDT 24
Peak memory 683992 kb
Host smart-4e5257a5-4085-4219-be16-c1ac6b00ab37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468462041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1468462041
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3478349473
Short name T211
Test name
Test status
Simulation time 2114470138 ps
CPU time 120.34 seconds
Started Aug 12 05:24:34 PM PDT 24
Finished Aug 12 05:26:35 PM PDT 24
Peak memory 200612 kb
Host smart-243f7788-8bd3-4da0-9a66-7fe53183cadd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478349473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3478349473
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2561454669
Short name T205
Test name
Test status
Simulation time 10708058198 ps
CPU time 146.57 seconds
Started Aug 12 05:24:12 PM PDT 24
Finished Aug 12 05:26:38 PM PDT 24
Peak memory 209044 kb
Host smart-48f5fa98-682d-440a-88e5-26cfe3e2e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561454669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2561454669
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1655312624
Short name T334
Test name
Test status
Simulation time 264252984 ps
CPU time 5.42 seconds
Started Aug 12 05:24:15 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 200740 kb
Host smart-821b6bcd-e67c-4d75-9975-734b68b1a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655312624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1655312624
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4209272924
Short name T213
Test name
Test status
Simulation time 68473906404 ps
CPU time 2642.37 seconds
Started Aug 12 05:24:20 PM PDT 24
Finished Aug 12 06:08:23 PM PDT 24
Peak memory 787796 kb
Host smart-2a7d0a02-c820-4b54-8732-13496bb34efb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209272924 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4209272924
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1054768744
Short name T461
Test name
Test status
Simulation time 7417296390 ps
CPU time 127.53 seconds
Started Aug 12 05:24:22 PM PDT 24
Finished Aug 12 05:26:30 PM PDT 24
Peak memory 200920 kb
Host smart-1c0621e3-96ee-4b45-9d4f-e6be18d948c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054768744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1054768744
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1755746713
Short name T458
Test name
Test status
Simulation time 15055457 ps
CPU time 0.6 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:23:51 PM PDT 24
Peak memory 196728 kb
Host smart-b4f36814-86ea-4406-98de-2c5eb7279495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755746713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1755746713
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2966620605
Short name T417
Test name
Test status
Simulation time 805715274 ps
CPU time 11.39 seconds
Started Aug 12 05:23:19 PM PDT 24
Finished Aug 12 05:23:31 PM PDT 24
Peak memory 200672 kb
Host smart-0e18186c-2d6b-4960-9a56-feb71e7c0890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966620605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2966620605
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.4019936361
Short name T180
Test name
Test status
Simulation time 12445357275 ps
CPU time 39.92 seconds
Started Aug 12 05:23:16 PM PDT 24
Finished Aug 12 05:23:56 PM PDT 24
Peak memory 200884 kb
Host smart-4b5cd2d0-c0b8-4ae2-8439-e072aa4ce979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019936361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4019936361
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2722387355
Short name T403
Test name
Test status
Simulation time 7420583591 ps
CPU time 1268.24 seconds
Started Aug 12 05:23:35 PM PDT 24
Finished Aug 12 05:44:44 PM PDT 24
Peak memory 730576 kb
Host smart-e7a9b847-d7a5-4a6c-934e-1430d7dc09e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722387355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2722387355
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.848229348
Short name T428
Test name
Test status
Simulation time 3209390495 ps
CPU time 172.41 seconds
Started Aug 12 05:23:26 PM PDT 24
Finished Aug 12 05:26:18 PM PDT 24
Peak memory 200784 kb
Host smart-9db8171c-3d77-4e9f-8dc0-a35cc61580fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848229348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.848229348
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2816467540
Short name T333
Test name
Test status
Simulation time 8630955673 ps
CPU time 56.23 seconds
Started Aug 12 05:23:32 PM PDT 24
Finished Aug 12 05:24:28 PM PDT 24
Peak memory 200840 kb
Host smart-8f544fc9-fc88-42ea-9af0-b6c4c98582dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816467540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2816467540
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3710455353
Short name T389
Test name
Test status
Simulation time 1242911726 ps
CPU time 15.11 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:23:53 PM PDT 24
Peak memory 200780 kb
Host smart-d2bda341-670f-4192-a3ed-1e5361b83ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710455353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3710455353
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4141106580
Short name T125
Test name
Test status
Simulation time 84789467827 ps
CPU time 2138.78 seconds
Started Aug 12 05:23:46 PM PDT 24
Finished Aug 12 05:59:25 PM PDT 24
Peak memory 764072 kb
Host smart-fa555cbd-faa5-4ace-b491-f512d90d10d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141106580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4141106580
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1873001357
Short name T65
Test name
Test status
Simulation time 6987095388 ps
CPU time 435.62 seconds
Started Aug 12 05:23:20 PM PDT 24
Finished Aug 12 05:30:35 PM PDT 24
Peak memory 352680 kb
Host smart-2485edb2-ccef-4299-a520-8b3803795a84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873001357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1873001357
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.578282032
Short name T410
Test name
Test status
Simulation time 20621090056 ps
CPU time 76.04 seconds
Started Aug 12 05:23:53 PM PDT 24
Finished Aug 12 05:25:09 PM PDT 24
Peak memory 200792 kb
Host smart-dbeda955-ba4a-4842-a94c-39f2415dbbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578282032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.578282032
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3026727304
Short name T155
Test name
Test status
Simulation time 27473369 ps
CPU time 0.63 seconds
Started Aug 12 05:23:22 PM PDT 24
Finished Aug 12 05:23:23 PM PDT 24
Peak memory 196704 kb
Host smart-ecd564cb-bd12-42be-a3fc-dde3c6c75f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026727304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3026727304
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2679939744
Short name T248
Test name
Test status
Simulation time 789718614 ps
CPU time 45.28 seconds
Started Aug 12 05:24:05 PM PDT 24
Finished Aug 12 05:24:50 PM PDT 24
Peak memory 200804 kb
Host smart-1d92fe37-badd-4e79-9b0d-f55c1b956171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679939744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2679939744
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.721401308
Short name T489
Test name
Test status
Simulation time 1662605367 ps
CPU time 29.75 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:24:08 PM PDT 24
Peak memory 200752 kb
Host smart-d8c740a2-ecd5-43e7-bbb7-f851c001a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721401308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.721401308
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1573748278
Short name T85
Test name
Test status
Simulation time 20264599416 ps
CPU time 945.33 seconds
Started Aug 12 05:23:21 PM PDT 24
Finished Aug 12 05:39:06 PM PDT 24
Peak memory 707968 kb
Host smart-d8ba93f4-556c-454c-8a3c-fce20b48ab96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573748278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1573748278
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.357495124
Short name T217
Test name
Test status
Simulation time 5020123157 ps
CPU time 129.74 seconds
Started Aug 12 05:23:39 PM PDT 24
Finished Aug 12 05:25:49 PM PDT 24
Peak memory 200772 kb
Host smart-1efebe53-75cb-4779-823b-2fd4be55c247
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357495124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.357495124
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2285261875
Short name T197
Test name
Test status
Simulation time 2130573423 ps
CPU time 5.71 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:23:44 PM PDT 24
Peak memory 200724 kb
Host smart-2e2c998e-1989-423e-94c7-10965f3f6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285261875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2285261875
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.165135422
Short name T223
Test name
Test status
Simulation time 4244680137 ps
CPU time 12.03 seconds
Started Aug 12 05:23:33 PM PDT 24
Finished Aug 12 05:23:45 PM PDT 24
Peak memory 200888 kb
Host smart-227e2794-3d7a-45a7-bc24-d07874b17066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165135422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.165135422
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1037108797
Short name T337
Test name
Test status
Simulation time 10644744683 ps
CPU time 113.02 seconds
Started Aug 12 05:23:40 PM PDT 24
Finished Aug 12 05:25:33 PM PDT 24
Peak memory 200864 kb
Host smart-7eb11a5f-eb70-4ab2-8fba-080b08d6b5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037108797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1037108797
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2543390263
Short name T492
Test name
Test status
Simulation time 12152105 ps
CPU time 0.57 seconds
Started Aug 12 05:23:40 PM PDT 24
Finished Aug 12 05:23:41 PM PDT 24
Peak memory 197408 kb
Host smart-7398d853-75ca-4a64-90d5-0754157e9c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543390263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2543390263
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.377972072
Short name T375
Test name
Test status
Simulation time 749666612 ps
CPU time 39.95 seconds
Started Aug 12 05:24:00 PM PDT 24
Finished Aug 12 05:24:40 PM PDT 24
Peak memory 200756 kb
Host smart-09b7c5c3-b7fd-48db-b6c1-59648d694500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377972072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.377972072
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2086042521
Short name T151
Test name
Test status
Simulation time 4079342849 ps
CPU time 56.41 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:24:34 PM PDT 24
Peak memory 200812 kb
Host smart-403c7bbf-ed71-4871-84f9-6cfcf712d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086042521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2086042521
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3325136081
Short name T392
Test name
Test status
Simulation time 17514443288 ps
CPU time 310.8 seconds
Started Aug 12 05:23:38 PM PDT 24
Finished Aug 12 05:28:49 PM PDT 24
Peak memory 486668 kb
Host smart-97f37132-3237-4f29-bbc7-ffca19d801a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3325136081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3325136081
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3499757703
Short name T34
Test name
Test status
Simulation time 714164227 ps
CPU time 9.3 seconds
Started Aug 12 05:23:41 PM PDT 24
Finished Aug 12 05:23:51 PM PDT 24
Peak memory 200812 kb
Host smart-a7897647-1b89-478c-bb25-9d15c3647090
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499757703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3499757703
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1001697743
Short name T252
Test name
Test status
Simulation time 11547759353 ps
CPU time 155.6 seconds
Started Aug 12 05:23:29 PM PDT 24
Finished Aug 12 05:26:05 PM PDT 24
Peak memory 200704 kb
Host smart-6761081e-3cc5-4034-ba0d-1174d184d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001697743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1001697743
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3749186998
Short name T415
Test name
Test status
Simulation time 540265861 ps
CPU time 11.34 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:23:35 PM PDT 24
Peak memory 200816 kb
Host smart-19214887-5cad-4b09-8532-bf704e4d2f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749186998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3749186998
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.207788414
Short name T96
Test name
Test status
Simulation time 5703331879 ps
CPU time 78.35 seconds
Started Aug 12 05:23:40 PM PDT 24
Finished Aug 12 05:24:58 PM PDT 24
Peak memory 200804 kb
Host smart-bd1a6c89-b8e1-4520-b8e9-b5a63fa5e4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207788414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.207788414
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3611812888
Short name T505
Test name
Test status
Simulation time 21692993 ps
CPU time 0.55 seconds
Started Aug 12 05:23:23 PM PDT 24
Finished Aug 12 05:23:24 PM PDT 24
Peak memory 196336 kb
Host smart-53cd8d65-64be-40f9-bcd9-0f301dcc9f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611812888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3611812888
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2688633749
Short name T31
Test name
Test status
Simulation time 35844623655 ps
CPU time 102.36 seconds
Started Aug 12 05:23:39 PM PDT 24
Finished Aug 12 05:25:22 PM PDT 24
Peak memory 200832 kb
Host smart-e1a595d4-26b6-4518-bdce-e3bb5f81ad47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2688633749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2688633749
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3517350468
Short name T153
Test name
Test status
Simulation time 11399009448 ps
CPU time 31.02 seconds
Started Aug 12 05:23:31 PM PDT 24
Finished Aug 12 05:24:03 PM PDT 24
Peak memory 200836 kb
Host smart-b27829d3-36d0-45bb-862c-2065027f9748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517350468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3517350468
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2020062397
Short name T506
Test name
Test status
Simulation time 62559711536 ps
CPU time 1670.45 seconds
Started Aug 12 05:23:58 PM PDT 24
Finished Aug 12 05:51:49 PM PDT 24
Peak memory 800828 kb
Host smart-da162693-a89c-40fe-b448-dee61d247a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020062397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2020062397
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.413118288
Short name T181
Test name
Test status
Simulation time 33108394815 ps
CPU time 104.33 seconds
Started Aug 12 05:23:45 PM PDT 24
Finished Aug 12 05:25:30 PM PDT 24
Peak memory 200856 kb
Host smart-4b3367c0-232f-466e-a81e-20c627df05eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413118288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.413118288
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1719325904
Short name T42
Test name
Test status
Simulation time 4934403650 ps
CPU time 33.13 seconds
Started Aug 12 05:23:41 PM PDT 24
Finished Aug 12 05:24:15 PM PDT 24
Peak memory 200840 kb
Host smart-4f2fc994-9c49-44f5-b984-f13a2bd15d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719325904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1719325904
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3726200477
Short name T189
Test name
Test status
Simulation time 4241382276 ps
CPU time 12.52 seconds
Started Aug 12 05:23:39 PM PDT 24
Finished Aug 12 05:23:52 PM PDT 24
Peak memory 200816 kb
Host smart-fe0ea247-81a1-45fc-9d32-d76603fed7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726200477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3726200477
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2714271683
Short name T247
Test name
Test status
Simulation time 12610004 ps
CPU time 0.56 seconds
Started Aug 12 05:23:54 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 195680 kb
Host smart-be84e56a-6cb7-4edb-9322-464c1e983251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714271683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2714271683
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2580763286
Short name T261
Test name
Test status
Simulation time 6063793658 ps
CPU time 84.25 seconds
Started Aug 12 05:23:24 PM PDT 24
Finished Aug 12 05:24:48 PM PDT 24
Peak memory 217108 kb
Host smart-e8b427f5-57f5-4809-9233-e1daefca5b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580763286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2580763286
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.23193326
Short name T508
Test name
Test status
Simulation time 13272758225 ps
CPU time 60.91 seconds
Started Aug 12 05:23:52 PM PDT 24
Finished Aug 12 05:24:53 PM PDT 24
Peak memory 200888 kb
Host smart-bfca164d-ac98-484c-86a8-f3412acd6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23193326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.23193326
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3012646472
Short name T171
Test name
Test status
Simulation time 26322087549 ps
CPU time 837.59 seconds
Started Aug 12 05:23:48 PM PDT 24
Finished Aug 12 05:37:46 PM PDT 24
Peak memory 720044 kb
Host smart-29297496-5fb3-451b-9abf-3fff299773c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012646472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3012646472
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.293296552
Short name T366
Test name
Test status
Simulation time 4662180493 ps
CPU time 67.63 seconds
Started Aug 12 05:23:43 PM PDT 24
Finished Aug 12 05:24:51 PM PDT 24
Peak memory 200828 kb
Host smart-4471ec73-7637-4c8b-bc3d-3c14409ba93c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293296552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.293296552
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.239217669
Short name T491
Test name
Test status
Simulation time 1850107847 ps
CPU time 105.98 seconds
Started Aug 12 05:23:42 PM PDT 24
Finished Aug 12 05:25:28 PM PDT 24
Peak memory 200756 kb
Host smart-fb72922d-e45d-4cd1-8d4d-14e144320756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239217669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.239217669
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1181041548
Short name T177
Test name
Test status
Simulation time 2260790738 ps
CPU time 13.79 seconds
Started Aug 12 05:23:21 PM PDT 24
Finished Aug 12 05:23:34 PM PDT 24
Peak memory 200808 kb
Host smart-eece9770-6859-487e-8924-a6d6a2798b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181041548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1181041548
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1459162095
Short name T28
Test name
Test status
Simulation time 15355771964 ps
CPU time 1615.55 seconds
Started Aug 12 05:23:47 PM PDT 24
Finished Aug 12 05:50:43 PM PDT 24
Peak memory 796696 kb
Host smart-01520439-5c7b-49a9-9b05-5f44e087de47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459162095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1459162095
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2542475778
Short name T13
Test name
Test status
Simulation time 9975944667 ps
CPU time 159.95 seconds
Started Aug 12 05:23:50 PM PDT 24
Finished Aug 12 05:26:30 PM PDT 24
Peak memory 245852 kb
Host smart-046dbd54-5d0a-4eff-a87a-12be9d810171
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542475778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2542475778
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.228862661
Short name T122
Test name
Test status
Simulation time 5777651851 ps
CPU time 105.1 seconds
Started Aug 12 05:23:59 PM PDT 24
Finished Aug 12 05:25:44 PM PDT 24
Peak memory 200824 kb
Host smart-ab7df17c-1520-4a25-ab71-69d6e8085872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228862661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.228862661
Directory /workspace/9.hmac_wipe_secret/latest
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