Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16656171	1			T1	5309		T2	16596		T3	254208
all_values[1]	16656171	1			T1	5309		T2	16596		T3	254208
all_values[2]	16656171	1			T1	5309		T2	16596		T3	254208

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270074

1

T1

276

T2

2

T3

4991

auto[1]

49698439

1

T1

15651

T2

49786

T3

757633

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42747230

1

T1

12722

T2

37895

T3

639065

auto[1]

7221283

1

T1

3205

T2

11893

T3

123559

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	95110	1			T3	4727		T4	3		T12	462
all_values[0]	auto[0]	auto[1]	293	1			T3	11		T4	3		T6	2
all_values[0]	auto[1]	auto[0]	16542690	1			T1	5301		T2	16594		T3	249246
all_values[0]	auto[1]	auto[1]	18078	1			T1	8		T2	2		T3	224
all_values[1]	auto[0]	auto[0]	97000	1			T3	133		T4	599		T6	162
all_values[1]	auto[0]	auto[1]	192	1			T3	6		T4	2		T18	3
all_values[1]	auto[1]	auto[0]	16558727	1			T1	5309		T2	16596		T3	254061
all_values[1]	auto[1]	auto[1]	252	1			T3	8		T4	1		T16	5
all_values[2]	auto[0]	auto[0]	40433	1			T1	1		T2	1		T3	15
all_values[2]	auto[0]	auto[1]	37046	1			T1	275		T2	1		T3	99
all_values[2]	auto[1]	auto[0]	9413270	1			T1	2111		T2	4704		T3	130883
all_values[2]	auto[1]	auto[1]	7165422	1			T1	2922		T2	11890		T3	123211