Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101549

1

T1

18

T2

16

T3

2096

auto[1]

113350

1

T1

10

T2

12

T3

2236

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	81132	1			T1	13		T2	10		T3	1653
len_1026_2046	5232	1			T3	146		T5	2		T6	1
len_514_1022	2954	1			T3	38		T6	2		T22	1
len_2_510	3408	1			T3	20		T6	1		T13	2
len_2056	144	1			T6	3		T18	6		T36	3
len_2048	297	1			T3	1		T6	2		T13	1
len_2040	155	1			T3	3		T6	6		T132	3
len_1032	156	1			T18	2		T36	2		T132	3
len_1024	1821	1			T3	6		T6	3		T16	5
len_1016	156	1			T3	6		T6	1		T36	3
len_520	197	1			T3	4		T6	2		T18	4
len_512	286	1			T3	6		T6	1		T16	8
len_504	200	1			T3	1		T18	6		T39	2
len_8	1099	1			T3	37		T18	18		T36	5
len_0	10213	1			T1	1		T2	4		T3	245

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

121

1

T14

2

T16

3

T35

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	39738	1			T1	8		T2	5		T3	760
auto[0]	len_1026_2046	2290	1			T3	96		T5	2		T13	1
auto[0]	len_514_1022	1730	1			T3	17		T22	1		T16	42
auto[0]	len_2_510	2249	1			T3	9		T13	1		T22	2
auto[0]	len_2056	70	1			T6	2		T18	1		T36	1
auto[0]	len_2048	169	1			T13	1		T16	1		T18	1
auto[0]	len_2040	88	1			T3	2		T6	1		T132	1
auto[0]	len_1032	94	1			T18	2		T36	1		T132	3
auto[0]	len_1024	247	1			T3	2		T16	3		T18	1
auto[0]	len_1016	94	1			T3	4		T6	1		T36	2
auto[0]	len_520	87	1			T3	3		T6	1		T18	2
auto[0]	len_512	173	1			T3	2		T16	6		T36	3
auto[0]	len_504	105	1			T18	1		T81	2		T40	1
auto[0]	len_8	25	1			T76	1		T133	1		T134	1
auto[0]	len_0	3616	1			T1	1		T2	3		T3	153
auto[1]	len_2050_plus	41394	1			T1	5		T2	5		T3	893
auto[1]	len_1026_2046	2942	1			T3	50		T6	1		T13	1
auto[1]	len_514_1022	1224	1			T3	21		T6	2		T16	360
auto[1]	len_2_510	1159	1			T3	11		T6	1		T13	1
auto[1]	len_2056	74	1			T6	1		T18	5		T36	2
auto[1]	len_2048	128	1			T3	1		T6	2		T14	1
auto[1]	len_2040	67	1			T3	1		T6	5		T132	2
auto[1]	len_1032	62	1			T36	1		T77	1		T135	1
auto[1]	len_1024	1574	1			T3	4		T6	3		T16	2
auto[1]	len_1016	62	1			T3	2		T36	1		T40	2
auto[1]	len_520	110	1			T3	1		T6	1		T18	2
auto[1]	len_512	113	1			T3	4		T6	1		T16	2
auto[1]	len_504	95	1			T3	1		T18	5		T39	2
auto[1]	len_8	1074	1			T3	37		T18	18		T36	5
auto[1]	len_0	6597	1			T2	1		T3	92		T4	4

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

69

1

T16

3

T35

2

T40

3

auto[1]

len_upper

52

1

T14

2

T39

2

T136

3