Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4203639 1 T1 7 T2 592 T3 57301
auto[1] 2637998 1 T1 8 T2 2123 T3 51506


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2557127 1 T1 8 T2 1175 T3 54277
auto[1] 4284510 1 T1 7 T2 1540 T3 54530


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2997084 1 T1 9 T2 2269 T3 7649
auto[1] 3844553 1 T1 6 T2 446 T3 101158


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4191628 1 T1 10 T2 1809 T3 49320
auto[1] 2650009 1 T1 5 T2 906 T3 59487


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6266200 1 T1 12 T2 2189 T3 106229
fifo_depth[1] 109275 1 T2 144 T3 1121 T4 80
fifo_depth[2] 78966 1 T1 1 T2 141 T3 712
fifo_depth[3] 61298 1 T2 111 T3 265 T4 8
fifo_depth[4] 55140 1 T2 77 T3 244 T4 1
fifo_depth[5] 43786 1 T2 40 T3 55 T5 1
fifo_depth[6] 35284 1 T2 12 T3 47 T6 16
fifo_depth[7] 23274 1 T1 1 T2 1 T3 25


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 575437 1 T1 3 T2 526 T3 2578
auto[1] 6266200 1 T1 12 T2 2189 T3 106229


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6835114 1 T1 15 T2 2715 T3 108807
auto[1] 6523 1 T16 799 T21 15 T138 181


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 17670 1 T3 99 T5 2 T13 417
auto[0] auto[0] auto[0] auto[0] auto[1] 15802 1 T3 78 T4 46 T5 1
auto[0] auto[0] auto[0] auto[1] auto[0] 26385 1 T3 3 T4 30 T5 1
auto[0] auto[0] auto[0] auto[1] auto[1] 21296 1 T2 200 T3 8 T4 1
auto[0] auto[0] auto[1] auto[0] auto[0] 128193 1 T3 92 T14 1 T22 7
auto[0] auto[0] auto[1] auto[0] auto[1] 29769 1 T3 41 T13 232 T14 1
auto[0] auto[0] auto[1] auto[1] auto[0] 20642 1 T1 1 T2 326 T3 62
auto[0] auto[0] auto[1] auto[1] auto[1] 29808 1 T1 1 T3 49 T14 1
auto[0] auto[1] auto[0] auto[0] auto[0] 26651 1 T3 367 T5 1 T6 36
auto[0] auto[1] auto[0] auto[0] auto[1] 36061 1 T3 37 T4 22 T15 1
auto[0] auto[1] auto[0] auto[1] auto[0] 33314 1 T3 193 T5 1 T13 299
auto[0] auto[1] auto[0] auto[1] auto[1] 34380 1 T3 416 T4 13 T5 3
auto[0] auto[1] auto[1] auto[0] auto[0] 47344 1 T3 259 T6 5 T13 94
auto[0] auto[1] auto[1] auto[0] auto[1] 39287 1 T3 436 T5 2 T6 9
auto[0] auto[1] auto[1] auto[1] auto[0] 34693 1 T1 1 T3 86 T6 8
auto[0] auto[1] auto[1] auto[1] auto[1] 34142 1 T3 352 T6 44 T13 66
auto[1] auto[0] auto[0] auto[0] auto[0] 158032 1 T1 1 T3 1149 T4 5
auto[1] auto[0] auto[0] auto[0] auto[1] 137520 1 T2 1 T3 1464 T4 798
auto[1] auto[0] auto[0] auto[1] auto[0] 147074 1 T1 3 T3 581 T4 486
auto[1] auto[0] auto[0] auto[1] auto[1] 151886 1 T2 531 T3 804 T4 75
auto[1] auto[0] auto[1] auto[0] auto[0] 1691184 1 T1 1 T2 1 T3 1126
auto[1] auto[0] auto[1] auto[0] auto[1] 144361 1 T1 1 T2 169 T3 464
auto[1] auto[0] auto[1] auto[1] auto[0] 145979 1 T2 1041 T3 913 T5 1
auto[1] auto[0] auto[1] auto[1] auto[1] 131483 1 T1 1 T3 716 T6 13
auto[1] auto[1] auto[0] auto[0] auto[0] 403355 1 T1 2 T2 417 T3 18299
auto[1] auto[1] auto[0] auto[0] auto[1] 390069 1 T1 1 T2 1 T3 8427
auto[1] auto[1] auto[0] auto[1] auto[0] 454985 1 T1 1 T2 24 T3 9683
auto[1] auto[1] auto[0] auto[1] auto[1] 502647 1 T2 1 T3 12669 T4 594
auto[1] auto[1] auto[1] auto[0] auto[0] 467203 1 T3 8637 T4 2 T5 3
auto[1] auto[1] auto[1] auto[0] auto[1] 471138 1 T1 1 T2 3 T3 16326
auto[1] auto[1] auto[1] auto[1] auto[0] 388924 1 T3 7771 T4 363 T5 2
auto[1] auto[1] auto[1] auto[1] auto[1] 480360 1 T3 17200 T4 3 T12 1


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 175415 1 T1 1 T3 1248 T4 5
auto[0] auto[0] auto[0] auto[0] auto[1] 153066 1 T2 1 T3 1542 T4 844
auto[0] auto[0] auto[0] auto[1] auto[0] 173247 1 T1 3 T3 584 T4 516
auto[0] auto[0] auto[0] auto[1] auto[1] 172906 1 T2 731 T3 812 T4 76
auto[0] auto[0] auto[1] auto[0] auto[0] 1818743 1 T1 1 T2 1 T3 1218
auto[0] auto[0] auto[1] auto[0] auto[1] 173035 1 T1 1 T2 169 T3 505
auto[0] auto[0] auto[1] auto[1] auto[0] 166426 1 T1 1 T2 1367 T3 975
auto[0] auto[0] auto[1] auto[1] auto[1] 160051 1 T1 2 T3 765 T6 13
auto[0] auto[1] auto[0] auto[0] auto[0] 429514 1 T1 2 T2 417 T3 18666
auto[0] auto[1] auto[0] auto[0] auto[1] 425941 1 T1 1 T2 1 T3 8464
auto[0] auto[1] auto[0] auto[1] auto[0] 487748 1 T1 1 T2 24 T3 9876
auto[0] auto[1] auto[0] auto[1] auto[1] 536684 1 T2 1 T3 13085 T4 607
auto[0] auto[1] auto[1] auto[0] auto[0] 514328 1 T3 8896 T4 2 T5 3
auto[0] auto[1] auto[1] auto[0] auto[1] 510187 1 T1 1 T2 3 T3 16762
auto[0] auto[1] auto[1] auto[1] auto[0] 423474 1 T1 1 T3 7857 T4 363
auto[0] auto[1] auto[1] auto[1] auto[1] 514349 1 T3 17552 T4 3 T12 1
auto[1] auto[0] auto[0] auto[0] auto[0] 287 1 T138 2 T93 5 T139 18
auto[1] auto[0] auto[0] auto[0] auto[1] 256 1 T16 34 T138 25 T140 8
auto[1] auto[0] auto[0] auto[1] auto[0] 212 1 T16 4 T138 12 T141 34
auto[1] auto[0] auto[0] auto[1] auto[1] 276 1 T16 2 T135 6 T142 73
auto[1] auto[0] auto[1] auto[0] auto[0] 634 1 T16 22 T135 7 T142 293
auto[1] auto[0] auto[1] auto[0] auto[1] 1095 1 T16 7 T21 5 T138 114
auto[1] auto[0] auto[1] auto[1] auto[0] 195 1 T16 3 T138 25 T140 51
auto[1] auto[0] auto[1] auto[1] auto[1] 1240 1 T21 10 T138 1 T38 12
auto[1] auto[1] auto[0] auto[0] auto[0] 492 1 T16 75 T143 110 T142 248
auto[1] auto[1] auto[0] auto[0] auto[1] 189 1 T16 4 T138 1 T135 6
auto[1] auto[1] auto[0] auto[1] auto[0] 551 1 T16 516 T144 1 T145 34
auto[1] auto[1] auto[0] auto[1] auto[1] 343 1 T16 132 T138 1 T143 28
auto[1] auto[1] auto[1] auto[0] auto[0] 219 1 T141 5 T142 3 T139 8
auto[1] auto[1] auto[1] auto[0] auto[1] 238 1 T38 16 T143 5 T142 26
auto[1] auto[1] auto[1] auto[1] auto[0] 143 1 T38 44 T139 11 T146 26
auto[1] auto[1] auto[1] auto[1] auto[1] 153 1 T147 9 T139 8 T20 15


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 158032 1 T1 1 T3 1149 T4 5
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 137520 1 T2 1 T3 1464 T4 798
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 147074 1 T1 3 T3 581 T4 486
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 151886 1 T2 531 T3 804 T4 75
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1691184 1 T1 1 T2 1 T3 1126
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 144361 1 T1 1 T2 169 T3 464
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 145979 1 T2 1041 T3 913 T5 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 131483 1 T1 1 T3 716 T6 13
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 403355 1 T1 2 T2 417 T3 18299
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 390069 1 T1 1 T2 1 T3 8427
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 454985 1 T1 1 T2 24 T3 9683
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 502647 1 T2 1 T3 12669 T4 594
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 467203 1 T3 8637 T4 2 T5 3
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 471138 1 T1 1 T2 3 T3 16326
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 388924 1 T3 7771 T4 363 T5 2
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 480360 1 T3 17200 T4 3 T12 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3184 1 T3 9 T13 64 T22 9
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 2582 1 T3 17 T4 35 T13 11
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3483 1 T3 1 T4 24 T13 6
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 2822 1 T2 52 T4 1 T13 17
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 38401 1 T3 31 T22 2 T34 12
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3097 1 T3 10 T13 46 T16 5
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3254 1 T2 92 T3 4 T16 219
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 2628 1 T16 53 T18 24 T35 28
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 4700 1 T3 184 T6 5 T13 11
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6020 1 T3 14 T4 13 T16 10
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6594 1 T3 96 T13 55 T18 169
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6281 1 T3 228 T4 7 T13 8
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 7757 1 T3 107 T13 10 T16 6
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6377 1 T3 192 T5 1 T13 89
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5522 1 T3 26 T6 1 T13 9
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6573 1 T3 202 T6 4 T13 10
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2162 1 T3 6 T13 60 T22 5
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 1653 1 T3 22 T4 9 T13 17
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2578 1 T4 3 T13 11 T22 4
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2063 1 T2 50 T3 1 T13 14
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 24124 1 T3 29 T22 5 T34 5
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2242 1 T3 7 T13 47 T16 7
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2586 1 T2 91 T3 6 T16 252
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 1933 1 T3 29 T14 1 T16 54
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 3757 1 T3 95 T6 7 T13 11
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4873 1 T3 12 T4 8 T16 10
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5118 1 T3 47 T13 54 T18 84
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4809 1 T3 125 T4 3 T13 5
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6215 1 T3 44 T13 13 T16 7
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5315 1 T3 158 T6 1 T13 92
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4211 1 T1 1 T3 22 T13 20
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5327 1 T3 109 T6 8 T13 11
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1432 1 T3 7 T13 63 T18 12
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1156 1 T3 5 T4 1 T13 14
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1810 1 T3 2 T4 3 T5 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1286 1 T2 48 T3 1 T13 19
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 17417 1 T3 13 T16 1 T34 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1603 1 T3 10 T13 42 T16 7
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1974 1 T2 63 T3 6 T16 241
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1475 1 T16 49 T18 3 T35 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 2989 1 T3 39 T6 6 T13 8
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4143 1 T3 5 T4 1 T16 14
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4442 1 T3 20 T13 41 T18 23
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3916 1 T3 41 T4 3 T13 7
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5391 1 T3 29 T6 2 T13 11
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4278 1 T3 45 T6 3 T13 98
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3536 1 T3 10 T13 25 T18 11
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4450 1 T3 32 T6 6 T13 8
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 1446 1 T3 41 T13 55 T18 3
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1131 1 T3 16 T4 1 T13 13
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1890 1 T13 9 T16 6 T18 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1467 1 T2 32 T13 16 T36 3
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 13165 1 T3 13 T36 2 T39 5
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1697 1 T3 9 T13 37 T16 6
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2048 1 T2 45 T3 22 T15 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 1481 1 T3 20 T16 48 T18 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 2821 1 T3 28 T6 7 T13 10
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3729 1 T3 3 T15 1 T16 12
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4188 1 T3 10 T13 47 T18 8
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3562 1 T3 11 T13 6 T16 9
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4952 1 T3 24 T13 15 T16 40
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3883 1 T3 19 T6 1 T13 93
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3566 1 T3 21 T6 2 T13 17
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4114 1 T3 7 T6 6 T13 7
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 923 1 T3 5 T13 54 T21 23
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 792 1 T3 3 T13 13 T16 8
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1378 1 T13 8 T15 1 T16 17
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 862 1 T2 11 T13 14 T16 3
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9845 1 T3 6 T39 6 T21 28
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1203 1 T3 3 T13 29 T16 7
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1295 1 T2 29 T3 3 T16 109
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1165 1 T16 55 T21 98 T85 11
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2299 1 T3 1 T6 3 T13 17
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3225 1 T16 12 T36 1 T39 4
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3593 1 T3 5 T5 1 T13 36
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3052 1 T3 7 T13 9 T16 10
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4360 1 T3 11 T13 9 T16 38
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3246 1 T3 6 T6 1 T13 68
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 2857 1 T3 4 T6 1 T13 26
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3691 1 T3 1 T6 2 T13 5
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 735 1 T3 3 T13 53 T21 21
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 614 1 T3 8 T13 9 T16 2
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1319 1 T13 5 T16 2 T21 16
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1120 1 T2 6 T13 13 T16 7
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7087 1 T14 1 T39 5 T21 20
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1218 1 T3 1 T13 17 T15 1
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1067 1 T2 6 T3 6 T16 4
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 933 1 T16 35 T21 49 T85 11
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 1930 1 T3 1 T6 3 T13 8
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2630 1 T3 1 T16 10 T39 5
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2790 1 T3 5 T13 28 T21 49
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2448 1 T3 2 T13 7 T16 8
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3345 1 T3 11 T6 1 T13 15
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2550 1 T3 6 T6 2 T13 37
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2518 1 T3 2 T13 17 T86 5
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2980 1 T3 1 T6 10 T13 9
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 513 1 T3 2 T13 35 T21 17
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 409 1 T3 1 T13 5 T16 8
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 839 1 T13 3 T16 17 T21 11
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 628 1 T2 1 T13 9 T16 4
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4376 1 T39 2 T21 17 T85 9
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 754 1 T3 1 T13 7 T16 8
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 541 1 T3 3 T86 1 T138 14
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 778 1 T1 1 T16 4 T21 65
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1297 1 T3 1 T5 1 T6 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1685 1 T16 10 T21 90 T89 17
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1915 1 T3 2 T13 16 T21 41
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1720 1 T3 2 T13 5 T16 9
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2449 1 T3 11 T13 11 T16 38
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1888 1 T3 2 T5 1 T13 20
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1562 1 T6 2 T13 14 T39 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1920 1 T6 4 T13 7 T16 6

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