Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16656171	1			T1	5309		T2	16596		T3	254208
all_pins[1]	16656171	1			T1	5309		T2	16596		T3	254208
all_pins[2]	16656171	1			T1	5309		T2	16596		T3	254208

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42784031	1			T1	12997		T2	37896		T3	639175
values[0x1]	7184482	1			T1	2930		T2	11892		T3	123449
transitions[0x0=>0x1]	7184314	1			T1	2930		T2	11892		T3	123445
transitions[0x1=>0x0]	7184325	1			T1	2930		T2	11892		T3	123445

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16637382	1			T1	5301		T2	16594		T3	253978
all_pins[0]	values[0x1]	18789	1			T1	8		T2	2		T3	230
all_pins[0]	transitions[0x0=>0x1]	18714	1			T1	8		T2	2		T3	228
all_pins[0]	transitions[0x1=>0x0]	7165358	1			T1	2922		T2	11890		T3	123209
all_pins[1]	values[0x0]	16655900	1			T1	5309		T2	16596		T3	254200
all_pins[1]	values[0x1]	271	1			T3	8		T4	1		T16	5
all_pins[1]	transitions[0x0=>0x1]	227	1			T3	7		T4	1		T16	5
all_pins[1]	transitions[0x1=>0x0]	18745	1			T1	8		T2	2		T3	229
all_pins[2]	values[0x0]	9490749	1			T1	2387		T2	4706		T3	130997
all_pins[2]	values[0x1]	7165422	1			T1	2922		T2	11890		T3	123211
all_pins[2]	transitions[0x0=>0x1]	7165373	1			T1	2922		T2	11890		T3	123210
all_pins[2]	transitions[0x1=>0x0]	222	1			T3	7		T4	1		T16	5