Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 879 1 T3 32 T4 7 T18 11
all_values[1] 879 1 T3 32 T4 7 T18 11
all_values[2] 879 1 T3 32 T4 7 T18 11


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1383 1 T3 48 T4 13 T18 22
auto[1] 1254 1 T3 48 T4 8 T18 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 945 1 T3 48 T4 5 T18 13
auto[1] 1692 1 T3 48 T4 16 T18 20


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1502 1 T3 61 T4 9 T18 17
auto[1] 1135 1 T3 35 T4 12 T18 16


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 173 1 T3 9 T18 3 T36 2
all_values[0] auto[0] auto[0] auto[1] 77 1 T3 1 T4 1 T18 1
all_values[0] auto[0] auto[1] auto[0] 150 1 T3 7 T18 2 T36 1
all_values[0] auto[0] auto[1] auto[1] 97 1 T3 2 T21 6 T119 3
all_values[0] auto[1] auto[0] auto[1] 203 1 T3 7 T4 3 T18 3
all_values[0] auto[1] auto[1] auto[1] 179 1 T3 6 T4 3 T18 2
all_values[1] auto[0] auto[0] auto[0] 154 1 T3 6 T4 1 T18 3
all_values[1] auto[0] auto[0] auto[1] 105 1 T3 3 T4 1 T18 2
all_values[1] auto[0] auto[1] auto[0] 121 1 T3 4 T4 1 T36 1
all_values[1] auto[0] auto[1] auto[1] 113 1 T3 5 T4 1 T18 1
all_values[1] auto[1] auto[0] auto[1] 210 1 T3 7 T4 2 T18 2
all_values[1] auto[1] auto[1] auto[1] 176 1 T3 7 T4 1 T18 3
all_values[2] auto[0] auto[0] auto[0] 182 1 T3 12 T4 2 T18 4
all_values[2] auto[0] auto[0] auto[1] 84 1 T36 3 T21 3 T119 3
all_values[2] auto[0] auto[1] auto[0] 165 1 T3 10 T4 1 T18 1
all_values[2] auto[0] auto[1] auto[1] 81 1 T3 2 T4 1 T21 4
all_values[2] auto[1] auto[0] auto[1] 195 1 T3 3 T4 3 T18 4
all_values[2] auto[1] auto[1] auto[1] 172 1 T3 5 T18 2 T36 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%