Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3617	1			T1	5		T2	5		T3	78
sha2_none	3597	1			T1	3		T2	2		T3	67
sha2_512	7046	1			T2	1		T3	69		T4	2
sha2_384	6677	1			T1	4		T3	89		T4	6
sha2_256	5634	1			T1	3		T2	5		T3	73

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17053

1

T1

7

T2

7

T3

211

auto[1]

9821

1

T1

8

T2

6

T3

175

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9505

1

T1

8

T2

7

T3

192

auto[1]

17369

1

T1

7

T2

6

T3

194

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

13971

1

T1

6

T2

7

T3

240

disabled

12903

1

T1

9

T2

6

T3

146

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	3950	1			T1	2		T2	2		T3	68
key_none	7349	1			T1	3		T2	2		T3	51
key_1024	3901	1			T1	1		T3	52		T4	2
key_512	3323	1			T1	3		T2	2		T3	60
key_384	3059	1			T1	2		T2	4		T3	43
key_256	2676	1			T1	2		T2	2		T3	62
key_128	2530	1			T1	2		T2	1		T3	49

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17225

1

T1

10

T2

7

T3

204

auto[1]

9649

1

T1

5

T2

6

T3

182

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

26679

1

T1

15

T2

12

T3

386

disabled

195

1

T2

1

T18

4

T36

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1310

1

T1

2

T2

3

T3

38

enabled

auto[0]

auto[0]

auto[1]

1362

1

T1

1

T3

25

T4

2

enabled

auto[0]

auto[1]

auto[0]

1391

1

T1

1

T2

1

T3

28

enabled

auto[0]

auto[1]

auto[1]

1390

1

T2

1

T3

22

T4

2

enabled

auto[1]

auto[0]

auto[0]

4119

1

T3

36

T4

1

T5

3

enabled

auto[1]

auto[0]

auto[1]

1444

1

T1

1

T2

2

T3

39

enabled

auto[1]

auto[1]

auto[0]

1520

1

T1

1

T3

22

T4

6

enabled

auto[1]

auto[1]

auto[1]

1435

1

T3

30

T4

3

T12

1

disabled

auto[0]

auto[0]

auto[0]

979

1

T1

1

T3

22

T5

4

disabled

auto[0]

auto[0]

auto[1]

1010

1

T3

19

T4

4

T5

2

disabled

auto[0]

auto[1]

auto[0]

1035

1

T1

3

T3

22

T4

2

disabled

auto[0]

auto[1]

auto[1]

1028

1

T2

2

T3

16

T4

1

disabled

auto[1]

auto[0]

auto[0]

5827

1

T1

1

T2

1

T3

15

disabled

auto[1]

auto[0]

auto[1]

1002

1

T1

1

T2

1

T3

17

disabled

auto[1]

auto[1]

auto[0]

1044

1

T1

1

T2

2

T3

21

disabled

auto[1]

auto[1]

auto[1]

978

1

T1

2

T3

14

T6

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

13901

1

T1

6

T2

7

T3

240

enabled

disabled

70

1

T18

1

T36

1

T21

2

disabled

disabled

125

1

T2

1

T18

3

T39

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

12778

1

T1

9

T2

5

T3

146

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	963	1			T1	1		T2	2		T3	16
key_invalid	sha2_none	732	1			T1	1		T3	13		T12	1
key_invalid	sha2_512	757	1			T3	10		T4	1		T6	2
key_invalid	sha2_384	718	1			T3	17		T6	1		T13	1
key_invalid	sha2_256	698	1			T3	11		T4	3		T13	2
key_none	sha2_invalid	452	1			T1	1		T3	14		T14	1
key_none	sha2_none	495	1			T1	1		T3	8		T5	1
key_none	sha2_512	2433	1			T3	9		T6	1		T13	3
key_none	sha2_384	2451	1			T3	10		T5	2		T6	1
key_none	sha2_256	1481	1			T1	1		T2	2		T3	10
key_1024	sha2_invalid	427	1			T3	6		T5	1		T14	2
key_1024	sha2_none	459	1			T3	9		T4	1		T5	2
key_1024	sha2_512	1637	1			T3	6		T4	1		T5	3
key_1024	sha2_384	861	1			T1	1		T3	16		T6	1
key_512	sha2_invalid	440	1			T1	1		T2	1		T3	11
key_512	sha2_none	458	1			T3	11		T14	1		T15	1
key_512	sha2_512	537	1			T3	16		T5	3		T6	1
key_512	sha2_384	1123	1			T1	1		T3	12		T5	1
key_512	sha2_256	724	1			T1	1		T2	1		T3	9
key_384	sha2_invalid	441	1			T2	1		T3	8		T5	2
key_384	sha2_none	470	1			T2	1		T3	7		T12	1
key_384	sha2_512	575	1			T2	1		T3	7		T6	3
key_384	sha2_384	515	1			T1	1		T3	12		T4	1
key_384	sha2_256	1021	1			T1	1		T2	1		T3	8
key_256	sha2_invalid	433	1			T1	2		T2	1		T3	14
key_256	sha2_none	485	1			T3	11		T6	2		T13	1
key_256	sha2_512	547	1			T3	10		T5	1		T13	1
key_256	sha2_384	486	1			T3	12		T4	2		T5	2
key_256	sha2_256	690	1			T2	1		T3	14		T4	5
key_128	sha2_invalid	447	1			T3	9		T4	1		T5	1
key_128	sha2_none	481	1			T1	1		T2	1		T3	8
key_128	sha2_512	546	1			T3	11		T6	2		T13	2
key_128	sha2_384	499	1			T1	1		T3	10		T4	3
key_128	sha2_256	524	1			T3	10		T5	1		T6	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

481

1

T3

10

T5

1

T14

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	963	1			T1	1		T2	2		T3	16
key_invalid	sha2_none	732	1			T1	1		T3	13		T12	1
key_invalid	sha2_512	757	1			T3	10		T4	1		T6	2
key_invalid	sha2_384	718	1			T3	17		T6	1		T13	1
key_invalid	sha2_256	698	1			T3	11		T4	3		T13	2
key_none	sha2_invalid	452	1			T1	1		T3	14		T14	1
key_none	sha2_none	495	1			T1	1		T3	8		T5	1
key_none	sha2_512	2433	1			T3	9		T6	1		T13	3
key_none	sha2_384	2451	1			T3	10		T5	2		T6	1
key_none	sha2_256	1481	1			T1	1		T2	2		T3	10
key_1024	sha2_invalid	427	1			T3	6		T5	1		T14	2
key_1024	sha2_none	459	1			T3	9		T4	1		T5	2
key_1024	sha2_512	1637	1			T3	6		T4	1		T5	3
key_1024	sha2_384	861	1			T1	1		T3	16		T6	1
key_1024	sha2_256	481	1			T3	10		T5	1		T14	1
key_512	sha2_invalid	440	1			T1	1		T2	1		T3	11
key_512	sha2_none	458	1			T3	11		T14	1		T15	1
key_512	sha2_512	537	1			T3	16		T5	3		T6	1
key_512	sha2_384	1123	1			T1	1		T3	12		T5	1
key_512	sha2_256	724	1			T1	1		T2	1		T3	9
key_384	sha2_invalid	441	1			T2	1		T3	8		T5	2
key_384	sha2_none	470	1			T2	1		T3	7		T12	1
key_384	sha2_512	575	1			T2	1		T3	7		T6	3
key_384	sha2_384	515	1			T1	1		T3	12		T4	1
key_384	sha2_256	1021	1			T1	1		T2	1		T3	8
key_256	sha2_invalid	433	1			T1	2		T2	1		T3	14
key_256	sha2_none	485	1			T3	11		T6	2		T13	1
key_256	sha2_512	547	1			T3	10		T5	1		T13	1
key_256	sha2_384	486	1			T3	12		T4	2		T5	2
key_256	sha2_256	690	1			T2	1		T3	14		T4	5
key_128	sha2_invalid	447	1			T3	9		T4	1		T5	1
key_128	sha2_none	481	1			T1	1		T2	1		T3	8
key_128	sha2_512	546	1			T3	11		T6	2		T13	2
key_128	sha2_384	499	1			T1	1		T3	10		T4	3
key_128	sha2_256	524	1			T3	10		T5	1		T6	2