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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.11 100.00 97.06 98.27 98.48 99.85


Total test records in report: 656
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T70 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1810361295 Aug 13 06:47:59 PM PDT 24 Aug 13 06:48:00 PM PDT 24 31388469 ps
T60 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.963757013 Aug 13 06:47:36 PM PDT 24 Aug 13 06:47:39 PM PDT 24 193931499 ps
T61 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.457020657 Aug 13 06:47:28 PM PDT 24 Aug 13 06:47:32 PM PDT 24 175752530 ps
T539 /workspace/coverage/cover_reg_top/32.hmac_intr_test.152200600 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:56 PM PDT 24 12479228 ps
T71 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1636086017 Aug 13 06:47:37 PM PDT 24 Aug 13 06:47:37 PM PDT 24 286053172 ps
T97 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1414045802 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:50 PM PDT 24 125027710 ps
T540 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4015876148 Aug 13 06:47:52 PM PDT 24 Aug 13 06:47:53 PM PDT 24 27690003 ps
T541 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3180561435 Aug 13 06:47:25 PM PDT 24 Aug 13 06:47:26 PM PDT 24 55613171 ps
T115 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3655424448 Aug 13 06:47:18 PM PDT 24 Aug 13 06:47:20 PM PDT 24 283175767 ps
T62 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.292547894 Aug 13 06:47:35 PM PDT 24 Aug 13 06:47:38 PM PDT 24 53442687 ps
T542 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2804990775 Aug 13 06:47:27 PM PDT 24 Aug 13 06:47:37 PM PDT 24 115453680 ps
T543 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2999254551 Aug 13 06:47:59 PM PDT 24 Aug 13 06:47:59 PM PDT 24 26623317 ps
T55 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3380774637 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:52 PM PDT 24 340239154 ps
T544 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3897373038 Aug 13 06:47:37 PM PDT 24 Aug 13 06:47:38 PM PDT 24 151224168 ps
T545 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3216375729 Aug 13 06:47:32 PM PDT 24 Aug 13 06:47:32 PM PDT 24 24763962 ps
T546 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1197022406 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:53 PM PDT 24 116161270 ps
T547 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2810447203 Aug 13 06:47:56 PM PDT 24 Aug 13 06:47:59 PM PDT 24 201203143 ps
T548 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3784042679 Aug 13 06:47:40 PM PDT 24 Aug 13 06:47:42 PM PDT 24 40142969 ps
T549 /workspace/coverage/cover_reg_top/8.hmac_intr_test.756442333 Aug 13 06:47:43 PM PDT 24 Aug 13 06:47:44 PM PDT 24 44816537 ps
T550 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1170742945 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:49 PM PDT 24 52134159 ps
T551 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2575174629 Aug 13 06:47:43 PM PDT 24 Aug 13 06:47:44 PM PDT 24 37747570 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.155923180 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:49 PM PDT 24 34418964 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1138971989 Aug 13 06:47:30 PM PDT 24 Aug 13 06:47:36 PM PDT 24 359218086 ps
T552 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3279157104 Aug 13 06:47:18 PM PDT 24 Aug 13 06:47:19 PM PDT 24 40178524 ps
T56 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2516549982 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:51 PM PDT 24 151592733 ps
T553 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3940424351 Aug 13 06:47:44 PM PDT 24 Aug 13 06:47:47 PM PDT 24 160823819 ps
T554 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2931858579 Aug 13 06:47:46 PM PDT 24 Aug 13 06:47:47 PM PDT 24 56030026 ps
T555 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2040282082 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:50 PM PDT 24 19598736 ps
T57 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2724124655 Aug 13 06:47:31 PM PDT 24 Aug 13 06:47:34 PM PDT 24 325033643 ps
T100 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2551219001 Aug 13 06:47:44 PM PDT 24 Aug 13 06:47:45 PM PDT 24 19280901 ps
T121 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2208917430 Aug 13 06:47:29 PM PDT 24 Aug 13 06:47:33 PM PDT 24 284920935 ps
T125 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1042633425 Aug 13 06:47:39 PM PDT 24 Aug 13 06:47:48 PM PDT 24 128658003 ps
T556 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2045409948 Aug 13 06:47:42 PM PDT 24 Aug 13 06:47:44 PM PDT 24 80446442 ps
T122 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2449691857 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:48 PM PDT 24 528990997 ps
T557 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1586659451 Aug 13 06:47:31 PM PDT 24 Aug 13 07:00:47 PM PDT 24 53773879963 ps
T558 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1571891682 Aug 13 06:47:35 PM PDT 24 Aug 13 06:47:37 PM PDT 24 344038702 ps
T559 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1461279341 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:49 PM PDT 24 113806465 ps
T101 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.568487270 Aug 13 06:47:24 PM PDT 24 Aug 13 06:47:25 PM PDT 24 208433578 ps
T560 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2788106719 Aug 13 06:47:52 PM PDT 24 Aug 13 06:47:52 PM PDT 24 19819426 ps
T561 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1305035317 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 39753993 ps
T562 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2669465906 Aug 13 06:47:22 PM PDT 24 Aug 13 06:47:24 PM PDT 24 563637365 ps
T563 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3730365483 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:51 PM PDT 24 50052400 ps
T564 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1428331193 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:46 PM PDT 24 100516283 ps
T565 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2780761910 Aug 13 06:47:46 PM PDT 24 Aug 13 06:47:51 PM PDT 24 750300441 ps
T566 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4019539412 Aug 13 06:47:51 PM PDT 24 Aug 13 06:52:00 PM PDT 24 66137085306 ps
T126 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3132730208 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:48 PM PDT 24 183008951 ps
T567 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2138905309 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:48 PM PDT 24 11407492 ps
T102 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.101258682 Aug 13 06:47:37 PM PDT 24 Aug 13 06:47:38 PM PDT 24 44960071 ps
T116 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.756933179 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:49 PM PDT 24 257055465 ps
T568 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.856998440 Aug 13 06:47:21 PM PDT 24 Aug 13 06:47:24 PM PDT 24 246140824 ps
T569 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2550329537 Aug 13 06:47:57 PM PDT 24 Aug 13 06:47:59 PM PDT 24 37504662 ps
T117 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2520733182 Aug 13 06:47:43 PM PDT 24 Aug 13 06:47:45 PM PDT 24 42625335 ps
T570 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2723080119 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:58 PM PDT 24 144505919 ps
T103 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3013971109 Aug 13 06:47:25 PM PDT 24 Aug 13 06:47:31 PM PDT 24 1234428822 ps
T571 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1294231188 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:46 PM PDT 24 28812651 ps
T572 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1184703839 Aug 13 06:47:42 PM PDT 24 Aug 13 06:47:43 PM PDT 24 175669008 ps
T573 /workspace/coverage/cover_reg_top/21.hmac_intr_test.877782059 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:07 PM PDT 24 52021234 ps
T574 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1045060996 Aug 13 06:47:59 PM PDT 24 Aug 13 06:48:00 PM PDT 24 125391304 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1062749234 Aug 13 06:47:32 PM PDT 24 Aug 13 06:47:32 PM PDT 24 24108501 ps
T575 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2623655239 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:51 PM PDT 24 55653198 ps
T576 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1620121627 Aug 13 06:47:41 PM PDT 24 Aug 13 06:47:42 PM PDT 24 167717653 ps
T577 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1119687869 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:46 PM PDT 24 13790195 ps
T578 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1188942524 Aug 13 06:47:27 PM PDT 24 Aug 13 06:47:29 PM PDT 24 295566189 ps
T579 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.613752963 Aug 13 06:47:16 PM PDT 24 Aug 13 06:47:19 PM PDT 24 146895470 ps
T123 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.987143018 Aug 13 06:47:24 PM PDT 24 Aug 13 06:47:26 PM PDT 24 52435228 ps
T580 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2605053173 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:50 PM PDT 24 11780198 ps
T581 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1594706901 Aug 13 06:47:35 PM PDT 24 Aug 13 06:47:35 PM PDT 24 50076630 ps
T582 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1497962936 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:48 PM PDT 24 15082498 ps
T583 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1328143845 Aug 13 06:48:00 PM PDT 24 Aug 13 06:48:03 PM PDT 24 460268771 ps
T584 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1677396243 Aug 13 06:47:21 PM PDT 24 Aug 13 06:57:33 PM PDT 24 164245187087 ps
T105 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.865051007 Aug 13 06:47:41 PM PDT 24 Aug 13 06:47:41 PM PDT 24 338024554 ps
T585 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2614136812 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:49 PM PDT 24 33612405 ps
T586 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.23451860 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:50 PM PDT 24 116490527 ps
T587 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1363243466 Aug 13 06:47:56 PM PDT 24 Aug 13 06:47:57 PM PDT 24 13809498 ps
T588 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.980331260 Aug 13 06:47:44 PM PDT 24 Aug 13 06:47:45 PM PDT 24 102951959 ps
T106 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1423586151 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:49 PM PDT 24 33046098 ps
T124 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2019854692 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:52 PM PDT 24 170856321 ps
T589 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3434740238 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 99438645 ps
T590 /workspace/coverage/cover_reg_top/18.hmac_intr_test.765305294 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:51 PM PDT 24 21261418 ps
T591 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4219680740 Aug 13 06:48:06 PM PDT 24 Aug 13 06:48:07 PM PDT 24 37064616 ps
T592 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1161942103 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:50 PM PDT 24 161200099 ps
T593 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2361357361 Aug 13 06:47:19 PM PDT 24 Aug 13 06:47:24 PM PDT 24 20914573 ps
T594 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.457916269 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:56 PM PDT 24 99900857 ps
T595 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1868379402 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:53 PM PDT 24 287676693 ps
T596 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1248313630 Aug 13 06:47:46 PM PDT 24 Aug 13 06:47:47 PM PDT 24 15891874 ps
T107 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3741083311 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:49 PM PDT 24 21081105 ps
T597 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3205446389 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:47 PM PDT 24 106096608 ps
T598 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1030681407 Aug 13 06:47:38 PM PDT 24 Aug 13 06:47:41 PM PDT 24 643626733 ps
T599 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.259288457 Aug 13 06:47:40 PM PDT 24 Aug 13 06:47:45 PM PDT 24 464047442 ps
T127 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3251037212 Aug 13 06:47:28 PM PDT 24 Aug 13 06:47:31 PM PDT 24 694551861 ps
T600 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1584115800 Aug 13 06:47:36 PM PDT 24 Aug 13 06:47:37 PM PDT 24 53826645 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3924362177 Aug 13 06:47:27 PM PDT 24 Aug 13 06:47:30 PM PDT 24 1580245841 ps
T602 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3843014639 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:50 PM PDT 24 30518374 ps
T603 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2883195219 Aug 13 06:47:53 PM PDT 24 Aug 13 06:56:40 PM PDT 24 101746419882 ps
T604 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.654684198 Aug 13 06:47:22 PM PDT 24 Aug 13 06:47:25 PM PDT 24 414919772 ps
T605 /workspace/coverage/cover_reg_top/22.hmac_intr_test.571078302 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:48 PM PDT 24 52947970 ps
T130 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.941900252 Aug 13 06:47:56 PM PDT 24 Aug 13 06:47:59 PM PDT 24 425926637 ps
T128 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2617981302 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:50 PM PDT 24 85747578 ps
T606 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1250982557 Aug 13 06:47:36 PM PDT 24 Aug 13 06:47:38 PM PDT 24 295201771 ps
T129 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3798679117 Aug 13 06:47:43 PM PDT 24 Aug 13 06:47:48 PM PDT 24 908779638 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2828981902 Aug 13 06:47:16 PM PDT 24 Aug 13 06:47:16 PM PDT 24 48794072 ps
T109 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.165077219 Aug 13 06:47:55 PM PDT 24 Aug 13 06:48:16 PM PDT 24 3269575922 ps
T607 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2864457615 Aug 13 06:47:43 PM PDT 24 Aug 13 06:47:43 PM PDT 24 46057605 ps
T608 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1212894255 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:52 PM PDT 24 32602798 ps
T609 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1759087575 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:54 PM PDT 24 14367937 ps
T610 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.858623050 Aug 13 06:47:46 PM PDT 24 Aug 13 06:47:48 PM PDT 24 87342024 ps
T611 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1265033205 Aug 13 06:47:57 PM PDT 24 Aug 13 06:47:59 PM PDT 24 96338982 ps
T612 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.711852130 Aug 13 06:47:36 PM PDT 24 Aug 13 06:47:38 PM PDT 24 33538563 ps
T613 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3064794597 Aug 13 06:47:22 PM PDT 24 Aug 13 06:47:26 PM PDT 24 690619839 ps
T614 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2063526909 Aug 13 06:47:31 PM PDT 24 Aug 13 06:47:32 PM PDT 24 28466061 ps
T615 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2170870507 Aug 13 06:47:34 PM PDT 24 Aug 13 06:47:36 PM PDT 24 115999459 ps
T616 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1833915778 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:49 PM PDT 24 47467555 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3423661204 Aug 13 06:47:33 PM PDT 24 Aug 13 06:47:37 PM PDT 24 386421496 ps
T618 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4236711884 Aug 13 06:47:39 PM PDT 24 Aug 13 06:47:40 PM PDT 24 18883577 ps
T619 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2312900329 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:07 PM PDT 24 32284170 ps
T110 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2834100193 Aug 13 06:47:58 PM PDT 24 Aug 13 06:47:59 PM PDT 24 107128648 ps
T620 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3744745604 Aug 13 06:47:35 PM PDT 24 Aug 13 06:47:38 PM PDT 24 502766345 ps
T621 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1508501506 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:48 PM PDT 24 23310956 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.389245921 Aug 13 06:47:36 PM PDT 24 Aug 13 06:47:37 PM PDT 24 127662731 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.352771541 Aug 13 06:47:21 PM PDT 24 Aug 13 06:47:22 PM PDT 24 102876283 ps
T623 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3072827219 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:50 PM PDT 24 32297253 ps
T624 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1538767360 Aug 13 06:47:37 PM PDT 24 Aug 13 06:47:39 PM PDT 24 52870195 ps
T131 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1379568237 Aug 13 06:47:49 PM PDT 24 Aug 13 06:47:54 PM PDT 24 1106874255 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1097799923 Aug 13 06:47:38 PM PDT 24 Aug 13 06:47:40 PM PDT 24 371190260 ps
T626 /workspace/coverage/cover_reg_top/41.hmac_intr_test.515271088 Aug 13 06:48:02 PM PDT 24 Aug 13 06:48:03 PM PDT 24 42983954 ps
T627 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.89873315 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:49 PM PDT 24 112541935 ps
T628 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3510506002 Aug 13 06:47:38 PM PDT 24 Aug 13 06:47:39 PM PDT 24 132954626 ps
T629 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1848524271 Aug 13 06:47:44 PM PDT 24 Aug 13 06:47:45 PM PDT 24 76077242 ps
T630 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3270538307 Aug 13 06:47:25 PM PDT 24 Aug 13 06:47:31 PM PDT 24 940920080 ps
T631 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1833586720 Aug 13 06:47:40 PM PDT 24 Aug 13 06:47:41 PM PDT 24 76924847 ps
T632 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.549006294 Aug 13 06:47:18 PM PDT 24 Aug 13 06:47:29 PM PDT 24 911164228 ps
T112 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1080629877 Aug 13 06:47:45 PM PDT 24 Aug 13 06:47:51 PM PDT 24 6032991924 ps
T633 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3158900684 Aug 13 06:47:40 PM PDT 24 Aug 13 06:47:41 PM PDT 24 33387553 ps
T634 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1491249203 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:48 PM PDT 24 265155946 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4061339671 Aug 13 06:47:44 PM PDT 24 Aug 13 06:47:50 PM PDT 24 407321174 ps
T636 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.65345040 Aug 13 06:47:22 PM PDT 24 Aug 13 06:47:36 PM PDT 24 322019593 ps
T637 /workspace/coverage/cover_reg_top/34.hmac_intr_test.4041127790 Aug 13 06:47:33 PM PDT 24 Aug 13 06:47:34 PM PDT 24 32916697 ps
T638 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3603523263 Aug 13 06:47:59 PM PDT 24 Aug 13 06:48:00 PM PDT 24 79850426 ps
T639 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1738598799 Aug 13 06:47:48 PM PDT 24 Aug 13 06:47:48 PM PDT 24 18392448 ps
T640 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2128111668 Aug 13 06:47:19 PM PDT 24 Aug 13 06:47:21 PM PDT 24 81025186 ps
T641 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1555107978 Aug 13 06:47:51 PM PDT 24 Aug 13 06:47:52 PM PDT 24 97820098 ps
T642 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1364965007 Aug 13 06:47:53 PM PDT 24 Aug 13 06:47:53 PM PDT 24 28260373 ps
T643 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1173197183 Aug 13 06:47:52 PM PDT 24 Aug 13 06:47:53 PM PDT 24 16262047 ps
T644 /workspace/coverage/cover_reg_top/0.hmac_intr_test.906140343 Aug 13 06:47:44 PM PDT 24 Aug 13 06:47:44 PM PDT 24 13205399 ps
T645 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1564903031 Aug 13 06:47:38 PM PDT 24 Aug 13 06:47:39 PM PDT 24 48097346 ps
T646 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2531001082 Aug 13 06:47:55 PM PDT 24 Aug 13 06:47:59 PM PDT 24 304491943 ps
T647 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.770723130 Aug 13 06:47:50 PM PDT 24 Aug 13 06:47:51 PM PDT 24 23909718 ps
T648 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2604339196 Aug 13 06:47:45 PM PDT 24 Aug 13 06:57:17 PM PDT 24 191355813986 ps
T649 /workspace/coverage/cover_reg_top/37.hmac_intr_test.88532221 Aug 13 06:48:01 PM PDT 24 Aug 13 06:48:02 PM PDT 24 172183796 ps
T650 /workspace/coverage/cover_reg_top/30.hmac_intr_test.334932145 Aug 13 06:47:54 PM PDT 24 Aug 13 06:47:55 PM PDT 24 18024246 ps
T651 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.826442995 Aug 13 06:47:37 PM PDT 24 Aug 13 06:47:39 PM PDT 24 101749763 ps
T652 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4292086152 Aug 13 06:47:38 PM PDT 24 Aug 13 06:57:48 PM PDT 24 184820979150 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.128065305 Aug 13 06:47:32 PM PDT 24 Aug 13 06:47:34 PM PDT 24 38883069 ps
T654 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1527844989 Aug 13 06:47:47 PM PDT 24 Aug 13 06:47:48 PM PDT 24 72201308 ps
T655 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.283572198 Aug 13 06:47:40 PM PDT 24 Aug 13 06:47:48 PM PDT 24 227844295 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.268956350 Aug 13 06:47:46 PM PDT 24 Aug 13 06:47:47 PM PDT 24 45566722 ps

Test location /workspace/coverage/default/47.hmac_stress_all.636495592
Short name T3
Test name
Test status
Simulation time 164032984114 ps
CPU time 4151.18 seconds
Started Aug 13 06:32:44 PM PDT 24
Finished Aug 13 07:41:56 PM PDT 24
Peak memory 815084 kb
Host smart-8874aa6f-51b6-4287-bc14-ea04f57a5b25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636495592 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.636495592
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2466852561
Short name T7
Test name
Test status
Simulation time 58530460229 ps
CPU time 202.62 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:34:52 PM PDT 24
Peak memory 209024 kb
Host smart-3c3d8377-323a-4d6e-a9c9-8665923d5731
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466852561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2466852561
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4282644858
Short name T21
Test name
Test status
Simulation time 18395501398 ps
CPU time 1577.35 seconds
Started Aug 13 06:32:21 PM PDT 24
Finished Aug 13 06:58:39 PM PDT 24
Peak memory 756676 kb
Host smart-39ed892e-045c-4679-b710-50db7aaccf04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282644858 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4282644858
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2208917430
Short name T121
Test name
Test status
Simulation time 284920935 ps
CPU time 4.34 seconds
Started Aug 13 06:47:29 PM PDT 24
Finished Aug 13 06:47:33 PM PDT 24
Peak memory 200256 kb
Host smart-23817334-312a-4145-a57b-7d49dca6e2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208917430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2208917430
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.4188242467
Short name T8
Test name
Test status
Simulation time 12253792952 ps
CPU time 419.66 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:38:53 PM PDT 24
Peak memory 610760 kb
Host smart-10fa2044-bd33-421f-9273-37c29b0c6cec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188242467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.4188242467
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3879215561
Short name T33
Test name
Test status
Simulation time 17912198 ps
CPU time 0.55 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:32:10 PM PDT 24
Peak memory 195644 kb
Host smart-a2bf8330-10d9-4823-8c2c-b75611c753b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879215561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3879215561
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.4159189516
Short name T16
Test name
Test status
Simulation time 5274095608 ps
CPU time 66.99 seconds
Started Aug 13 06:32:22 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 200764 kb
Host smart-99b9abda-1297-4165-9cb7-ea6b7d6ffc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159189516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4159189516
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1150755323
Short name T69
Test name
Test status
Simulation time 75058340 ps
CPU time 0.93 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 200080 kb
Host smart-68f18b41-794f-482a-a87f-36b36545aef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150755323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1150755323
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/default/28.hmac_stress_all.176271106
Short name T9
Test name
Test status
Simulation time 9155350810 ps
CPU time 1175.11 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:51:41 PM PDT 24
Peak memory 697788 kb
Host smart-9dc69938-a03f-4be4-9d93-96135284e45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176271106 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.176271106
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1576830064
Short name T44
Test name
Test status
Simulation time 324078545 ps
CPU time 1.02 seconds
Started Aug 13 06:31:35 PM PDT 24
Finished Aug 13 06:31:36 PM PDT 24
Peak memory 219996 kb
Host smart-0d687430-b936-4cf4-b29e-84ec3f65132a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576830064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1576830064
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/26.hmac_stress_all.197943106
Short name T139
Test name
Test status
Simulation time 36600139540 ps
CPU time 2424.01 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 07:12:31 PM PDT 24
Peak memory 834156 kb
Host smart-5c5e4e4d-3e6a-45c7-bf18-0169abf98e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197943106 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.197943106
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1379568237
Short name T131
Test name
Test status
Simulation time 1106874255 ps
CPU time 4.34 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 200252 kb
Host smart-df2b11b1-a8ca-452c-8460-ae4e3e65fa69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379568237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1379568237
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_smoke.2967974303
Short name T6
Test name
Test status
Simulation time 546761518 ps
CPU time 11.95 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 200708 kb
Host smart-daf11eaf-a26e-4959-bffe-e4a0df9ba050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967974303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2967974303
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3251037212
Short name T127
Test name
Test status
Simulation time 694551861 ps
CPU time 3.1 seconds
Started Aug 13 06:47:28 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 200232 kb
Host smart-e20b0287-778d-4a11-9101-102c96c335e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251037212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3251037212
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1138971989
Short name T99
Test name
Test status
Simulation time 359218086 ps
CPU time 5.87 seconds
Started Aug 13 06:47:30 PM PDT 24
Finished Aug 13 06:47:36 PM PDT 24
Peak memory 200332 kb
Host smart-4747c73c-9f90-460c-b568-53001a720e89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138971989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1138971989
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4278304227
Short name T206
Test name
Test status
Simulation time 4573611625 ps
CPU time 127.53 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 217176 kb
Host smart-51d85177-424c-4c5c-9162-df5b781de087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278304227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4278304227
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3013971109
Short name T103
Test name
Test status
Simulation time 1234428822 ps
CPU time 5.83 seconds
Started Aug 13 06:47:25 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 200156 kb
Host smart-7ef8fe33-ccb5-4760-b673-4f629cd63718
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013971109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3013971109
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.65345040
Short name T636
Test name
Test status
Simulation time 322019593 ps
CPU time 14.07 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:36 PM PDT 24
Peak memory 199372 kb
Host smart-3ade0e3c-590d-4047-b0c6-450ea34f3a39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65345040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.65345040
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.268956350
Short name T656
Test name
Test status
Simulation time 45566722 ps
CPU time 1.01 seconds
Started Aug 13 06:47:46 PM PDT 24
Finished Aug 13 06:47:47 PM PDT 24
Peak memory 199632 kb
Host smart-9dcfe4ad-f387-4321-8349-010576f4b5c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268956350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.268956350
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2045409948
Short name T556
Test name
Test status
Simulation time 80446442 ps
CPU time 1.99 seconds
Started Aug 13 06:47:42 PM PDT 24
Finished Aug 13 06:47:44 PM PDT 24
Peak memory 200368 kb
Host smart-5ea8c126-3f33-44b2-bb0e-4183a60a8f0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045409948 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2045409948
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1062749234
Short name T104
Test name
Test status
Simulation time 24108501 ps
CPU time 0.77 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 199664 kb
Host smart-876e9c87-3b3f-478f-a32c-4291a3d93cb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062749234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1062749234
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.906140343
Short name T644
Test name
Test status
Simulation time 13205399 ps
CPU time 0.58 seconds
Started Aug 13 06:47:44 PM PDT 24
Finished Aug 13 06:47:44 PM PDT 24
Peak memory 195212 kb
Host smart-d9e499d9-304d-420a-b75a-ab3bd111146d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906140343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.906140343
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.613752963
Short name T579
Test name
Test status
Simulation time 146895470 ps
CPU time 2.34 seconds
Started Aug 13 06:47:16 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 200284 kb
Host smart-403b5544-f083-4ce4-abdc-87b741476de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613752963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.613752963
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.457020657
Short name T61
Test name
Test status
Simulation time 175752530 ps
CPU time 3.74 seconds
Started Aug 13 06:47:28 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 200316 kb
Host smart-51338c1f-7ded-4499-bf86-e5d6f403c883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457020657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.457020657
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3270538307
Short name T630
Test name
Test status
Simulation time 940920080 ps
CPU time 5.81 seconds
Started Aug 13 06:47:25 PM PDT 24
Finished Aug 13 06:47:31 PM PDT 24
Peak memory 200268 kb
Host smart-1b7d0b31-e6dd-4a50-b972-120e586fedf3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270538307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3270538307
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.155923180
Short name T98
Test name
Test status
Simulation time 34418964 ps
CPU time 1.05 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 200064 kb
Host smart-914a7c93-0288-401a-8734-eafd382404f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155923180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.155923180
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.89873315
Short name T627
Test name
Test status
Simulation time 112541935 ps
CPU time 3.87 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 216012 kb
Host smart-51a6e37f-9b2a-4f45-94c0-b5b90193328d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89873315 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.89873315
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.352771541
Short name T111
Test name
Test status
Simulation time 102876283 ps
CPU time 0.84 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:22 PM PDT 24
Peak memory 199704 kb
Host smart-d6c8f5fc-31c4-4f4f-a516-7b8566c1baa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352771541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.352771541
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3216375729
Short name T545
Test name
Test status
Simulation time 24763962 ps
CPU time 0.56 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 195228 kb
Host smart-d7dd4c96-7d31-454a-98fd-1faed50c71e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216375729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3216375729
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.654684198
Short name T604
Test name
Test status
Simulation time 414919772 ps
CPU time 2.49 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:25 PM PDT 24
Peak memory 200320 kb
Host smart-19a6cad1-4214-4f87-8cdc-d04c8b24a534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654684198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.654684198
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2810447203
Short name T547
Test name
Test status
Simulation time 201203143 ps
CPU time 2.58 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 200308 kb
Host smart-57c2a822-eaad-4ffd-afa2-ae2bccec87af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810447203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2810447203
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2669465906
Short name T562
Test name
Test status
Simulation time 563637365 ps
CPU time 1.88 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 200352 kb
Host smart-36cf9f99-5d5a-4855-bc4f-f69d4ca12c48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669465906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2669465906
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4292086152
Short name T652
Test name
Test status
Simulation time 184820979150 ps
CPU time 609.96 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:57:48 PM PDT 24
Peak memory 216872 kb
Host smart-38964f34-a0f6-4d33-9ff5-bdc7ab36774b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292086152 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4292086152
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2864457615
Short name T607
Test name
Test status
Simulation time 46057605 ps
CPU time 0.67 seconds
Started Aug 13 06:47:43 PM PDT 24
Finished Aug 13 06:47:43 PM PDT 24
Peak memory 198436 kb
Host smart-8c187627-4ba9-45bb-8c8c-c0f322dfc749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864457615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2864457615
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2575174629
Short name T551
Test name
Test status
Simulation time 37747570 ps
CPU time 0.6 seconds
Started Aug 13 06:47:43 PM PDT 24
Finished Aug 13 06:47:44 PM PDT 24
Peak memory 195320 kb
Host smart-99a5333c-c538-4a14-9282-6740228af79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575174629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2575174629
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.23451860
Short name T586
Test name
Test status
Simulation time 116490527 ps
CPU time 2.43 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200300 kb
Host smart-7bc10aea-6e27-4cd5-8ae6-de7287192332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_
outstanding.23451860
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2128111668
Short name T640
Test name
Test status
Simulation time 81025186 ps
CPU time 1.17 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:21 PM PDT 24
Peak memory 200196 kb
Host smart-93fcb2b0-7fb0-4af9-af88-9cdc53b0242a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128111668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2128111668
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3064794597
Short name T613
Test name
Test status
Simulation time 690619839 ps
CPU time 4.09 seconds
Started Aug 13 06:47:22 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 200380 kb
Host smart-275fc884-6524-40e7-b7c6-d552b7441baa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064794597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3064794597
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3940424351
Short name T553
Test name
Test status
Simulation time 160823819 ps
CPU time 2.79 seconds
Started Aug 13 06:47:44 PM PDT 24
Finished Aug 13 06:47:47 PM PDT 24
Peak memory 216148 kb
Host smart-7bce06eb-9171-4aa4-baac-68ad3b0a0e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940424351 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3940424351
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2834100193
Short name T110
Test name
Test status
Simulation time 107128648 ps
CPU time 0.94 seconds
Started Aug 13 06:47:58 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 200132 kb
Host smart-a99c9360-f42e-4908-bf5e-893938a62b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834100193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2834100193
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1564903031
Short name T645
Test name
Test status
Simulation time 48097346 ps
CPU time 0.6 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 195348 kb
Host smart-8bc51b06-4f82-4117-84d7-77edb64cfc0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564903031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1564903031
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1508501506
Short name T621
Test name
Test status
Simulation time 23310956 ps
CPU time 1.17 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200360 kb
Host smart-93aef8c4-5478-42ca-8fe1-e2dd94adac5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508501506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1508501506
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3603523263
Short name T638
Test name
Test status
Simulation time 79850426 ps
CPU time 1.69 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 200276 kb
Host smart-cfa9d2ee-6bb8-4fb4-b14a-c3b576947748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603523263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3603523263
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1188942524
Short name T578
Test name
Test status
Simulation time 295566189 ps
CPU time 2.76 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:29 PM PDT 24
Peak memory 200356 kb
Host smart-71c19383-0e48-4351-9b0a-9cba9f70a971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188942524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1188942524
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2604339196
Short name T648
Test name
Test status
Simulation time 191355813986 ps
CPU time 572.15 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:57:17 PM PDT 24
Peak memory 216848 kb
Host smart-bbb27231-aa84-40e5-8b58-82bef29e785d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604339196 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2604339196
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3158900684
Short name T633
Test name
Test status
Simulation time 33387553 ps
CPU time 0.61 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 195340 kb
Host smart-e9de3ae1-e6fd-40e2-9df6-32a7ae96a4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158900684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3158900684
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2419289975
Short name T114
Test name
Test status
Simulation time 168685541 ps
CPU time 2.12 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:40 PM PDT 24
Peak memory 200372 kb
Host smart-fc8f8c63-9246-4d82-b029-4c0db009b102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419289975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2419289975
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3784042679
Short name T548
Test name
Test status
Simulation time 40142969 ps
CPU time 2.1 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:42 PM PDT 24
Peak memory 200336 kb
Host smart-4a88a5de-2263-4c80-ad66-ed9f8c6dcb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784042679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3784042679
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.987143018
Short name T123
Test name
Test status
Simulation time 52435228 ps
CPU time 1.69 seconds
Started Aug 13 06:47:24 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 200304 kb
Host smart-e05b75fd-70ad-470d-814f-98253ba1402b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987143018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.987143018
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.826442995
Short name T651
Test name
Test status
Simulation time 101749763 ps
CPU time 1.73 seconds
Started Aug 13 06:47:37 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 200292 kb
Host smart-b47e92d7-d56b-44b1-9968-4af804fd7b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826442995 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.826442995
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1636086017
Short name T71
Test name
Test status
Simulation time 286053172 ps
CPU time 0.72 seconds
Started Aug 13 06:47:37 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 198248 kb
Host smart-af5c4077-78f4-4636-a216-ae726d8d5e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636086017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1636086017
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1833915778
Short name T616
Test name
Test status
Simulation time 47467555 ps
CPU time 0.54 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 195244 kb
Host smart-83f7f135-3cab-49ef-9d42-e44807b4e319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833915778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1833915778
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1555107978
Short name T641
Test name
Test status
Simulation time 97820098 ps
CPU time 1.1 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 200248 kb
Host smart-ca94b6ce-7c53-49b5-88d8-891364487b65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555107978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1555107978
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1461279341
Short name T559
Test name
Test status
Simulation time 113806465 ps
CPU time 1.54 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 200296 kb
Host smart-6803bedb-9744-442e-840d-06ddb5910257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461279341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1461279341
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2531001082
Short name T646
Test name
Test status
Simulation time 304491943 ps
CPU time 3.03 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 200296 kb
Host smart-b2565364-12fa-41ad-816d-70d80a469964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531001082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2531001082
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4019539412
Short name T566
Test name
Test status
Simulation time 66137085306 ps
CPU time 248.23 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:52:00 PM PDT 24
Peak memory 215956 kb
Host smart-164ede8e-04fd-4da2-aab2-8b692e359e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019539412 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4019539412
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3741083311
Short name T107
Test name
Test status
Simulation time 21081105 ps
CPU time 0.71 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 198784 kb
Host smart-554c4551-fefa-4e13-8753-874316709c19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741083311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3741083311
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1738598799
Short name T639
Test name
Test status
Simulation time 18392448 ps
CPU time 0.62 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 195368 kb
Host smart-7847dd74-fd53-4e2f-bb5e-f370a0ebf8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738598799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1738598799
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1184703839
Short name T572
Test name
Test status
Simulation time 175669008 ps
CPU time 1.6 seconds
Started Aug 13 06:47:42 PM PDT 24
Finished Aug 13 06:47:43 PM PDT 24
Peak memory 200244 kb
Host smart-1ea51e97-6f6b-4378-8ed1-8d4f69723e44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184703839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1184703839
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1666250670
Short name T59
Test name
Test status
Simulation time 184957599 ps
CPU time 4.01 seconds
Started Aug 13 06:47:37 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 200372 kb
Host smart-b45623e8-325c-47a1-8dfa-74981cd607ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666250670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1666250670
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1042633425
Short name T125
Test name
Test status
Simulation time 128658003 ps
CPU time 4.16 seconds
Started Aug 13 06:47:39 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200256 kb
Host smart-f129afd3-5d5b-47c0-beb1-5cbbaa79193c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042633425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1042633425
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1250982557
Short name T606
Test name
Test status
Simulation time 295201771 ps
CPU time 1.94 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 200452 kb
Host smart-e37430a8-7b09-47d0-be04-229f8215ac53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250982557 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1250982557
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1527844989
Short name T654
Test name
Test status
Simulation time 72201308 ps
CPU time 0.72 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 198424 kb
Host smart-26d29f0d-a36a-4adc-a431-bb8dc0385ff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527844989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1527844989
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1810361295
Short name T70
Test name
Test status
Simulation time 31388469 ps
CPU time 0.61 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 195320 kb
Host smart-b6ccfe23-ebfe-4c41-bcc2-558e65fb3366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810361295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1810361295
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.770723130
Short name T647
Test name
Test status
Simulation time 23909718 ps
CPU time 1.1 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 200216 kb
Host smart-7b937b22-b1d4-4ed0-a188-901472a92cdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770723130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.770723130
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1161942103
Short name T592
Test name
Test status
Simulation time 161200099 ps
CPU time 2.19 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200288 kb
Host smart-71da53a4-6789-4dd1-a300-a66131323909
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161942103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1161942103
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.941900252
Short name T130
Test name
Test status
Simulation time 425926637 ps
CPU time 2.01 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 200388 kb
Host smart-bff627c7-68a3-4f34-b3e0-f394d8db3a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941900252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.941900252
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3205446389
Short name T597
Test name
Test status
Simulation time 106096608 ps
CPU time 2.37 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:47 PM PDT 24
Peak memory 200236 kb
Host smart-ef8a9663-78bb-4a74-a433-f21a63058873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205446389 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3205446389
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1414045802
Short name T97
Test name
Test status
Simulation time 125027710 ps
CPU time 0.93 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 199780 kb
Host smart-c5cf5d28-c06b-4e65-ba26-3a6717ca5e17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414045802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1414045802
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2839762806
Short name T536
Test name
Test status
Simulation time 38070582 ps
CPU time 0.56 seconds
Started Aug 13 06:47:52 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 195244 kb
Host smart-0b11037b-785b-49de-83b6-cdc1ecf0fd50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839762806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2839762806
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2520733182
Short name T117
Test name
Test status
Simulation time 42625335 ps
CPU time 1.06 seconds
Started Aug 13 06:47:43 PM PDT 24
Finished Aug 13 06:47:45 PM PDT 24
Peak memory 200156 kb
Host smart-4a8857f7-b072-4b55-a426-7b4c619392fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520733182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2520733182
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2723080119
Short name T570
Test name
Test status
Simulation time 144505919 ps
CPU time 2.93 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 200288 kb
Host smart-a4df9776-fa80-41db-acc5-783ff0cf06e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723080119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2723080119
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1265033205
Short name T611
Test name
Test status
Simulation time 96338982 ps
CPU time 1.91 seconds
Started Aug 13 06:47:57 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 200300 kb
Host smart-1f667db8-8cc7-4c39-bc84-fb373c4fd019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265033205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1265033205
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2883195219
Short name T603
Test name
Test status
Simulation time 101746419882 ps
CPU time 526.12 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:56:40 PM PDT 24
Peak memory 216080 kb
Host smart-31c6f6f9-ce70-441b-8edd-09b693973a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883195219 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2883195219
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1491249203
Short name T634
Test name
Test status
Simulation time 265155946 ps
CPU time 0.96 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200132 kb
Host smart-aa7cf363-482e-44ac-94de-0fea8f1840b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491249203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1491249203
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1248313630
Short name T596
Test name
Test status
Simulation time 15891874 ps
CPU time 0.62 seconds
Started Aug 13 06:47:46 PM PDT 24
Finished Aug 13 06:47:47 PM PDT 24
Peak memory 195376 kb
Host smart-a41c6d0a-cae0-4830-b485-3f6a27e0a167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248313630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1248313630
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.756933179
Short name T116
Test name
Test status
Simulation time 257055465 ps
CPU time 1.3 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 198824 kb
Host smart-6a1a4126-140d-4870-a664-e5d4e55ecc7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756933179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.756933179
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1328143845
Short name T583
Test name
Test status
Simulation time 460268771 ps
CPU time 2.32 seconds
Started Aug 13 06:48:00 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 200212 kb
Host smart-98313c9c-ad36-4f65-ac69-6fb8d460fa56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328143845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1328143845
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2449691857
Short name T122
Test name
Test status
Simulation time 528990997 ps
CPU time 2.79 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200268 kb
Host smart-660661c2-7793-4561-935b-ed1e0d87f733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449691857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2449691857
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2550329537
Short name T569
Test name
Test status
Simulation time 37504662 ps
CPU time 1.06 seconds
Started Aug 13 06:47:57 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 200180 kb
Host smart-a640c6d5-8412-4e7c-b1fc-cbf3b320d5a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550329537 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2550329537
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4236711884
Short name T618
Test name
Test status
Simulation time 18883577 ps
CPU time 0.7 seconds
Started Aug 13 06:47:39 PM PDT 24
Finished Aug 13 06:47:40 PM PDT 24
Peak memory 197892 kb
Host smart-3d59f357-9bec-40f2-ac83-6c5f71bcd465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236711884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4236711884
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.765305294
Short name T590
Test name
Test status
Simulation time 21261418 ps
CPU time 0.62 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 195336 kb
Host smart-d0a1c012-5434-4a2e-b357-c2e5afb830ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765305294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.765305294
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3072827219
Short name T623
Test name
Test status
Simulation time 32297253 ps
CPU time 1.52 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200244 kb
Host smart-3517e687-49c5-461c-b5d9-5155d5e0c80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072827219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3072827219
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2780761910
Short name T565
Test name
Test status
Simulation time 750300441 ps
CPU time 3.52 seconds
Started Aug 13 06:47:46 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 200316 kb
Host smart-e66bbe98-cab7-46df-ae92-4be77fd74b5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780761910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2780761910
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2516549982
Short name T56
Test name
Test status
Simulation time 151592733 ps
CPU time 3.15 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 200332 kb
Host smart-8380372a-ccbb-4f95-8a49-21bdbb46547f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516549982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2516549982
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3744745604
Short name T620
Test name
Test status
Simulation time 502766345 ps
CPU time 2.67 seconds
Started Aug 13 06:47:35 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 200468 kb
Host smart-0c112778-cb3d-4279-a65e-121fdce4697c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744745604 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3744745604
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.457916269
Short name T594
Test name
Test status
Simulation time 99900857 ps
CPU time 0.92 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 200112 kb
Host smart-bc63addb-22dc-4e9c-9f36-3d14c8eb0d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457916269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.457916269
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2312900329
Short name T619
Test name
Test status
Simulation time 32284170 ps
CPU time 0.57 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 195308 kb
Host smart-31139166-1db0-43e0-ad2e-4c62cc009a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312900329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2312900329
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4219680740
Short name T591
Test name
Test status
Simulation time 37064616 ps
CPU time 1.06 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 200132 kb
Host smart-43570f6a-ead9-4bfa-81c3-9f59306e9645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219680740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4219680740
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1197022406
Short name T546
Test name
Test status
Simulation time 116161270 ps
CPU time 2.88 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 200304 kb
Host smart-79e54079-c01d-49bc-aab8-693a8f0e07af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197022406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1197022406
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4061339671
Short name T635
Test name
Test status
Simulation time 407321174 ps
CPU time 5.51 seconds
Started Aug 13 06:47:44 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200172 kb
Host smart-089b2800-5aa2-4c97-b838-e969266a2783
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061339671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4061339671
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.165077219
Short name T109
Test name
Test status
Simulation time 3269575922 ps
CPU time 16.67 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:48:16 PM PDT 24
Peak memory 200412 kb
Host smart-3914c086-5e83-4671-9479-7d302b0f4392
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165077219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.165077219
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.389245921
Short name T622
Test name
Test status
Simulation time 127662731 ps
CPU time 0.99 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 200124 kb
Host smart-9e0991b0-326d-4f2e-8d37-368d79cd9f68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389245921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.389245921
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3897373038
Short name T544
Test name
Test status
Simulation time 151224168 ps
CPU time 1.28 seconds
Started Aug 13 06:47:37 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 200060 kb
Host smart-bf988e78-ec80-4111-b11e-07e3ad5a5c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897373038 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3897373038
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1423586151
Short name T106
Test name
Test status
Simulation time 33046098 ps
CPU time 0.71 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 198380 kb
Host smart-237c949e-19cf-40bf-9689-29431edff84c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423586151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1423586151
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2063526909
Short name T614
Test name
Test status
Simulation time 28466061 ps
CPU time 0.58 seconds
Started Aug 13 06:47:31 PM PDT 24
Finished Aug 13 06:47:32 PM PDT 24
Peak memory 195260 kb
Host smart-57d306f8-70e3-4f88-9bd5-56ff9a1cdf89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063526909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2063526909
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.694618071
Short name T113
Test name
Test status
Simulation time 224528299 ps
CPU time 2.11 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200300 kb
Host smart-30f7c725-9417-4efa-8901-dcbe1314479a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694618071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.694618071
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3423661204
Short name T617
Test name
Test status
Simulation time 386421496 ps
CPU time 3.62 seconds
Started Aug 13 06:47:33 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 200416 kb
Host smart-65161a74-a2f4-4365-97b5-5e067baf1dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423661204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3423661204
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1173197183
Short name T643
Test name
Test status
Simulation time 16262047 ps
CPU time 0.57 seconds
Started Aug 13 06:47:52 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 195184 kb
Host smart-2386be53-b6ba-4e2d-9b5c-992a87063961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173197183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1173197183
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.877782059
Short name T573
Test name
Test status
Simulation time 52021234 ps
CPU time 0.6 seconds
Started Aug 13 06:48:06 PM PDT 24
Finished Aug 13 06:48:07 PM PDT 24
Peak memory 195412 kb
Host smart-78b209d1-7c77-4061-ae6f-be7f8d125b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877782059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.877782059
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.571078302
Short name T605
Test name
Test status
Simulation time 52947970 ps
CPU time 0.62 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 195412 kb
Host smart-4ef79d9d-0a14-45e6-a77c-d042049099ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571078302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.571078302
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2441950974
Short name T538
Test name
Test status
Simulation time 39172716 ps
CPU time 0.59 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 195396 kb
Host smart-4722cc1c-9312-452b-80e1-f56177430555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441950974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2441950974
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1119687869
Short name T577
Test name
Test status
Simulation time 13790195 ps
CPU time 0.57 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:46 PM PDT 24
Peak memory 195264 kb
Host smart-8f1accf0-e321-4ef1-8384-ddf970e33741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119687869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1119687869
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2605053173
Short name T580
Test name
Test status
Simulation time 11780198 ps
CPU time 0.6 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 195344 kb
Host smart-9ea333df-dee4-4ee9-872b-30eba2e1f3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605053173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2605053173
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1428331193
Short name T564
Test name
Test status
Simulation time 100516283 ps
CPU time 0.62 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:46 PM PDT 24
Peak memory 195236 kb
Host smart-a0de9f0e-ff19-45bd-b647-14934beeebcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428331193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1428331193
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2138905309
Short name T567
Test name
Test status
Simulation time 11407492 ps
CPU time 0.59 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 195272 kb
Host smart-143d77de-1ae7-4580-a32b-7debbfdca92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138905309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2138905309
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1497962936
Short name T582
Test name
Test status
Simulation time 15082498 ps
CPU time 0.63 seconds
Started Aug 13 06:47:47 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 195280 kb
Host smart-9ac36eb0-cb41-4b85-a730-295b26fc4a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497962936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1497962936
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1305035317
Short name T561
Test name
Test status
Simulation time 39753993 ps
CPU time 0.62 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 195208 kb
Host smart-92cb9a92-b143-424b-9fe0-c86b3414663f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305035317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1305035317
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.283572198
Short name T655
Test name
Test status
Simulation time 227844295 ps
CPU time 7.82 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200364 kb
Host smart-6668f11e-65ee-4770-8641-1b549e0836e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283572198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.283572198
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2804990775
Short name T542
Test name
Test status
Simulation time 115453680 ps
CPU time 5.2 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 200288 kb
Host smart-9edb3301-f912-484b-8fb4-ac9631f328e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804990775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2804990775
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.865051007
Short name T105
Test name
Test status
Simulation time 338024554 ps
CPU time 0.84 seconds
Started Aug 13 06:47:41 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 198716 kb
Host smart-44e57c3c-adb8-4e74-b5fd-41ac908a0f0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865051007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.865051007
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.128065305
Short name T653
Test name
Test status
Simulation time 38883069 ps
CPU time 1.26 seconds
Started Aug 13 06:47:32 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 200132 kb
Host smart-2a6b78dc-66b0-4a00-ad7a-318c1d3fefca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128065305 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.128065305
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.568487270
Short name T101
Test name
Test status
Simulation time 208433578 ps
CPU time 0.88 seconds
Started Aug 13 06:47:24 PM PDT 24
Finished Aug 13 06:47:25 PM PDT 24
Peak memory 200076 kb
Host smart-df273fef-3df2-4e2e-9fe3-ea3e576a4350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568487270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.568487270
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3279157104
Short name T552
Test name
Test status
Simulation time 40178524 ps
CPU time 0.59 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:19 PM PDT 24
Peak memory 195336 kb
Host smart-2f05c042-9170-4401-aba0-8e7ac3d7f472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279157104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3279157104
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.711852130
Short name T612
Test name
Test status
Simulation time 33538563 ps
CPU time 1.62 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 200376 kb
Host smart-db1066c9-4b89-4ddb-aa69-1615e5651f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711852130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.711852130
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3843014639
Short name T602
Test name
Test status
Simulation time 30518374 ps
CPU time 1.35 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200308 kb
Host smart-d642539d-0cc0-4d19-b723-e8cc97d39881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843014639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3843014639
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2019854692
Short name T124
Test name
Test status
Simulation time 170856321 ps
CPU time 2.96 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 200312 kb
Host smart-b30af15f-7766-4863-8bae-c9244ae74ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019854692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2019854692
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.334932145
Short name T650
Test name
Test status
Simulation time 18024246 ps
CPU time 0.63 seconds
Started Aug 13 06:47:54 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 195340 kb
Host smart-6807bfdf-805a-4b50-b953-925ef9d7cf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334932145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.334932145
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2040282082
Short name T555
Test name
Test status
Simulation time 19598736 ps
CPU time 0.58 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 195376 kb
Host smart-61187d8b-b04f-494f-899e-9a38f855c093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040282082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2040282082
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.152200600
Short name T539
Test name
Test status
Simulation time 12479228 ps
CPU time 0.59 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:56 PM PDT 24
Peak memory 195236 kb
Host smart-52d67829-00ec-4a21-afee-360f5080e447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152200600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.152200600
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2419518267
Short name T534
Test name
Test status
Simulation time 14959934 ps
CPU time 0.63 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 195296 kb
Host smart-8aa2fa3d-eb9f-48ec-8940-df9816c7179e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419518267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2419518267
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.4041127790
Short name T637
Test name
Test status
Simulation time 32916697 ps
CPU time 0.62 seconds
Started Aug 13 06:47:33 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 195328 kb
Host smart-c79dc948-fa17-4b11-8b44-41eb1c901f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041127790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.4041127790
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2788106719
Short name T560
Test name
Test status
Simulation time 19819426 ps
CPU time 0.59 seconds
Started Aug 13 06:47:52 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 195404 kb
Host smart-f462b82f-ebfd-4311-9769-343e2dae00a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788106719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2788106719
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3434740238
Short name T589
Test name
Test status
Simulation time 99438645 ps
CPU time 0.58 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 195356 kb
Host smart-6ea57cb4-01f5-4fc6-ac0c-98b4797f6ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434740238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3434740238
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.88532221
Short name T649
Test name
Test status
Simulation time 172183796 ps
CPU time 0.58 seconds
Started Aug 13 06:48:01 PM PDT 24
Finished Aug 13 06:48:02 PM PDT 24
Peak memory 195268 kb
Host smart-9ee2367e-6e82-4160-aeb8-5a74cf5b8398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88532221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.88532221
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2623655239
Short name T575
Test name
Test status
Simulation time 55653198 ps
CPU time 0.61 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 195304 kb
Host smart-183e3a27-e1ae-43db-90a9-b41c8e018881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623655239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2623655239
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2999254551
Short name T543
Test name
Test status
Simulation time 26623317 ps
CPU time 0.57 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:47:59 PM PDT 24
Peak memory 195260 kb
Host smart-450c8ea8-37a5-45e3-abe1-4240f51e73a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999254551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2999254551
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1080629877
Short name T112
Test name
Test status
Simulation time 6032991924 ps
CPU time 6.12 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 200468 kb
Host smart-ba1476ac-92ae-42c6-8375-cb1f9935c83f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080629877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1080629877
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.549006294
Short name T632
Test name
Test status
Simulation time 911164228 ps
CPU time 10.61 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:29 PM PDT 24
Peak memory 200340 kb
Host smart-5a0f4f94-bfc7-4509-83da-b7e4a48c9141
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549006294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.549006294
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1045060996
Short name T574
Test name
Test status
Simulation time 125391304 ps
CPU time 1.02 seconds
Started Aug 13 06:47:59 PM PDT 24
Finished Aug 13 06:48:00 PM PDT 24
Peak memory 199880 kb
Host smart-e8d96b85-00d4-4c9d-ae88-c2f1dcaefe2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045060996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1045060996
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1677396243
Short name T584
Test name
Test status
Simulation time 164245187087 ps
CPU time 610.93 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:57:33 PM PDT 24
Peak memory 225044 kb
Host smart-add2fd98-fd5b-4a2b-b09a-57799937e6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677396243 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1677396243
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2828981902
Short name T108
Test name
Test status
Simulation time 48794072 ps
CPU time 0.8 seconds
Started Aug 13 06:47:16 PM PDT 24
Finished Aug 13 06:47:16 PM PDT 24
Peak memory 199644 kb
Host smart-8d7e489e-0625-4cf0-8f8b-0b252ead407f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828981902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2828981902
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2614136812
Short name T585
Test name
Test status
Simulation time 33612405 ps
CPU time 0.63 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 195308 kb
Host smart-90ba1709-e59c-44a7-977f-c863758c8972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614136812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2614136812
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1097799923
Short name T625
Test name
Test status
Simulation time 371190260 ps
CPU time 1.67 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:40 PM PDT 24
Peak memory 200300 kb
Host smart-ac0137ac-0a14-4be1-b7f0-ddb34dc10e73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097799923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1097799923
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3924362177
Short name T601
Test name
Test status
Simulation time 1580245841 ps
CPU time 2.17 seconds
Started Aug 13 06:47:27 PM PDT 24
Finished Aug 13 06:47:30 PM PDT 24
Peak memory 200248 kb
Host smart-eea0edd9-e626-4538-b63e-feed8f0bae40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924362177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3924362177
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3132730208
Short name T126
Test name
Test status
Simulation time 183008951 ps
CPU time 2.92 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200292 kb
Host smart-d54ef06c-91a1-410f-acce-914c18879582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132730208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3132730208
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1212894255
Short name T608
Test name
Test status
Simulation time 32602798 ps
CPU time 0.59 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 195224 kb
Host smart-ab04c400-313e-4f98-9317-831dbbb5ee31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212894255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1212894255
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.515271088
Short name T626
Test name
Test status
Simulation time 42983954 ps
CPU time 0.59 seconds
Started Aug 13 06:48:02 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 195288 kb
Host smart-25b1aa9b-b6ac-4d62-ad55-1953a9fe489d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515271088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.515271088
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1759087575
Short name T609
Test name
Test status
Simulation time 14367937 ps
CPU time 0.62 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:54 PM PDT 24
Peak memory 195344 kb
Host smart-ce1f7016-0054-42c6-a08f-c382c24ed2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759087575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1759087575
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1364965007
Short name T642
Test name
Test status
Simulation time 28260373 ps
CPU time 0.63 seconds
Started Aug 13 06:47:53 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 195348 kb
Host smart-0da2c067-38d7-4f0a-8c2b-d9119f25ec24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364965007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1364965007
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1363243466
Short name T587
Test name
Test status
Simulation time 13809498 ps
CPU time 0.62 seconds
Started Aug 13 06:47:56 PM PDT 24
Finished Aug 13 06:47:57 PM PDT 24
Peak memory 195384 kb
Host smart-016cf551-fb81-42cf-85a5-d038cea41f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363243466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1363243466
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4015876148
Short name T540
Test name
Test status
Simulation time 27690003 ps
CPU time 0.64 seconds
Started Aug 13 06:47:52 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 195320 kb
Host smart-f17b9f4b-d744-40c3-aa50-a64464952c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015876148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4015876148
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3730365483
Short name T563
Test name
Test status
Simulation time 50052400 ps
CPU time 0.61 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 195352 kb
Host smart-bc0805f1-6c69-45bd-b984-760797bbc2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730365483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3730365483
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1773016559
Short name T537
Test name
Test status
Simulation time 13918201 ps
CPU time 0.59 seconds
Started Aug 13 06:47:50 PM PDT 24
Finished Aug 13 06:47:51 PM PDT 24
Peak memory 195300 kb
Host smart-1e90829d-78ad-43ce-a413-66376ec1eeaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773016559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1773016559
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1007805764
Short name T535
Test name
Test status
Simulation time 43757466 ps
CPU time 0.59 seconds
Started Aug 13 06:47:55 PM PDT 24
Finished Aug 13 06:47:55 PM PDT 24
Peak memory 195304 kb
Host smart-ee1f30a9-2d14-46ec-8e11-b0d818640451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007805764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1007805764
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1170742945
Short name T550
Test name
Test status
Simulation time 52134159 ps
CPU time 0.61 seconds
Started Aug 13 06:47:48 PM PDT 24
Finished Aug 13 06:47:49 PM PDT 24
Peak memory 195408 kb
Host smart-4bfe78ad-b206-4236-a558-f5c466f2a931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170742945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1170742945
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1586659451
Short name T557
Test name
Test status
Simulation time 53773879963 ps
CPU time 796.18 seconds
Started Aug 13 06:47:31 PM PDT 24
Finished Aug 13 07:00:47 PM PDT 24
Peak memory 224996 kb
Host smart-0230bc89-6cbf-4fcc-a681-11ed0710e847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586659451 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1586659451
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1594706901
Short name T581
Test name
Test status
Simulation time 50076630 ps
CPU time 0.66 seconds
Started Aug 13 06:47:35 PM PDT 24
Finished Aug 13 06:47:35 PM PDT 24
Peak memory 197728 kb
Host smart-711eda8b-ef7c-4ce8-8a4d-5f6729d467d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594706901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1594706901
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2361357361
Short name T593
Test name
Test status
Simulation time 20914573 ps
CPU time 0.55 seconds
Started Aug 13 06:47:19 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 195200 kb
Host smart-e4575b47-1d33-449e-9456-afb88b4c6c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361357361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2361357361
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3655424448
Short name T115
Test name
Test status
Simulation time 283175767 ps
CPU time 2.31 seconds
Started Aug 13 06:47:18 PM PDT 24
Finished Aug 13 06:47:20 PM PDT 24
Peak memory 200304 kb
Host smart-374fe5ad-4cb2-48f8-b47e-0462277a7864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655424448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3655424448
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1538767360
Short name T624
Test name
Test status
Simulation time 52870195 ps
CPU time 2.47 seconds
Started Aug 13 06:47:37 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 200356 kb
Host smart-95017b23-f44e-47e6-8ac4-8d1c506d93e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538767360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1538767360
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3380774637
Short name T55
Test name
Test status
Simulation time 340239154 ps
CPU time 3.09 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:52 PM PDT 24
Peak memory 200300 kb
Host smart-04d1f9fe-d5a0-4d8d-995c-905fee0a6bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380774637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3380774637
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.963757013
Short name T60
Test name
Test status
Simulation time 193931499 ps
CPU time 3.32 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 208632 kb
Host smart-bd66fed0-908b-4aca-a830-5a67f965bdf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963757013 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.963757013
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1584115800
Short name T600
Test name
Test status
Simulation time 53826645 ps
CPU time 0.97 seconds
Started Aug 13 06:47:36 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 200036 kb
Host smart-a1c4675b-8cd6-49c4-9f15-66f3ce130af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584115800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1584115800
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3180561435
Short name T541
Test name
Test status
Simulation time 55613171 ps
CPU time 0.61 seconds
Started Aug 13 06:47:25 PM PDT 24
Finished Aug 13 06:47:26 PM PDT 24
Peak memory 195400 kb
Host smart-001d41a8-ae4a-4179-801e-d47cbb6794d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180561435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3180561435
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1868379402
Short name T595
Test name
Test status
Simulation time 287676693 ps
CPU time 1.74 seconds
Started Aug 13 06:47:51 PM PDT 24
Finished Aug 13 06:47:53 PM PDT 24
Peak memory 200324 kb
Host smart-19a081b5-6b7e-4835-96f1-95fa2d1836f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868379402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1868379402
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2170870507
Short name T615
Test name
Test status
Simulation time 115999459 ps
CPU time 2.22 seconds
Started Aug 13 06:47:34 PM PDT 24
Finished Aug 13 06:47:36 PM PDT 24
Peak memory 200304 kb
Host smart-8af16813-a5d9-4cad-a084-85eec8b3f437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170870507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2170870507
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.259288457
Short name T599
Test name
Test status
Simulation time 464047442 ps
CPU time 4.65 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:45 PM PDT 24
Peak memory 200296 kb
Host smart-ef1791ea-0895-46ec-9ded-637dc4482de5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259288457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.259288457
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.858623050
Short name T610
Test name
Test status
Simulation time 87342024 ps
CPU time 1.71 seconds
Started Aug 13 06:47:46 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200468 kb
Host smart-2357dc25-3bdb-4143-8bb2-8cde02733483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858623050 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.858623050
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.101258682
Short name T102
Test name
Test status
Simulation time 44960071 ps
CPU time 0.98 seconds
Started Aug 13 06:47:37 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 200088 kb
Host smart-ee90eb95-d401-4d05-8e58-4c7b5335c3c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101258682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.101258682
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1294231188
Short name T571
Test name
Test status
Simulation time 28812651 ps
CPU time 0.61 seconds
Started Aug 13 06:47:45 PM PDT 24
Finished Aug 13 06:47:46 PM PDT 24
Peak memory 195344 kb
Host smart-9e555295-f484-4558-a29f-b008e78999a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294231188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1294231188
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1833586720
Short name T631
Test name
Test status
Simulation time 76924847 ps
CPU time 1.1 seconds
Started Aug 13 06:47:40 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 200344 kb
Host smart-f9a35f91-64f9-4b32-b232-bbd7164342f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833586720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1833586720
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.856998440
Short name T568
Test name
Test status
Simulation time 246140824 ps
CPU time 2.89 seconds
Started Aug 13 06:47:21 PM PDT 24
Finished Aug 13 06:47:24 PM PDT 24
Peak memory 200356 kb
Host smart-04ce7b0b-5753-4b5a-b6fe-c42c10a02e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856998440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.856998440
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2617981302
Short name T128
Test name
Test status
Simulation time 85747578 ps
CPU time 1.78 seconds
Started Aug 13 06:47:49 PM PDT 24
Finished Aug 13 06:47:50 PM PDT 24
Peak memory 200240 kb
Host smart-836659ee-be85-44b3-be4b-b68258e2eabc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617981302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2617981302
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1030681407
Short name T598
Test name
Test status
Simulation time 643626733 ps
CPU time 2.36 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:41 PM PDT 24
Peak memory 200376 kb
Host smart-eddb722b-dcca-418e-a19a-ba07a7aa77ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030681407 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1030681407
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1620121627
Short name T576
Test name
Test status
Simulation time 167717653 ps
CPU time 0.95 seconds
Started Aug 13 06:47:41 PM PDT 24
Finished Aug 13 06:47:42 PM PDT 24
Peak memory 200132 kb
Host smart-7e644302-1a04-49ca-b09d-acdc7f2ea36c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620121627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1620121627
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.756442333
Short name T549
Test name
Test status
Simulation time 44816537 ps
CPU time 0.61 seconds
Started Aug 13 06:47:43 PM PDT 24
Finished Aug 13 06:47:44 PM PDT 24
Peak memory 195384 kb
Host smart-1cdbb6fd-7188-4df9-bcac-e231ec19f4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756442333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.756442333
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1848524271
Short name T629
Test name
Test status
Simulation time 76077242 ps
CPU time 1.02 seconds
Started Aug 13 06:47:44 PM PDT 24
Finished Aug 13 06:47:45 PM PDT 24
Peak memory 200296 kb
Host smart-d13cbe0e-b971-4436-87b5-2be30befaa29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848524271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1848524271
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3510506002
Short name T628
Test name
Test status
Simulation time 132954626 ps
CPU time 1.55 seconds
Started Aug 13 06:47:38 PM PDT 24
Finished Aug 13 06:47:39 PM PDT 24
Peak memory 200360 kb
Host smart-d9aead49-abc9-41af-a3fe-bd5182eef237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510506002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3510506002
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2724124655
Short name T57
Test name
Test status
Simulation time 325033643 ps
CPU time 2.81 seconds
Started Aug 13 06:47:31 PM PDT 24
Finished Aug 13 06:47:34 PM PDT 24
Peak memory 200264 kb
Host smart-75ad5ead-16da-4b3d-b0b3-3640d778c219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724124655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2724124655
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.292547894
Short name T62
Test name
Test status
Simulation time 53442687 ps
CPU time 3.33 seconds
Started Aug 13 06:47:35 PM PDT 24
Finished Aug 13 06:47:38 PM PDT 24
Peak memory 208536 kb
Host smart-aa499efd-ec81-4622-9c5b-4a1219e789cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292547894 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.292547894
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2551219001
Short name T100
Test name
Test status
Simulation time 19280901 ps
CPU time 0.9 seconds
Started Aug 13 06:47:44 PM PDT 24
Finished Aug 13 06:47:45 PM PDT 24
Peak memory 200080 kb
Host smart-f5b6294a-df8f-4215-9d41-946c8e958c85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551219001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2551219001
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2931858579
Short name T554
Test name
Test status
Simulation time 56030026 ps
CPU time 0.58 seconds
Started Aug 13 06:47:46 PM PDT 24
Finished Aug 13 06:47:47 PM PDT 24
Peak memory 195268 kb
Host smart-2cdb4da1-9c52-43f2-99bc-ec2d1f0255f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931858579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2931858579
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.980331260
Short name T588
Test name
Test status
Simulation time 102951959 ps
CPU time 1.12 seconds
Started Aug 13 06:47:44 PM PDT 24
Finished Aug 13 06:47:45 PM PDT 24
Peak memory 200120 kb
Host smart-ee23d7b7-01ce-423e-b5e6-49da462a0d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980331260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.980331260
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1571891682
Short name T558
Test name
Test status
Simulation time 344038702 ps
CPU time 1.91 seconds
Started Aug 13 06:47:35 PM PDT 24
Finished Aug 13 06:47:37 PM PDT 24
Peak memory 200272 kb
Host smart-bf1d205e-be3c-46d3-8c90-23cc4cd6db4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571891682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1571891682
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3798679117
Short name T129
Test name
Test status
Simulation time 908779638 ps
CPU time 4.17 seconds
Started Aug 13 06:47:43 PM PDT 24
Finished Aug 13 06:47:48 PM PDT 24
Peak memory 200296 kb
Host smart-29339a27-7a27-4eb7-9d82-2bdf8d278da7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798679117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3798679117
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2902010384
Short name T501
Test name
Test status
Simulation time 17520174 ps
CPU time 0.6 seconds
Started Aug 13 06:31:37 PM PDT 24
Finished Aug 13 06:31:38 PM PDT 24
Peak memory 196780 kb
Host smart-9aae23a4-904d-4d87-af93-39bf2a339355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902010384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2902010384
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3119940926
Short name T17
Test name
Test status
Simulation time 8816813411 ps
CPU time 86.23 seconds
Started Aug 13 06:31:48 PM PDT 24
Finished Aug 13 06:33:14 PM PDT 24
Peak memory 200688 kb
Host smart-808e4ca0-3dde-4bc7-a8d6-77e691a520a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119940926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3119940926
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1088025982
Short name T390
Test name
Test status
Simulation time 244389803 ps
CPU time 3.44 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:31:41 PM PDT 24
Peak memory 200628 kb
Host smart-fe8ed980-4bed-4440-8e4a-772126a905fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088025982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1088025982
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1094231584
Short name T190
Test name
Test status
Simulation time 13782710652 ps
CPU time 1975.09 seconds
Started Aug 13 06:31:28 PM PDT 24
Finished Aug 13 07:04:24 PM PDT 24
Peak memory 740824 kb
Host smart-4b110790-94d5-42e0-a057-3d6f3efbbf96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094231584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1094231584
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2156982391
Short name T514
Test name
Test status
Simulation time 133944309 ps
CPU time 7.45 seconds
Started Aug 13 06:31:36 PM PDT 24
Finished Aug 13 06:31:44 PM PDT 24
Peak memory 200564 kb
Host smart-2c927a51-bbe1-45fe-866a-30c3d7eb1e3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156982391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2156982391
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2567935636
Short name T430
Test name
Test status
Simulation time 3162831618 ps
CPU time 60.11 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 06:32:30 PM PDT 24
Peak memory 200812 kb
Host smart-bcc46936-41c6-40ab-b853-c9f1d2a69056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567935636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2567935636
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3099061027
Short name T447
Test name
Test status
Simulation time 535284500 ps
CPU time 12.72 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 06:31:43 PM PDT 24
Peak memory 200684 kb
Host smart-83e621f7-963f-4736-b5c9-e88ea1b7cc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099061027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3099061027
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.938044459
Short name T455
Test name
Test status
Simulation time 609398668 ps
CPU time 29.92 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:31:59 PM PDT 24
Peak memory 200760 kb
Host smart-b8e5a218-7eb3-489b-8083-a0143bd75b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938044459 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.938044459
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2591178476
Short name T414
Test name
Test status
Simulation time 2409399948 ps
CPU time 44.53 seconds
Started Aug 13 06:31:47 PM PDT 24
Finished Aug 13 06:32:31 PM PDT 24
Peak memory 200704 kb
Host smart-dab5f262-794c-4256-9e20-424185745cbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2591178476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2591178476
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3116375614
Short name T377
Test name
Test status
Simulation time 4305543716 ps
CPU time 69.37 seconds
Started Aug 13 06:31:27 PM PDT 24
Finished Aug 13 06:32:37 PM PDT 24
Peak memory 200768 kb
Host smart-6c9a2e61-b464-434d-9ff8-51ec6d592915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3116375614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3116375614
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.815704938
Short name T360
Test name
Test status
Simulation time 55681886641 ps
CPU time 130.61 seconds
Started Aug 13 06:31:45 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 200708 kb
Host smart-8ddeed77-46f6-4193-89c2-b2acb2be1863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=815704938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.815704938
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2476169288
Short name T398
Test name
Test status
Simulation time 9685173745 ps
CPU time 537.6 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:40:40 PM PDT 24
Peak memory 200656 kb
Host smart-6ef73c6f-7f53-4c7a-a4dc-6170beb0f0c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2476169288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2476169288
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1386212989
Short name T133
Test name
Test status
Simulation time 1079841356542 ps
CPU time 2404.21 seconds
Started Aug 13 06:31:25 PM PDT 24
Finished Aug 13 07:11:31 PM PDT 24
Peak memory 216168 kb
Host smart-635c02e2-87d3-481f-8484-4082b3b6a539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1386212989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1386212989
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.780236194
Short name T195
Test name
Test status
Simulation time 755753416466 ps
CPU time 2514.61 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 07:13:26 PM PDT 24
Peak memory 216228 kb
Host smart-e0d0710d-47b1-40d8-b6e4-d468d8833dff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=780236194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.780236194
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.107680839
Short name T277
Test name
Test status
Simulation time 3325735961 ps
CPU time 105.2 seconds
Started Aug 13 06:31:44 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 200756 kb
Host smart-c81dbe12-8805-4176-8989-49cda965a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107680839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.107680839
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2347136521
Short name T305
Test name
Test status
Simulation time 13714043 ps
CPU time 0.6 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:31:50 PM PDT 24
Peak memory 196368 kb
Host smart-95dac808-e73f-4ef4-9e00-e17e53351ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347136521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2347136521
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4010590545
Short name T15
Test name
Test status
Simulation time 5443521170 ps
CPU time 78.17 seconds
Started Aug 13 06:31:28 PM PDT 24
Finished Aug 13 06:32:46 PM PDT 24
Peak memory 200776 kb
Host smart-6bc3d399-f8d3-4167-9eec-007306a1df14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010590545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4010590545
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3770768422
Short name T520
Test name
Test status
Simulation time 275073928 ps
CPU time 5.22 seconds
Started Aug 13 06:31:31 PM PDT 24
Finished Aug 13 06:31:36 PM PDT 24
Peak memory 200664 kb
Host smart-39a7c513-e948-4e5f-b2d7-1de71f46eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770768422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3770768422
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3407170032
Short name T375
Test name
Test status
Simulation time 4609553606 ps
CPU time 266.51 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:36:08 PM PDT 24
Peak memory 625756 kb
Host smart-24ef1b8a-e780-402a-96e5-903cd4bdf840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407170032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3407170032
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2409703880
Short name T531
Test name
Test status
Simulation time 19397514050 ps
CPU time 57.55 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:32:27 PM PDT 24
Peak memory 200584 kb
Host smart-900d4521-d546-40db-b8a3-1a4e881622c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409703880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2409703880
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1946669455
Short name T41
Test name
Test status
Simulation time 121203590 ps
CPU time 0.83 seconds
Started Aug 13 06:31:35 PM PDT 24
Finished Aug 13 06:31:36 PM PDT 24
Peak memory 219020 kb
Host smart-0f4f310b-e7c3-414b-b4da-56c458f2f390
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946669455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1946669455
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1138135282
Short name T295
Test name
Test status
Simulation time 867741737 ps
CPU time 9.74 seconds
Started Aug 13 06:31:44 PM PDT 24
Finished Aug 13 06:31:54 PM PDT 24
Peak memory 200672 kb
Host smart-07d2818e-d66a-4177-a3ae-f401fc227041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138135282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1138135282
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3516142030
Short name T68
Test name
Test status
Simulation time 165286525577 ps
CPU time 598.08 seconds
Started Aug 13 06:31:27 PM PDT 24
Finished Aug 13 06:41:25 PM PDT 24
Peak memory 461104 kb
Host smart-c2b729c9-93e2-4ab0-bd2c-566bda685e84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516142030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3516142030
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2399870283
Short name T20
Test name
Test status
Simulation time 26477478531 ps
CPU time 633.43 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 673096 kb
Host smart-34c893ce-943b-4d47-a872-f9be27b9e7c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399870283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2399870283
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.807286889
Short name T495
Test name
Test status
Simulation time 35856537026 ps
CPU time 68.38 seconds
Started Aug 13 06:31:32 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 200684 kb
Host smart-103afa93-c66a-4e4f-955f-8b0402e4c082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=807286889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.807286889
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.4215804053
Short name T242
Test name
Test status
Simulation time 5570735683 ps
CPU time 64.06 seconds
Started Aug 13 06:31:26 PM PDT 24
Finished Aug 13 06:32:30 PM PDT 24
Peak memory 200740 kb
Host smart-dbdb3844-b355-4533-beff-5c2e6e3fe12c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4215804053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.4215804053
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.4252749156
Short name T73
Test name
Test status
Simulation time 31833481750 ps
CPU time 111.37 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 06:33:21 PM PDT 24
Peak memory 200736 kb
Host smart-f94ae6d1-a6ba-476b-bf80-9a7458e74bb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4252749156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.4252749156
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2311742366
Short name T374
Test name
Test status
Simulation time 96577516372 ps
CPU time 600.48 seconds
Started Aug 13 06:31:30 PM PDT 24
Finished Aug 13 06:41:31 PM PDT 24
Peak memory 200712 kb
Host smart-008ada62-ac6e-40b3-9450-2a5826a01e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2311742366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2311742366
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.109807220
Short name T134
Test name
Test status
Simulation time 434889653012 ps
CPU time 2762.71 seconds
Started Aug 13 06:31:27 PM PDT 24
Finished Aug 13 07:17:31 PM PDT 24
Peak memory 216132 kb
Host smart-db2d8850-2d57-45ed-b19f-4a802890ae1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=109807220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.109807220
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3441323150
Short name T491
Test name
Test status
Simulation time 350593994038 ps
CPU time 2326.71 seconds
Started Aug 13 06:31:41 PM PDT 24
Finished Aug 13 07:10:28 PM PDT 24
Peak memory 216200 kb
Host smart-edf2c985-c1e3-4302-a581-fb04e89e4fd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3441323150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3441323150
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3728845838
Short name T234
Test name
Test status
Simulation time 2395229305 ps
CPU time 58.87 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 200736 kb
Host smart-093f8236-09b5-4b1c-9415-f9fbad0b8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728845838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3728845838
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3275184516
Short name T47
Test name
Test status
Simulation time 15484500 ps
CPU time 0.59 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:31:50 PM PDT 24
Peak memory 197436 kb
Host smart-31663056-97e1-486a-bc2d-2393f563147b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275184516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3275184516
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.96609881
Short name T432
Test name
Test status
Simulation time 6571374167 ps
CPU time 53.58 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:32:46 PM PDT 24
Peak memory 200764 kb
Host smart-667fbe03-91d8-4d5a-95b1-f1bab7dbfbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96609881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.96609881
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2242350349
Short name T215
Test name
Test status
Simulation time 3810821914 ps
CPU time 17.72 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:32:14 PM PDT 24
Peak memory 200732 kb
Host smart-1e31ecd2-2aca-4ec5-b4ef-51b99ccd1a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242350349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2242350349
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.917782
Short name T336
Test name
Test status
Simulation time 1109577440 ps
CPU time 77.12 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:33:13 PM PDT 24
Peak memory 351052 kb
Host smart-ca07eba3-12fc-4ca0-8e6a-8a30adef4e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.917782
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.773641392
Short name T223
Test name
Test status
Simulation time 30569036255 ps
CPU time 101.56 seconds
Started Aug 13 06:31:48 PM PDT 24
Finished Aug 13 06:33:30 PM PDT 24
Peak memory 200756 kb
Host smart-208db01d-7e44-45bd-ad55-14dbe6bc1002
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773641392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.773641392
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.598720535
Short name T226
Test name
Test status
Simulation time 5176505597 ps
CPU time 32.79 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:32:29 PM PDT 24
Peak memory 200720 kb
Host smart-74eb8f8a-053b-4515-9429-12c1c75387d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598720535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.598720535
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2090843881
Short name T294
Test name
Test status
Simulation time 2371082260 ps
CPU time 10.49 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 200828 kb
Host smart-8d349502-54ce-4f2e-b402-027557889b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090843881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2090843881
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1497763154
Short name T65
Test name
Test status
Simulation time 143578674653 ps
CPU time 1677.8 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:59:36 PM PDT 24
Peak memory 716616 kb
Host smart-9963e6b3-cfc0-44b9-ba38-948cf05facbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497763154 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1497763154
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.521291884
Short name T96
Test name
Test status
Simulation time 38976816802 ps
CPU time 125.57 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:34:08 PM PDT 24
Peak memory 200776 kb
Host smart-ae34f272-23d7-4f14-8927-cb7f1eef4d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521291884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.521291884
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1176766642
Short name T276
Test name
Test status
Simulation time 155335254 ps
CPU time 0.59 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:31:55 PM PDT 24
Peak memory 196440 kb
Host smart-486ab077-d8ff-4bd6-96fd-00f4bd823dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176766642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1176766642
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2049724416
Short name T272
Test name
Test status
Simulation time 3107279489 ps
CPU time 24.17 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:32:18 PM PDT 24
Peak memory 200764 kb
Host smart-6ae934a5-1845-4fe2-8e0b-6e543d367bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049724416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2049724416
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.36668568
Short name T477
Test name
Test status
Simulation time 3151583344 ps
CPU time 41.39 seconds
Started Aug 13 06:31:35 PM PDT 24
Finished Aug 13 06:32:17 PM PDT 24
Peak memory 200720 kb
Host smart-b9875ea4-6130-4181-8430-e6e9ff101413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36668568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.36668568
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3904137020
Short name T356
Test name
Test status
Simulation time 9186090561 ps
CPU time 397.97 seconds
Started Aug 13 06:31:46 PM PDT 24
Finished Aug 13 06:38:24 PM PDT 24
Peak memory 668896 kb
Host smart-6e7068cc-44d8-48d4-a6cd-1b998deaac72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904137020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3904137020
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.810833953
Short name T263
Test name
Test status
Simulation time 7270031307 ps
CPU time 89.06 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 200688 kb
Host smart-03c93ec0-813d-4100-a19d-ff05f1e13f67
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810833953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.810833953
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.997111683
Short name T505
Test name
Test status
Simulation time 2809108674 ps
CPU time 158.94 seconds
Started Aug 13 06:31:44 PM PDT 24
Finished Aug 13 06:34:23 PM PDT 24
Peak memory 200872 kb
Host smart-becb06e0-5b6c-4045-8a91-96d3512db8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997111683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.997111683
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_stress_all.220399623
Short name T119
Test name
Test status
Simulation time 303182105996 ps
CPU time 3965.46 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 07:38:00 PM PDT 24
Peak memory 808900 kb
Host smart-17d95caa-8f81-4fb1-8a8c-cbf35f6d4f7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220399623 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.220399623
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3948167922
Short name T94
Test name
Test status
Simulation time 23532261007 ps
CPU time 73.03 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 200756 kb
Host smart-583daa6a-bfbb-45cc-ae08-fd24fbc86354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948167922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3948167922
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3881452745
Short name T410
Test name
Test status
Simulation time 13574472 ps
CPU time 0.59 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:31:44 PM PDT 24
Peak memory 195716 kb
Host smart-05332bec-25c5-4950-a92a-0eb4bce7430b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881452745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3881452745
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.583020007
Short name T384
Test name
Test status
Simulation time 1130870687 ps
CPU time 61.15 seconds
Started Aug 13 06:31:48 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 200692 kb
Host smart-693f9c45-712c-4042-a9aa-260a97529f14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583020007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.583020007
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2347123065
Short name T334
Test name
Test status
Simulation time 532766317 ps
CPU time 11.79 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:32:12 PM PDT 24
Peak memory 200684 kb
Host smart-a680e35f-a68b-417d-a8c7-3994fd53092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347123065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2347123065
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.324330159
Short name T406
Test name
Test status
Simulation time 10058358109 ps
CPU time 861 seconds
Started Aug 13 06:31:50 PM PDT 24
Finished Aug 13 06:46:11 PM PDT 24
Peak memory 707680 kb
Host smart-a3f7cbed-6d5b-4036-9250-088d9cb2df67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324330159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.324330159
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3873160783
Short name T304
Test name
Test status
Simulation time 2667830242 ps
CPU time 44.68 seconds
Started Aug 13 06:31:50 PM PDT 24
Finished Aug 13 06:32:34 PM PDT 24
Peak memory 200716 kb
Host smart-89c44b0c-ca3c-49c0-ba41-6ffe10e93614
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873160783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3873160783
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3665128515
Short name T330
Test name
Test status
Simulation time 12604140167 ps
CPU time 161.04 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:34:34 PM PDT 24
Peak memory 208908 kb
Host smart-484e9dd8-df7d-4bb6-b36e-70dee5cc812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665128515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3665128515
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1242522309
Short name T391
Test name
Test status
Simulation time 246093707 ps
CPU time 3.11 seconds
Started Aug 13 06:31:44 PM PDT 24
Finished Aug 13 06:31:47 PM PDT 24
Peak memory 200704 kb
Host smart-13d4b2c9-89f6-4bd3-a808-9e2826845558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242522309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1242522309
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.276195081
Short name T66
Test name
Test status
Simulation time 522702075915 ps
CPU time 4565.42 seconds
Started Aug 13 06:32:01 PM PDT 24
Finished Aug 13 07:48:08 PM PDT 24
Peak memory 852176 kb
Host smart-74f85f6f-1919-4c08-b799-16b4a4e0d128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276195081 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.276195081
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1355821453
Short name T239
Test name
Test status
Simulation time 1735823499 ps
CPU time 26.03 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:32:18 PM PDT 24
Peak memory 200580 kb
Host smart-e8ec6b6b-ecc1-456b-97d0-f938d173df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355821453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1355821453
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1884427873
Short name T394
Test name
Test status
Simulation time 16598010 ps
CPU time 0.6 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:31:57 PM PDT 24
Peak memory 196760 kb
Host smart-4da00958-77a6-42f4-b2bc-14a2c4b7da7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884427873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1884427873
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1455689430
Short name T397
Test name
Test status
Simulation time 529621551 ps
CPU time 11.4 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 200672 kb
Host smart-e700f8ce-da92-48ea-9254-79417acbb14e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455689430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1455689430
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3157531877
Short name T228
Test name
Test status
Simulation time 33566615314 ps
CPU time 53.98 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 200724 kb
Host smart-9c2ce3ee-e072-43c8-adca-1f12ed02441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157531877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3157531877
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3311332507
Short name T167
Test name
Test status
Simulation time 4243316864 ps
CPU time 772.1 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:45:01 PM PDT 24
Peak memory 745928 kb
Host smart-fefa1b58-1dd1-4797-8f66-e44f5f91dbc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311332507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3311332507
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2692534035
Short name T169
Test name
Test status
Simulation time 3206613427 ps
CPU time 45.71 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 200620 kb
Host smart-929de5a6-9ac0-4756-bf62-694075150f0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692534035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2692534035
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.640945001
Short name T252
Test name
Test status
Simulation time 1352906949 ps
CPU time 18.7 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:26 PM PDT 24
Peak memory 200656 kb
Host smart-3fab42ee-f1df-4905-9fc7-0def68ccb23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640945001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.640945001
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3278549921
Short name T415
Test name
Test status
Simulation time 637850861 ps
CPU time 15.01 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:31:57 PM PDT 24
Peak memory 200696 kb
Host smart-5ffcc04d-bea3-48a1-a556-92f17004d9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278549921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3278549921
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1406917039
Short name T498
Test name
Test status
Simulation time 166503400715 ps
CPU time 1014.69 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:48:55 PM PDT 24
Peak memory 696680 kb
Host smart-428f9f9d-84ad-4a1b-b72c-f0a2adf03040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406917039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1406917039
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.620027281
Short name T72
Test name
Test status
Simulation time 11798310099 ps
CPU time 105.87 seconds
Started Aug 13 06:32:03 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 200744 kb
Host smart-e914e5d7-871b-4f04-a5d7-be685abc066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620027281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.620027281
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2364045175
Short name T261
Test name
Test status
Simulation time 31678034 ps
CPU time 0.58 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:06 PM PDT 24
Peak memory 195756 kb
Host smart-7bd0b2ae-ab4d-4393-9a5f-776fdc3cc4bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364045175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2364045175
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1993074379
Short name T14
Test name
Test status
Simulation time 1267097274 ps
CPU time 72.58 seconds
Started Aug 13 06:32:01 PM PDT 24
Finished Aug 13 06:33:13 PM PDT 24
Peak memory 200696 kb
Host smart-e69aeb08-74ad-415b-976f-add6ad9a4124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993074379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1993074379
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2868621179
Short name T145
Test name
Test status
Simulation time 9501407080 ps
CPU time 34.45 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:43 PM PDT 24
Peak memory 200752 kb
Host smart-864ce947-f4dd-4037-9a1b-abab3c234022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868621179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2868621179
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3369253839
Short name T523
Test name
Test status
Simulation time 13781651413 ps
CPU time 649.64 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 747952 kb
Host smart-0d4a21fe-b829-4e6f-8e34-bc4f37c9acb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369253839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3369253839
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.691395323
Short name T341
Test name
Test status
Simulation time 9610269341 ps
CPU time 137.1 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:34:22 PM PDT 24
Peak memory 200728 kb
Host smart-439b2b9d-a168-4100-8e83-9159c7c5a18b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691395323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.691395323
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.275724665
Short name T222
Test name
Test status
Simulation time 15814278411 ps
CPU time 65.12 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 200840 kb
Host smart-e70489f0-f60a-4b27-b09e-8a0bcedbfba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275724665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.275724665
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2164428156
Short name T362
Test name
Test status
Simulation time 399520265 ps
CPU time 5.23 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:31:47 PM PDT 24
Peak memory 200700 kb
Host smart-96c0f60f-c96d-419a-a900-f4a9763818e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164428156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2164428156
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3320697570
Short name T192
Test name
Test status
Simulation time 136500752654 ps
CPU time 191.83 seconds
Started Aug 13 06:32:03 PM PDT 24
Finished Aug 13 06:35:15 PM PDT 24
Peak memory 217144 kb
Host smart-e393f7d9-4d2c-4e1a-b973-a37eb8667d52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320697570 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3320697570
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3276755626
Short name T413
Test name
Test status
Simulation time 1173847575 ps
CPU time 33.3 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 200708 kb
Host smart-4ec8c495-7281-4834-a4ce-5caa7b8f4c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276755626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3276755626
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2627437395
Short name T315
Test name
Test status
Simulation time 37973887 ps
CPU time 0.58 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 06:32:00 PM PDT 24
Peak memory 195744 kb
Host smart-93885b0c-ebad-465b-bc17-0cdce478474a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627437395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2627437395
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1534031973
Short name T493
Test name
Test status
Simulation time 3827704934 ps
CPU time 89.6 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:33:37 PM PDT 24
Peak memory 200704 kb
Host smart-bc0239a6-2eb5-4de6-b838-8af695eb0f24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534031973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1534031973
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2934998728
Short name T30
Test name
Test status
Simulation time 2800009962 ps
CPU time 49.92 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 216964 kb
Host smart-bb181cd8-6ee4-45c0-bae9-38a89d96e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934998728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2934998728
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1888140367
Short name T522
Test name
Test status
Simulation time 4933558421 ps
CPU time 921.81 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:47:15 PM PDT 24
Peak memory 720484 kb
Host smart-bf3c748d-bd00-4d39-96a4-9d3108912053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888140367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1888140367
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1596965022
Short name T154
Test name
Test status
Simulation time 67305004660 ps
CPU time 150.37 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:34:25 PM PDT 24
Peak memory 200644 kb
Host smart-92903592-dc84-440e-807e-ba8388511a2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596965022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1596965022
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1314718841
Short name T164
Test name
Test status
Simulation time 10323664393 ps
CPU time 35.83 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:43 PM PDT 24
Peak memory 200776 kb
Host smart-3ac530be-c35a-4a32-8de0-3b96fc1664b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314718841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1314718841
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4025889733
Short name T448
Test name
Test status
Simulation time 96258740 ps
CPU time 1.68 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:31:58 PM PDT 24
Peak memory 200616 kb
Host smart-ad5f899b-23be-4409-8977-93ec63f44c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025889733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4025889733
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2897633057
Short name T519
Test name
Test status
Simulation time 13162216370 ps
CPU time 224.93 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:35:40 PM PDT 24
Peak memory 200732 kb
Host smart-5aa80dc6-a829-45d8-8040-cf5c7f078f9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897633057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2897633057
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.470414281
Short name T457
Test name
Test status
Simulation time 15955471701 ps
CPU time 54.6 seconds
Started Aug 13 06:31:47 PM PDT 24
Finished Aug 13 06:32:42 PM PDT 24
Peak memory 200780 kb
Host smart-b0bb48a9-e617-4edf-9f44-3ccec575762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470414281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.470414281
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1593213177
Short name T210
Test name
Test status
Simulation time 16519084 ps
CPU time 0.56 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:31:55 PM PDT 24
Peak memory 196420 kb
Host smart-1c7d940b-3908-4c44-be52-b29321a4d9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593213177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1593213177
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.622700699
Short name T489
Test name
Test status
Simulation time 5517625615 ps
CPU time 87.02 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 200760 kb
Host smart-fdc719ae-55d3-4a8a-9ed6-aa49c7f89fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622700699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.622700699
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2839586432
Short name T298
Test name
Test status
Simulation time 1780625747 ps
CPU time 7.29 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 200684 kb
Host smart-5dcf81c6-00d4-4391-80a3-2d37c61da6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839586432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2839586432
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3791795090
Short name T311
Test name
Test status
Simulation time 3735265005 ps
CPU time 283.03 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:36:38 PM PDT 24
Peak memory 503628 kb
Host smart-b601f60c-50af-4fad-95ab-b660e34f3ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791795090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3791795090
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4023068722
Short name T517
Test name
Test status
Simulation time 21941053481 ps
CPU time 183.55 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:35:09 PM PDT 24
Peak memory 200708 kb
Host smart-196bd030-f66a-4610-be15-216c1a40c24a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023068722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4023068722
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3597738075
Short name T438
Test name
Test status
Simulation time 10986588770 ps
CPU time 194.26 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:35:22 PM PDT 24
Peak memory 208984 kb
Host smart-063b9a67-1108-4f23-94c9-cb03e73780cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597738075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3597738075
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1103804820
Short name T351
Test name
Test status
Simulation time 182669826 ps
CPU time 2.06 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:10 PM PDT 24
Peak memory 200656 kb
Host smart-92f591d6-6353-4621-82e7-f690dce2c4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103804820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1103804820
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3527062515
Short name T11
Test name
Test status
Simulation time 11542827355 ps
CPU time 616.65 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:42:36 PM PDT 24
Peak memory 200760 kb
Host smart-91603b57-06f9-4129-97ba-ded9b1b56d82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527062515 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3527062515
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1806930645
Short name T389
Test name
Test status
Simulation time 7467663514 ps
CPU time 108.84 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:33:38 PM PDT 24
Peak memory 200772 kb
Host smart-78d4e9b0-31b2-4257-af87-79e45b9e5024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806930645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1806930645
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.953168869
Short name T340
Test name
Test status
Simulation time 17468899 ps
CPU time 0.57 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:32:14 PM PDT 24
Peak memory 196360 kb
Host smart-b4cf0897-3a2f-4b7f-8a27-ad3acce08f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953168869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.953168869
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.208233450
Short name T1
Test name
Test status
Simulation time 594477846 ps
CPU time 36.04 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:32:32 PM PDT 24
Peak memory 200636 kb
Host smart-38b12068-d743-4520-b5aa-2c13b68e14e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208233450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.208233450
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1003000243
Short name T467
Test name
Test status
Simulation time 1729419295 ps
CPU time 16.68 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:23 PM PDT 24
Peak memory 200708 kb
Host smart-501ad289-1e4c-44a1-ab1d-96f1aa20e1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003000243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1003000243
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1889505229
Short name T335
Test name
Test status
Simulation time 23920908276 ps
CPU time 950.67 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:47:58 PM PDT 24
Peak memory 778068 kb
Host smart-74a1da91-507d-4150-a6b1-95ed9c11fdfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889505229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1889505229
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.614030273
Short name T387
Test name
Test status
Simulation time 14794315313 ps
CPU time 221.03 seconds
Started Aug 13 06:31:47 PM PDT 24
Finished Aug 13 06:35:28 PM PDT 24
Peak memory 200764 kb
Host smart-66ad176a-3769-4fde-a8e7-7877829ca701
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614030273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.614030273
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2149115545
Short name T136
Test name
Test status
Simulation time 37876118189 ps
CPU time 179.04 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:34:54 PM PDT 24
Peak memory 201204 kb
Host smart-a7b5efe3-fa10-48e4-9359-b9c7b1d9170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149115545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2149115545
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3132476353
Short name T285
Test name
Test status
Simulation time 833112996 ps
CPU time 3.09 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:31:58 PM PDT 24
Peak memory 200760 kb
Host smart-c96c0a98-a521-4122-ac9c-fb7349feb54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132476353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3132476353
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3076907587
Short name T322
Test name
Test status
Simulation time 9404441523 ps
CPU time 1214.77 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:52:20 PM PDT 24
Peak memory 730960 kb
Host smart-f5de1784-5638-4fcc-9782-61b2e4aab2c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076907587 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3076907587
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1542774308
Short name T339
Test name
Test status
Simulation time 232720000 ps
CPU time 12.94 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:32:17 PM PDT 24
Peak memory 200640 kb
Host smart-b1e8849f-9d65-4f28-a56f-22f3782002e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542774308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1542774308
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2166419268
Short name T440
Test name
Test status
Simulation time 14535298 ps
CPU time 0.59 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 06:32:00 PM PDT 24
Peak memory 195720 kb
Host smart-4c4702d9-a93a-4d94-baea-fdec7e456528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166419268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2166419268
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3651826305
Short name T302
Test name
Test status
Simulation time 285774546 ps
CPU time 3.15 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:31:52 PM PDT 24
Peak memory 200532 kb
Host smart-13200aa2-8fd5-45b5-9c90-3d01f291068a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651826305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3651826305
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.674806636
Short name T172
Test name
Test status
Simulation time 1525961334 ps
CPU time 20.23 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 06:32:20 PM PDT 24
Peak memory 200724 kb
Host smart-98899823-3ca1-4368-b5bf-1b73871f2391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674806636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.674806636
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2317137642
Short name T470
Test name
Test status
Simulation time 3070623787 ps
CPU time 135.88 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 468076 kb
Host smart-fa54954d-4fca-478b-8250-37aa61534285
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317137642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2317137642
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1601598232
Short name T412
Test name
Test status
Simulation time 3728651697 ps
CPU time 32.09 seconds
Started Aug 13 06:32:01 PM PDT 24
Finished Aug 13 06:32:33 PM PDT 24
Peak memory 200712 kb
Host smart-f9f3d76c-2152-4fdb-8b3b-2e3ea32c0558
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601598232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1601598232
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3034308574
Short name T271
Test name
Test status
Simulation time 4219511928 ps
CPU time 49.43 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:32:39 PM PDT 24
Peak memory 200700 kb
Host smart-36af1abf-aa71-43aa-962c-f9020dfb3993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034308574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3034308574
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.360178939
Short name T439
Test name
Test status
Simulation time 778958523 ps
CPU time 9.47 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 200716 kb
Host smart-a592161b-2588-41d6-b20a-cb18b07fb38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360178939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.360178939
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1093521953
Short name T471
Test name
Test status
Simulation time 16924868773 ps
CPU time 159.44 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:34:50 PM PDT 24
Peak memory 200824 kb
Host smart-150b137d-de24-4b03-8a5e-d88bf18225a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093521953 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1093521953
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1506088930
Short name T323
Test name
Test status
Simulation time 3378215822 ps
CPU time 47.9 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:32:37 PM PDT 24
Peak memory 200840 kb
Host smart-7f147221-78e8-4a5a-a08d-9031e144f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506088930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1506088930
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1256848646
Short name T348
Test name
Test status
Simulation time 14287998 ps
CPU time 0.62 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:32:24 PM PDT 24
Peak memory 196340 kb
Host smart-57598f12-fe2a-49c3-9b82-b7ad60b4ceff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256848646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1256848646
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2768455051
Short name T328
Test name
Test status
Simulation time 4253629095 ps
CPU time 62.03 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:33:09 PM PDT 24
Peak memory 200904 kb
Host smart-181ab242-9fd7-4bfc-9d34-52a3c3a3fab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768455051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2768455051
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2606632712
Short name T528
Test name
Test status
Simulation time 6015064997 ps
CPU time 27.06 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:35 PM PDT 24
Peak memory 200788 kb
Host smart-5df56dbb-736b-4929-88d3-3cf46dd97fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606632712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2606632712
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3125511531
Short name T188
Test name
Test status
Simulation time 592279712 ps
CPU time 62.55 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:33:05 PM PDT 24
Peak memory 269160 kb
Host smart-6b48b3a6-52dc-4f2d-93f4-fa2bd5eed5e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125511531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3125511531
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.655063213
Short name T378
Test name
Test status
Simulation time 17958461805 ps
CPU time 56.56 seconds
Started Aug 13 06:32:14 PM PDT 24
Finished Aug 13 06:33:11 PM PDT 24
Peak memory 200720 kb
Host smart-94fe01c6-4922-489b-8fbe-53e46e0e175f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655063213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.655063213
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.744591840
Short name T83
Test name
Test status
Simulation time 3647807217 ps
CPU time 12.95 seconds
Started Aug 13 06:32:21 PM PDT 24
Finished Aug 13 06:32:34 PM PDT 24
Peak memory 200592 kb
Host smart-472474a8-3f88-448d-aaea-059b0968c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744591840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.744591840
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.725496567
Short name T472
Test name
Test status
Simulation time 341394893 ps
CPU time 4.18 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:32:01 PM PDT 24
Peak memory 200768 kb
Host smart-e6b6a2fc-0685-4127-80b1-53345e2f3a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725496567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.725496567
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2896436112
Short name T307
Test name
Test status
Simulation time 71802022705 ps
CPU time 2310.47 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 07:10:54 PM PDT 24
Peak memory 795264 kb
Host smart-798277cc-2d59-48e8-822a-a545f2cbe517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896436112 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2896436112
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.637838453
Short name T532
Test name
Test status
Simulation time 22579236249 ps
CPU time 94.72 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 200764 kb
Host smart-8396a1bf-051b-4354-a5bf-dfbfc7338755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637838453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.637838453
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2133962283
Short name T345
Test name
Test status
Simulation time 13128332 ps
CPU time 0.58 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:31:43 PM PDT 24
Peak memory 195548 kb
Host smart-c834522d-c6eb-4f8c-8dbf-ab30d15c2ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133962283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2133962283
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1535870073
Short name T170
Test name
Test status
Simulation time 5032863514 ps
CPU time 74.81 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:32:57 PM PDT 24
Peak memory 200784 kb
Host smart-8843b7f6-87ba-41cd-a10a-66395af1a4ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535870073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1535870073
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.720363790
Short name T141
Test name
Test status
Simulation time 2593248381 ps
CPU time 36.04 seconds
Started Aug 13 06:31:28 PM PDT 24
Finished Aug 13 06:32:04 PM PDT 24
Peak memory 200688 kb
Host smart-58e0b54f-e051-468b-9e0f-f91647957c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720363790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.720363790
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1372044011
Short name T194
Test name
Test status
Simulation time 3320345064 ps
CPU time 322.4 seconds
Started Aug 13 06:31:29 PM PDT 24
Finished Aug 13 06:36:51 PM PDT 24
Peak memory 687552 kb
Host smart-7e19e0d7-5296-4286-a8a8-7f11df7a9697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372044011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1372044011
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3809442634
Short name T365
Test name
Test status
Simulation time 1169557029 ps
CPU time 32.2 seconds
Started Aug 13 06:31:33 PM PDT 24
Finished Aug 13 06:32:05 PM PDT 24
Peak memory 200632 kb
Host smart-577dcbf0-5a5b-468e-a3f2-6649d56e4a44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809442634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3809442634
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3061052745
Short name T35
Test name
Test status
Simulation time 12232378040 ps
CPU time 158.32 seconds
Started Aug 13 06:31:36 PM PDT 24
Finished Aug 13 06:34:15 PM PDT 24
Peak memory 217160 kb
Host smart-b01d11a9-7f3f-409e-aa6d-8de25fc7015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061052745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3061052745
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1411523661
Short name T43
Test name
Test status
Simulation time 60309216 ps
CPU time 0.87 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:31:54 PM PDT 24
Peak memory 218920 kb
Host smart-ca714323-b3a1-48d1-862e-d9bf3bdaafc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411523661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1411523661
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1445260314
Short name T529
Test name
Test status
Simulation time 583763595 ps
CPU time 2.56 seconds
Started Aug 13 06:31:27 PM PDT 24
Finished Aug 13 06:31:30 PM PDT 24
Peak memory 200704 kb
Host smart-d2353cbe-eab4-4cfb-8d3f-7817349e724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445260314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1445260314
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2349414167
Short name T260
Test name
Test status
Simulation time 128202445659 ps
CPU time 507.57 seconds
Started Aug 13 06:31:33 PM PDT 24
Finished Aug 13 06:40:01 PM PDT 24
Peak memory 200712 kb
Host smart-66f12292-44d2-44d6-80f8-05bb8e5e8153
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349414167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2349414167
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1912440802
Short name T191
Test name
Test status
Simulation time 19558690076 ps
CPU time 74.09 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 200812 kb
Host smart-102eb64c-6b7f-49aa-99ff-ed8e56570959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1912440802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1912440802
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.334615008
Short name T149
Test name
Test status
Simulation time 15522280222 ps
CPU time 53.95 seconds
Started Aug 13 06:31:41 PM PDT 24
Finished Aug 13 06:32:35 PM PDT 24
Peak memory 200760 kb
Host smart-903b68e3-8d63-447c-b198-5c6aa3e7d05b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=334615008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.334615008
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.420456791
Short name T500
Test name
Test status
Simulation time 2921808030 ps
CPU time 103.76 seconds
Started Aug 13 06:31:44 PM PDT 24
Finished Aug 13 06:33:28 PM PDT 24
Peak memory 200732 kb
Host smart-6c83e61b-7a5d-4fa0-a7f1-4669294a3783
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=420456791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.420456791
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.92871465
Short name T452
Test name
Test status
Simulation time 88509152412 ps
CPU time 636.26 seconds
Started Aug 13 06:31:36 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 200632 kb
Host smart-1a7fe87b-7b2a-4996-8c69-b71318642694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=92871465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.92871465
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3303549598
Short name T76
Test name
Test status
Simulation time 309285899776 ps
CPU time 2869.49 seconds
Started Aug 13 06:31:39 PM PDT 24
Finished Aug 13 07:19:29 PM PDT 24
Peak memory 216076 kb
Host smart-07a460d6-6ebb-4699-8093-b9b0b21f44d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3303549598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3303549598
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3208500235
Short name T186
Test name
Test status
Simulation time 60373532097 ps
CPU time 2183.81 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 07:08:26 PM PDT 24
Peak memory 215616 kb
Host smart-d8709926-e7e0-4138-aa4f-75be6f2fca85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3208500235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3208500235
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1461748636
Short name T293
Test name
Test status
Simulation time 7159131423 ps
CPU time 126.78 seconds
Started Aug 13 06:31:28 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 200684 kb
Host smart-0231d3b7-d70e-4781-8a4e-fc8cf277d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461748636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1461748636
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1965053217
Short name T337
Test name
Test status
Simulation time 14254950 ps
CPU time 0.59 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:31:57 PM PDT 24
Peak memory 195716 kb
Host smart-8d382508-3da0-411f-a7d7-1a183633cdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965053217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1965053217
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2938991363
Short name T158
Test name
Test status
Simulation time 653703130 ps
CPU time 9.04 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:31:52 PM PDT 24
Peak memory 200628 kb
Host smart-606af3d0-f041-4985-a254-ad12b755a3c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938991363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2938991363
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1966621121
Short name T473
Test name
Test status
Simulation time 4999815883 ps
CPU time 32.42 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:32:35 PM PDT 24
Peak memory 200800 kb
Host smart-aebacb40-d5b2-42d9-9d78-8fd48e7ce885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966621121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1966621121
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1724394777
Short name T264
Test name
Test status
Simulation time 12100256662 ps
CPU time 707.24 seconds
Started Aug 13 06:32:03 PM PDT 24
Finished Aug 13 06:43:51 PM PDT 24
Peak memory 735168 kb
Host smart-33f12ca1-ca6d-4237-9cd5-9a0d9ac953f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724394777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1724394777
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2434122787
Short name T512
Test name
Test status
Simulation time 41738777033 ps
CPU time 135.05 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 200720 kb
Host smart-1ad4f983-46fa-4ef2-b7a4-55e5d6b2a6ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434122787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2434122787
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1187435689
Short name T29
Test name
Test status
Simulation time 10010141121 ps
CPU time 177.83 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:34:55 PM PDT 24
Peak memory 208992 kb
Host smart-28644558-3711-45a3-b447-16357b5a19a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187435689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1187435689
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1029252825
Short name T476
Test name
Test status
Simulation time 675795108 ps
CPU time 12.4 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:32:24 PM PDT 24
Peak memory 200684 kb
Host smart-46aa69a8-e207-4223-b58d-a430c6711bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029252825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1029252825
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1477143943
Short name T458
Test name
Test status
Simulation time 142741442777 ps
CPU time 2422.97 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 07:12:31 PM PDT 24
Peak memory 750748 kb
Host smart-2fcac4c2-7194-45c6-b060-f5f7bd5f459f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477143943 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1477143943
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1976785690
Short name T507
Test name
Test status
Simulation time 13595141079 ps
CPU time 69.92 seconds
Started Aug 13 06:32:03 PM PDT 24
Finished Aug 13 06:33:13 PM PDT 24
Peak memory 200752 kb
Host smart-eec51736-014d-4fb4-ba31-7ec4b4e31f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976785690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1976785690
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3658824279
Short name T253
Test name
Test status
Simulation time 30859215 ps
CPU time 0.56 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:31:59 PM PDT 24
Peak memory 196428 kb
Host smart-523d0477-d344-4b78-b10f-7efb821a67c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658824279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3658824279
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.997481606
Short name T508
Test name
Test status
Simulation time 2858389199 ps
CPU time 39.98 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:32:45 PM PDT 24
Peak memory 200640 kb
Host smart-9659c712-0ac6-4d36-98e1-99c1a3db0b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997481606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.997481606
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.652624720
Short name T460
Test name
Test status
Simulation time 7226767108 ps
CPU time 22.96 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:32:28 PM PDT 24
Peak memory 200748 kb
Host smart-1b0bc9ff-65c8-4f3a-b78c-3d08e4e0120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652624720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.652624720
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.38375095
Short name T376
Test name
Test status
Simulation time 11009995357 ps
CPU time 501.88 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:40:22 PM PDT 24
Peak memory 700860 kb
Host smart-7d200fb9-ca93-48fa-a044-9d2cb814ff83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38375095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.38375095
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2405018573
Short name T248
Test name
Test status
Simulation time 3502716962 ps
CPU time 190.7 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:35:16 PM PDT 24
Peak memory 200680 kb
Host smart-1da9d6cd-f721-4cb5-acb2-bf4964e34660
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405018573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2405018573
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1032091752
Short name T509
Test name
Test status
Simulation time 27312574457 ps
CPU time 120.34 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:33:56 PM PDT 24
Peak memory 209044 kb
Host smart-fd69ed4e-0ad0-4920-8748-0eff21d82451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032091752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1032091752
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3552548951
Short name T289
Test name
Test status
Simulation time 665782768 ps
CPU time 3.06 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:31:58 PM PDT 24
Peak memory 200684 kb
Host smart-2275a847-3dc2-40d4-9d65-f0e69e167003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552548951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3552548951
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2672359581
Short name T18
Test name
Test status
Simulation time 59438035151 ps
CPU time 2516.35 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 07:14:10 PM PDT 24
Peak memory 774268 kb
Host smart-06ea3426-c1fb-43de-8d42-d81f16b96409
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672359581 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2672359581
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.380379344
Short name T361
Test name
Test status
Simulation time 927200828 ps
CPU time 24.06 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:32:29 PM PDT 24
Peak memory 200760 kb
Host smart-e6a8116a-4c81-49d9-b990-5ce703bde1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380379344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.380379344
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.855306593
Short name T426
Test name
Test status
Simulation time 14299626 ps
CPU time 0.59 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:32:01 PM PDT 24
Peak memory 196764 kb
Host smart-18573709-34ed-41f4-babe-c4a6f466f091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855306593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.855306593
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2185774493
Short name T422
Test name
Test status
Simulation time 2932171867 ps
CPU time 13.48 seconds
Started Aug 13 06:31:59 PM PDT 24
Finished Aug 13 06:32:13 PM PDT 24
Peak memory 200712 kb
Host smart-f47489e9-13ed-41b4-bf04-2f8587f7ea8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185774493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2185774493
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.974410359
Short name T357
Test name
Test status
Simulation time 469793325 ps
CPU time 5.43 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:32:07 PM PDT 24
Peak memory 200716 kb
Host smart-c619f3fd-78a8-4d65-8d51-9dd50bf41b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974410359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.974410359
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2922329717
Short name T241
Test name
Test status
Simulation time 13822877987 ps
CPU time 571.6 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:41:40 PM PDT 24
Peak memory 609288 kb
Host smart-d756abb4-74ef-4b63-b3ec-7d710a97fa7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922329717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2922329717
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2760189538
Short name T175
Test name
Test status
Simulation time 3173608990 ps
CPU time 28.32 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:32:31 PM PDT 24
Peak memory 200756 kb
Host smart-4a07e9d2-21f5-4e7f-8f83-2c853f63af25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760189538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2760189538
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2152544363
Short name T369
Test name
Test status
Simulation time 3177699962 ps
CPU time 59.03 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:33:06 PM PDT 24
Peak memory 200828 kb
Host smart-a922b612-97df-4c2a-ace3-d27fa9fe6e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152544363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2152544363
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2130082793
Short name T249
Test name
Test status
Simulation time 2391592618 ps
CPU time 16.08 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:22 PM PDT 24
Peak memory 200700 kb
Host smart-a500902e-c081-406e-b41c-da2980a71306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130082793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2130082793
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1254930783
Short name T39
Test name
Test status
Simulation time 122904702219 ps
CPU time 2957.27 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 07:21:16 PM PDT 24
Peak memory 790156 kb
Host smart-2f45872f-423b-4f83-811b-377356d4a9a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254930783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1254930783
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3937211416
Short name T90
Test name
Test status
Simulation time 2066527706 ps
CPU time 96.36 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 200592 kb
Host smart-8f04a9b9-b72b-4ec3-895d-928d37a87500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937211416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3937211416
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1421914541
Short name T281
Test name
Test status
Simulation time 14764956 ps
CPU time 0.62 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:32:05 PM PDT 24
Peak memory 196748 kb
Host smart-5439cf2f-3d43-4fe6-a6ee-2e2c8b759398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421914541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1421914541
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1369942586
Short name T434
Test name
Test status
Simulation time 2150324092 ps
CPU time 31.33 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:39 PM PDT 24
Peak memory 200660 kb
Host smart-2274f276-a1c4-4be4-96a2-f96071db43a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369942586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1369942586
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.838205161
Short name T262
Test name
Test status
Simulation time 15543851469 ps
CPU time 49.47 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 200708 kb
Host smart-aa349ec1-a04a-4b14-8bf7-075b36bdb2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838205161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.838205161
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.405984913
Short name T393
Test name
Test status
Simulation time 8915050744 ps
CPU time 467.84 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:39:56 PM PDT 24
Peak memory 652652 kb
Host smart-2639e40f-794e-4429-a5fc-fb7982625e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405984913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.405984913
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1922499815
Short name T503
Test name
Test status
Simulation time 26321436039 ps
CPU time 83.8 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 200676 kb
Host smart-e0b69902-6580-4379-bed9-277109e8a859
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922499815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1922499815
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.479847630
Short name T436
Test name
Test status
Simulation time 13949165173 ps
CPU time 87.47 seconds
Started Aug 13 06:32:01 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 200692 kb
Host smart-ced45252-4af6-4113-a5a4-c4f9043040f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479847630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.479847630
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4244658307
Short name T487
Test name
Test status
Simulation time 1780475618 ps
CPU time 4.21 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:32:06 PM PDT 24
Peak memory 200644 kb
Host smart-5fe5a043-fb9a-47fb-a342-6191ada4f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244658307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4244658307
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.130106832
Short name T22
Test name
Test status
Simulation time 35213871734 ps
CPU time 47.49 seconds
Started Aug 13 06:32:03 PM PDT 24
Finished Aug 13 06:32:51 PM PDT 24
Peak memory 200772 kb
Host smart-f53c1e73-5a9b-4ecc-ab41-e5a7b9b00cfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130106832 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.130106832
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.775789226
Short name T449
Test name
Test status
Simulation time 791355902 ps
CPU time 10.87 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:17 PM PDT 24
Peak memory 200536 kb
Host smart-cf59c3b9-65cf-475c-863f-5a6d0e63ffa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775789226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.775789226
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2739802571
Short name T168
Test name
Test status
Simulation time 14670038 ps
CPU time 0.63 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:08 PM PDT 24
Peak memory 195712 kb
Host smart-e9bf1401-244f-4a4b-b334-22d8d69d8423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739802571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2739802571
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2788063159
Short name T182
Test name
Test status
Simulation time 1265361093 ps
CPU time 14.81 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:21 PM PDT 24
Peak memory 200756 kb
Host smart-e64c09d5-5146-4dec-ac92-5c9f8405c251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788063159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2788063159
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1055926569
Short name T475
Test name
Test status
Simulation time 158648871 ps
CPU time 2.5 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:32:13 PM PDT 24
Peak memory 200580 kb
Host smart-c0b570c6-e16d-450f-a2e0-d362ef655e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055926569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1055926569
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3645852900
Short name T221
Test name
Test status
Simulation time 1852555774 ps
CPU time 109.41 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:33:46 PM PDT 24
Peak memory 469684 kb
Host smart-acb6893b-e6b1-4d3e-acfe-ba2d165c4a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645852900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3645852900
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.567746859
Short name T189
Test name
Test status
Simulation time 25639591470 ps
CPU time 190.12 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:35:07 PM PDT 24
Peak memory 200768 kb
Host smart-ad25934d-2785-4aa5-818d-d329efb49217
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567746859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.567746859
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2851196919
Short name T151
Test name
Test status
Simulation time 10682564452 ps
CPU time 102.06 seconds
Started Aug 13 06:32:11 PM PDT 24
Finished Aug 13 06:33:53 PM PDT 24
Peak memory 200704 kb
Host smart-6006ff75-d8f3-4941-9202-6304a345e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851196919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2851196919
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3343133883
Short name T273
Test name
Test status
Simulation time 3765831493 ps
CPU time 12.55 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:18 PM PDT 24
Peak memory 200708 kb
Host smart-8ed87580-79e9-4157-87dd-394c591a7d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343133883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3343133883
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.562798571
Short name T429
Test name
Test status
Simulation time 140987298511 ps
CPU time 455.64 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:39:33 PM PDT 24
Peak memory 209012 kb
Host smart-00327b99-5737-4b19-9e5a-f0cc4fe67655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562798571 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.562798571
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3244298506
Short name T533
Test name
Test status
Simulation time 940886431 ps
CPU time 50.21 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:33:07 PM PDT 24
Peak memory 200676 kb
Host smart-096d350d-9256-40af-8c0b-9ed92662fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244298506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3244298506
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.903938924
Short name T492
Test name
Test status
Simulation time 12294102 ps
CPU time 0.58 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:07 PM PDT 24
Peak memory 196400 kb
Host smart-a6b4e7dc-f45c-493c-80d8-e0070404bb65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903938924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.903938924
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1479158009
Short name T444
Test name
Test status
Simulation time 91228386 ps
CPU time 4.81 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:20 PM PDT 24
Peak memory 200704 kb
Host smart-750de0d6-e300-429c-bfa9-d5859f7e5fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479158009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1479158009
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.838994618
Short name T431
Test name
Test status
Simulation time 7006029868 ps
CPU time 64.26 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 06:33:07 PM PDT 24
Peak memory 200780 kb
Host smart-3dbec4b7-63d3-415c-8b56-6725a6b41f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838994618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.838994618
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3600969570
Short name T173
Test name
Test status
Simulation time 1541634387 ps
CPU time 145.38 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:34:26 PM PDT 24
Peak memory 405872 kb
Host smart-b2a544ac-9169-488d-b152-4858f413c684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600969570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3600969570
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2344976224
Short name T382
Test name
Test status
Simulation time 159339593 ps
CPU time 1.54 seconds
Started Aug 13 06:32:11 PM PDT 24
Finished Aug 13 06:32:12 PM PDT 24
Peak memory 200568 kb
Host smart-9bc6a6dd-a631-4699-aa7f-05872f89c542
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344976224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2344976224
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3872154042
Short name T331
Test name
Test status
Simulation time 2241860346 ps
CPU time 10.88 seconds
Started Aug 13 06:32:00 PM PDT 24
Finished Aug 13 06:32:11 PM PDT 24
Peak memory 200776 kb
Host smart-52f695db-3747-43e8-917c-63acb010fbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872154042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3872154042
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1709259939
Short name T267
Test name
Test status
Simulation time 1273763512 ps
CPU time 6.49 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:32:12 PM PDT 24
Peak memory 200588 kb
Host smart-4540917f-786c-4f28-ac24-9429458bb64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709259939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1709259939
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3001604289
Short name T135
Test name
Test status
Simulation time 333693823469 ps
CPU time 6966.94 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 08:28:24 PM PDT 24
Peak memory 896332 kb
Host smart-428fdbcc-921c-4aae-aa6c-f3dd3ac47705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001604289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3001604289
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1910848553
Short name T201
Test name
Test status
Simulation time 10590878243 ps
CPU time 13.27 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:32:18 PM PDT 24
Peak memory 200724 kb
Host smart-cbac9c62-d454-4769-a500-d540a45b5b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910848553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1910848553
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.289245166
Short name T338
Test name
Test status
Simulation time 46481874 ps
CPU time 0.57 seconds
Started Aug 13 06:32:13 PM PDT 24
Finished Aug 13 06:32:14 PM PDT 24
Peak memory 196736 kb
Host smart-21536f50-a1f0-4617-9122-a51186347749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289245166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.289245166
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.341131739
Short name T10
Test name
Test status
Simulation time 2585920686 ps
CPU time 75.93 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 200812 kb
Host smart-3c47f932-93cf-47dc-9fa3-82d46eaa7ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341131739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.341131739
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2641795841
Short name T466
Test name
Test status
Simulation time 1649355641 ps
CPU time 5.64 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:12 PM PDT 24
Peak memory 200712 kb
Host smart-d7ae76bd-11d4-4954-aeb1-543404ee2e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641795841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2641795841
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1667701167
Short name T89
Test name
Test status
Simulation time 42509596697 ps
CPU time 540.28 seconds
Started Aug 13 06:32:11 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 668988 kb
Host smart-ab2739a4-ff73-4778-a6fc-9850e2f37139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667701167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1667701167
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4165192882
Short name T270
Test name
Test status
Simulation time 15319832706 ps
CPU time 132.72 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 200828 kb
Host smart-2b2a21b7-d768-46d5-b042-edf862bf066e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165192882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4165192882
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.621189399
Short name T527
Test name
Test status
Simulation time 15887194485 ps
CPU time 50.44 seconds
Started Aug 13 06:32:11 PM PDT 24
Finished Aug 13 06:33:01 PM PDT 24
Peak memory 200816 kb
Host smart-d851ff3d-b324-440b-b0e2-0bbb96042d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621189399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.621189399
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2293878059
Short name T132
Test name
Test status
Simulation time 949363708 ps
CPU time 15.29 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:21 PM PDT 24
Peak memory 200656 kb
Host smart-c7b041c7-80c9-4446-99ea-7d8a109c3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293878059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2293878059
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2497016606
Short name T53
Test name
Test status
Simulation time 4785087613 ps
CPU time 20.02 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:35 PM PDT 24
Peak memory 200788 kb
Host smart-15d80bad-5578-42d6-acef-9b8595804064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497016606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2497016606
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.324958216
Short name T329
Test name
Test status
Simulation time 57510516 ps
CPU time 0.57 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:31:58 PM PDT 24
Peak memory 195736 kb
Host smart-8d509dcb-0a95-4b5c-a44d-fe54c5b2f115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324958216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.324958216
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3365535470
Short name T176
Test name
Test status
Simulation time 1151781151 ps
CPU time 12.39 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:20 PM PDT 24
Peak memory 200632 kb
Host smart-c3242c03-b53d-493e-9dc3-f1f80eaa252c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365535470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3365535470
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.338634145
Short name T165
Test name
Test status
Simulation time 13934203670 ps
CPU time 43.91 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:32:48 PM PDT 24
Peak memory 208948 kb
Host smart-91886a3f-ecd9-4141-b70c-9824832f8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338634145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.338634145
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2981531981
Short name T490
Test name
Test status
Simulation time 24341084980 ps
CPU time 1097.97 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:50:27 PM PDT 24
Peak memory 692568 kb
Host smart-4ac8245c-0d4a-4d51-bb45-b01e74d7da11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981531981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2981531981
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.290106378
Short name T316
Test name
Test status
Simulation time 23966100688 ps
CPU time 100.07 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 200760 kb
Host smart-333413c7-187d-4ac1-a494-0222f54f19ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290106378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.290106378
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.88462976
Short name T309
Test name
Test status
Simulation time 11128763621 ps
CPU time 69.77 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:33:27 PM PDT 24
Peak memory 200736 kb
Host smart-8475e999-5ef4-4504-84f9-de30ee0fb9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88462976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.88462976
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.109148117
Short name T77
Test name
Test status
Simulation time 572765159 ps
CPU time 3.92 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:32:08 PM PDT 24
Peak memory 200724 kb
Host smart-2d4efaab-f7f2-4afb-a154-90eb5f970e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109148117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.109148117
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.4012703317
Short name T24
Test name
Test status
Simulation time 9667688133 ps
CPU time 1077.32 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:50:06 PM PDT 24
Peak memory 734620 kb
Host smart-188c292a-1529-4c88-8fc5-1fe5cfafbe53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012703317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.4012703317
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.662346669
Short name T370
Test name
Test status
Simulation time 903396505 ps
CPU time 14.99 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:32:11 PM PDT 24
Peak memory 200644 kb
Host smart-df1ecc77-979f-4b84-bd96-fb176d2d3ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662346669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.662346669
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3602966762
Short name T502
Test name
Test status
Simulation time 10611153 ps
CPU time 0.58 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:32:21 PM PDT 24
Peak memory 196412 kb
Host smart-fe50281b-1d3b-4b81-917e-714082204c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602966762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3602966762
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1095892566
Short name T433
Test name
Test status
Simulation time 6988353845 ps
CPU time 101.29 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 200756 kb
Host smart-3d62a04b-9059-4994-ab4d-f07454253e6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095892566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1095892566
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2923727912
Short name T513
Test name
Test status
Simulation time 685570778 ps
CPU time 38.94 seconds
Started Aug 13 06:32:13 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 200724 kb
Host smart-c42ed56f-2d88-4ec9-9eb5-1e6fc65e4d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923727912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2923727912
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3663973808
Short name T74
Test name
Test status
Simulation time 3181136244 ps
CPU time 122.68 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:34:07 PM PDT 24
Peak memory 451560 kb
Host smart-c460d1aa-c306-488f-9222-22688d1b78a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663973808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3663973808
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1153139061
Short name T28
Test name
Test status
Simulation time 73418391 ps
CPU time 0.64 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:32:07 PM PDT 24
Peak memory 197116 kb
Host smart-a0f68a63-f2a3-414e-a87b-e8e0b38135b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153139061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1153139061
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3285567640
Short name T213
Test name
Test status
Simulation time 7394242321 ps
CPU time 100.53 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 200672 kb
Host smart-fb0796dc-09da-43b6-b6c2-816f849358a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285567640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3285567640
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1942139659
Short name T427
Test name
Test status
Simulation time 1183918179 ps
CPU time 13.57 seconds
Started Aug 13 06:32:13 PM PDT 24
Finished Aug 13 06:32:27 PM PDT 24
Peak memory 200740 kb
Host smart-a8bad64f-39d4-46c5-8509-a816a21d9ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942139659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1942139659
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3968498295
Short name T220
Test name
Test status
Simulation time 20237733379 ps
CPU time 68.5 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 200720 kb
Host smart-9a32363b-90f9-4d0e-8efd-b1d62f0f24b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968498295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3968498295
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3353489074
Short name T420
Test name
Test status
Simulation time 39778721 ps
CPU time 0.6 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 196748 kb
Host smart-64173585-de21-400a-8701-79111c4c0183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353489074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3353489074
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.544083248
Short name T306
Test name
Test status
Simulation time 1119867840 ps
CPU time 63.89 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:33:12 PM PDT 24
Peak memory 200636 kb
Host smart-cd56af0e-1dd5-4eea-8fe3-63f5cf2d905a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544083248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.544083248
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.612952415
Short name T409
Test name
Test status
Simulation time 9558450489 ps
CPU time 20.91 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:36 PM PDT 24
Peak memory 208972 kb
Host smart-e1655e4b-3c1c-47b9-84f1-5f74be86826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612952415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.612952415
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1385523461
Short name T193
Test name
Test status
Simulation time 7875427643 ps
CPU time 324.9 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:37:42 PM PDT 24
Peak memory 602676 kb
Host smart-0ad766e3-ebad-4fa5-9eab-fd91ca3f1da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385523461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1385523461
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2487358901
Short name T407
Test name
Test status
Simulation time 43169611922 ps
CPU time 120.76 seconds
Started Aug 13 06:32:26 PM PDT 24
Finished Aug 13 06:34:27 PM PDT 24
Peak memory 200692 kb
Host smart-cdfcf279-977e-4ccb-a06f-909611619fc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487358901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2487358901
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3173556135
Short name T250
Test name
Test status
Simulation time 10304068616 ps
CPU time 193.52 seconds
Started Aug 13 06:32:33 PM PDT 24
Finished Aug 13 06:35:47 PM PDT 24
Peak memory 200716 kb
Host smart-3d663f1b-5c9d-4f09-bec7-b61c12206fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173556135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3173556135
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.839580175
Short name T163
Test name
Test status
Simulation time 1352752339 ps
CPU time 5.7 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:14 PM PDT 24
Peak memory 200668 kb
Host smart-3ee440a0-2c10-4059-8cb4-d1e1a279403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839580175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.839580175
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1598845524
Short name T36
Test name
Test status
Simulation time 32369752684 ps
CPU time 744.13 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:44:34 PM PDT 24
Peak memory 626552 kb
Host smart-a8e5a3ac-e85c-4024-9b03-9a8a40925e71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598845524 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1598845524
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3289246990
Short name T233
Test name
Test status
Simulation time 19590337353 ps
CPU time 99.86 seconds
Started Aug 13 06:32:14 PM PDT 24
Finished Aug 13 06:33:54 PM PDT 24
Peak memory 200720 kb
Host smart-ef3923a3-89f1-42b4-a95d-98e3245632f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289246990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3289246990
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.403511591
Short name T396
Test name
Test status
Simulation time 36594792 ps
CPU time 0.6 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:31:43 PM PDT 24
Peak memory 196764 kb
Host smart-5edff2ee-0a55-4bd4-974f-9c9197c4013c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403511591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.403511591
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3046077829
Short name T49
Test name
Test status
Simulation time 1042501755 ps
CPU time 22.65 seconds
Started Aug 13 06:31:33 PM PDT 24
Finished Aug 13 06:31:56 PM PDT 24
Peak memory 200676 kb
Host smart-358b203a-92c6-403a-ace1-7b6c3f45308b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046077829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3046077829
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1713770285
Short name T38
Test name
Test status
Simulation time 2523395719 ps
CPU time 31.74 seconds
Started Aug 13 06:31:37 PM PDT 24
Finished Aug 13 06:32:09 PM PDT 24
Peak memory 200740 kb
Host smart-0874c511-7dbf-474c-aa3c-e56f2a9870ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713770285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1713770285
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1251649617
Short name T219
Test name
Test status
Simulation time 1066214815 ps
CPU time 91.65 seconds
Started Aug 13 06:31:48 PM PDT 24
Finished Aug 13 06:33:20 PM PDT 24
Peak memory 457424 kb
Host smart-b48af505-128c-4314-8ab6-ade17049d26a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251649617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1251649617
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2964029090
Short name T51
Test name
Test status
Simulation time 8573475051 ps
CPU time 71.71 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:32:55 PM PDT 24
Peak memory 200748 kb
Host smart-789f8cb9-024b-4002-a282-4630140448c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964029090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2964029090
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3977722922
Short name T224
Test name
Test status
Simulation time 2380217653 ps
CPU time 24.98 seconds
Started Aug 13 06:31:45 PM PDT 24
Finished Aug 13 06:32:11 PM PDT 24
Peak memory 200768 kb
Host smart-f413c869-3b53-434f-a875-011a73d82cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977722922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3977722922
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1864455171
Short name T42
Test name
Test status
Simulation time 1261275589 ps
CPU time 0.96 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:31:43 PM PDT 24
Peak memory 220012 kb
Host smart-deb9c4db-56af-4fcf-8d31-ec409f82850a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864455171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1864455171
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.960539123
Short name T23
Test name
Test status
Simulation time 1204382745 ps
CPU time 14.97 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:32:08 PM PDT 24
Peak memory 200688 kb
Host smart-6bae1004-bcc0-4679-a026-36e91cab06da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960539123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.960539123
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1916966734
Short name T93
Test name
Test status
Simulation time 22283268581 ps
CPU time 1266.84 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:52:45 PM PDT 24
Peak memory 736072 kb
Host smart-f62f9972-a698-4da6-9e06-e1a2d83a6e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916966734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1916966734
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2728581697
Short name T58
Test name
Test status
Simulation time 2268773676 ps
CPU time 40.57 seconds
Started Aug 13 06:31:39 PM PDT 24
Finished Aug 13 06:32:20 PM PDT 24
Peak memory 209212 kb
Host smart-958f4a26-0184-40f8-8220-c61c0b8147ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728581697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2728581697
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1289112054
Short name T245
Test name
Test status
Simulation time 1185123821 ps
CPU time 40.96 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:32:32 PM PDT 24
Peak memory 200752 kb
Host smart-55dabccc-5c06-4d65-9cc5-60550e20ba0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1289112054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1289112054
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.55522765
Short name T27
Test name
Test status
Simulation time 4882111340 ps
CPU time 102.77 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:33:35 PM PDT 24
Peak memory 200756 kb
Host smart-39fb9d66-e244-4d73-9e5d-79abf6d3d714
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=55522765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.55522765
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3788459284
Short name T518
Test name
Test status
Simulation time 2396746096 ps
CPU time 69.92 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:33:02 PM PDT 24
Peak memory 200744 kb
Host smart-6c201e48-ff59-42d2-aca2-b5ab99d14195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3788459284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3788459284
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.4275920400
Short name T403
Test name
Test status
Simulation time 84846851722 ps
CPU time 573.74 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:41:26 PM PDT 24
Peak memory 200760 kb
Host smart-34cb7219-1b0e-4fae-a9be-1f1ef71f4698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4275920400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.4275920400
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2304234003
Short name T199
Test name
Test status
Simulation time 154476809165 ps
CPU time 1999.8 seconds
Started Aug 13 06:31:33 PM PDT 24
Finished Aug 13 07:04:53 PM PDT 24
Peak memory 200720 kb
Host smart-4324a3e8-7577-4653-9b11-e4240ae349d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2304234003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2304234003
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1091730914
Short name T50
Test name
Test status
Simulation time 150445080845 ps
CPU time 1940.29 seconds
Started Aug 13 06:31:50 PM PDT 24
Finished Aug 13 07:04:11 PM PDT 24
Peak memory 216176 kb
Host smart-e3e1d4a8-1205-4e9e-b0a2-0795a60221c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1091730914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1091730914
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2646302299
Short name T171
Test name
Test status
Simulation time 10363059789 ps
CPU time 133.02 seconds
Started Aug 13 06:31:46 PM PDT 24
Finished Aug 13 06:33:59 PM PDT 24
Peak memory 200784 kb
Host smart-3943956d-5d6b-491c-a2a3-677cf4a40483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646302299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2646302299
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1753766589
Short name T287
Test name
Test status
Simulation time 13975377 ps
CPU time 0.59 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:08 PM PDT 24
Peak memory 195740 kb
Host smart-d5b70bbd-10d9-4a23-ac51-48fe85b30813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753766589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1753766589
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1085783776
Short name T347
Test name
Test status
Simulation time 1202102130 ps
CPU time 71.53 seconds
Started Aug 13 06:32:21 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 200688 kb
Host smart-1f95b985-5062-4cad-b94b-35c1119c5de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085783776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1085783776
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2326065161
Short name T300
Test name
Test status
Simulation time 9115537582 ps
CPU time 78.43 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 200752 kb
Host smart-7a642486-13d0-4ca8-a3ee-cdbde5f01cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326065161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2326065161
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2052551535
Short name T166
Test name
Test status
Simulation time 32156043439 ps
CPU time 972.85 seconds
Started Aug 13 06:32:27 PM PDT 24
Finished Aug 13 06:48:40 PM PDT 24
Peak memory 748936 kb
Host smart-584796c0-ff97-4a19-a052-1e5a2ec872b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052551535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2052551535
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4247677853
Short name T155
Test name
Test status
Simulation time 10115404233 ps
CPU time 84.3 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:33:41 PM PDT 24
Peak memory 200764 kb
Host smart-1dabb809-536b-4b20-ba7e-20a366067478
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247677853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4247677853
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2267309019
Short name T160
Test name
Test status
Simulation time 17868873342 ps
CPU time 83.69 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:33:41 PM PDT 24
Peak memory 200720 kb
Host smart-69a01716-9220-4207-a57e-570e94c08f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267309019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2267309019
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2248402841
Short name T399
Test name
Test status
Simulation time 7103344203 ps
CPU time 9.59 seconds
Started Aug 13 06:32:26 PM PDT 24
Finished Aug 13 06:32:36 PM PDT 24
Peak memory 200752 kb
Host smart-0bc6ab90-f550-4343-8a16-a45d6bc0cb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248402841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2248402841
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1842701494
Short name T256
Test name
Test status
Simulation time 125366685886 ps
CPU time 4465.59 seconds
Started Aug 13 06:32:19 PM PDT 24
Finished Aug 13 07:46:45 PM PDT 24
Peak memory 875692 kb
Host smart-33ed3f34-b09e-4e3e-ae88-1d9e3bd7250f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842701494 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1842701494
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1419848393
Short name T179
Test name
Test status
Simulation time 10436174351 ps
CPU time 130.1 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 200632 kb
Host smart-da5dff69-efa7-42b3-9725-82291a8cae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419848393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1419848393
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.509980137
Short name T310
Test name
Test status
Simulation time 34963009 ps
CPU time 0.61 seconds
Started Aug 13 06:32:22 PM PDT 24
Finished Aug 13 06:32:23 PM PDT 24
Peak memory 196348 kb
Host smart-18ad1820-26e2-486e-8183-9b2b7db39ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509980137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.509980137
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.75850017
Short name T12
Test name
Test status
Simulation time 62551184 ps
CPU time 3.54 seconds
Started Aug 13 06:32:04 PM PDT 24
Finished Aug 13 06:32:08 PM PDT 24
Peak memory 200532 kb
Host smart-edc8f356-eace-476a-b47c-b77718e94392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75850017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.75850017
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3687762680
Short name T478
Test name
Test status
Simulation time 4500472933 ps
CPU time 16.63 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:32:33 PM PDT 24
Peak memory 200828 kb
Host smart-79b52ac8-4623-4b54-b74c-d5990af9f64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687762680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3687762680
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.685724741
Short name T246
Test name
Test status
Simulation time 6703511065 ps
CPU time 1169.15 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:51:45 PM PDT 24
Peak memory 755116 kb
Host smart-9e5ded9a-e1b8-4e86-a797-e81f66c91abf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685724741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.685724741
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2989374926
Short name T279
Test name
Test status
Simulation time 499685577 ps
CPU time 28.66 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:36 PM PDT 24
Peak memory 200528 kb
Host smart-731191ef-47e5-4fb7-bd50-9db6caa98031
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989374926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2989374926
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1756536004
Short name T207
Test name
Test status
Simulation time 3786517525 ps
CPU time 18.05 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:33 PM PDT 24
Peak memory 200776 kb
Host smart-a4a95b1a-6a66-4ee6-8920-766782a30db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756536004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1756536004
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3282791239
Short name T212
Test name
Test status
Simulation time 3009305200 ps
CPU time 8.86 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:32:24 PM PDT 24
Peak memory 200768 kb
Host smart-474b74c8-239f-474e-b62b-ed51322a76f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282791239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3282791239
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4107561253
Short name T299
Test name
Test status
Simulation time 132821812387 ps
CPU time 1146.92 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:51:30 PM PDT 24
Peak memory 671604 kb
Host smart-56a3686b-f240-495b-b157-8727d6ef46d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107561253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4107561253
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2338578420
Short name T91
Test name
Test status
Simulation time 5746247709 ps
CPU time 74.07 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:33:21 PM PDT 24
Peak memory 200744 kb
Host smart-8b85fe88-e4af-4a81-9fc4-b5d256994d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338578420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2338578420
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.658494477
Short name T181
Test name
Test status
Simulation time 156104443 ps
CPU time 0.54 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:32:08 PM PDT 24
Peak memory 196392 kb
Host smart-8a32638e-1704-4ff6-9a99-a999f3dc4cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658494477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.658494477
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1793311417
Short name T225
Test name
Test status
Simulation time 2155923772 ps
CPU time 17.38 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:26 PM PDT 24
Peak memory 200600 kb
Host smart-0146cdd5-8c94-4bdb-b7c2-2e24cd0ead1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793311417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1793311417
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3904773068
Short name T419
Test name
Test status
Simulation time 337228624 ps
CPU time 18.06 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:32:30 PM PDT 24
Peak memory 200656 kb
Host smart-49014e72-6ca6-4d59-97b6-deaa56769086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904773068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3904773068
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.567382441
Short name T205
Test name
Test status
Simulation time 5299665089 ps
CPU time 884.76 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:46:55 PM PDT 24
Peak memory 744960 kb
Host smart-52d7acd6-00dc-484b-90d0-e02c9b713cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567382441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.567382441
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2913389255
Short name T497
Test name
Test status
Simulation time 12943137340 ps
CPU time 223.11 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:35:55 PM PDT 24
Peak memory 200812 kb
Host smart-d0fe8e54-0ac2-4328-9d0f-5b1b9b1f1141
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913389255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2913389255
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.343609113
Short name T395
Test name
Test status
Simulation time 4427608635 ps
CPU time 77.64 seconds
Started Aug 13 06:32:24 PM PDT 24
Finished Aug 13 06:33:42 PM PDT 24
Peak memory 200756 kb
Host smart-a43ea107-cdd4-4b38-b529-44fc1e6b7cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343609113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.343609113
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2960103057
Short name T187
Test name
Test status
Simulation time 797109436 ps
CPU time 9.91 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:25 PM PDT 24
Peak memory 200684 kb
Host smart-9e1789f2-7bef-479b-9c4c-7927f367c068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960103057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2960103057
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1693332325
Short name T280
Test name
Test status
Simulation time 53160693396 ps
CPU time 972.02 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:48:20 PM PDT 24
Peak memory 200764 kb
Host smart-4d6f2f2e-e723-44ac-8fe9-792c5d98ac0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693332325 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1693332325
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3244866689
Short name T468
Test name
Test status
Simulation time 6081028592 ps
CPU time 29.4 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:37 PM PDT 24
Peak memory 200756 kb
Host smart-f2aca6d5-4608-4193-bcf3-4674294a47d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244866689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3244866689
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3829688762
Short name T437
Test name
Test status
Simulation time 18692384 ps
CPU time 0.6 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:32:10 PM PDT 24
Peak memory 196380 kb
Host smart-041bfb55-0a89-49d2-b89d-aa90a053b81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829688762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3829688762
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3781178952
Short name T445
Test name
Test status
Simulation time 6733552847 ps
CPU time 92.92 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:33:39 PM PDT 24
Peak memory 216196 kb
Host smart-ed900a73-20fd-48f4-adb6-584d44744c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781178952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3781178952
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3468138081
Short name T379
Test name
Test status
Simulation time 8081907615 ps
CPU time 59.98 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:33:17 PM PDT 24
Peak memory 200772 kb
Host smart-8fcf5f5f-2e0a-45f3-95df-73566084a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468138081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3468138081
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1787311643
Short name T231
Test name
Test status
Simulation time 16505305905 ps
CPU time 621.58 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:42:42 PM PDT 24
Peak memory 648724 kb
Host smart-b72f79cf-b44b-44e1-9cf6-d2fabc4f1d32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787311643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1787311643
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1504538516
Short name T392
Test name
Test status
Simulation time 6206646734 ps
CPU time 103.8 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:33:50 PM PDT 24
Peak memory 200756 kb
Host smart-0636e0e1-1d50-4f49-8b88-8b83d9d855ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504538516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1504538516
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3444760605
Short name T355
Test name
Test status
Simulation time 483481567 ps
CPU time 27.82 seconds
Started Aug 13 06:32:13 PM PDT 24
Finished Aug 13 06:32:40 PM PDT 24
Peak memory 200700 kb
Host smart-058682d7-7c19-4ad3-9e73-fef78e5cea16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444760605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3444760605
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3180887497
Short name T255
Test name
Test status
Simulation time 1418993707 ps
CPU time 17.03 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:32 PM PDT 24
Peak memory 200764 kb
Host smart-6c32e549-ea86-4e2c-9bfd-2083741c69a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180887497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3180887497
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.56606599
Short name T275
Test name
Test status
Simulation time 40237080993 ps
CPU time 128.82 seconds
Started Aug 13 06:32:05 PM PDT 24
Finished Aug 13 06:34:14 PM PDT 24
Peak memory 200760 kb
Host smart-7523cc9c-807f-46c0-8ff3-3263b6be4adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56606599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.56606599
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2904783434
Short name T87
Test name
Test status
Simulation time 13370534 ps
CPU time 0.59 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 196772 kb
Host smart-3868c6f8-6902-4f3d-817c-06e67eb0e8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904783434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2904783434
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1479206277
Short name T218
Test name
Test status
Simulation time 3427394014 ps
CPU time 100.82 seconds
Started Aug 13 06:32:38 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 200808 kb
Host smart-8a28481a-1678-4af8-968d-a17ea5e93845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479206277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1479206277
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3409764683
Short name T258
Test name
Test status
Simulation time 4868808334 ps
CPU time 273.01 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:36:40 PM PDT 24
Peak memory 649416 kb
Host smart-7ce6369f-66cc-4eab-be55-8c3ac565fc8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409764683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3409764683
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3839104089
Short name T424
Test name
Test status
Simulation time 1398002545 ps
CPU time 71.08 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:33:27 PM PDT 24
Peak memory 200672 kb
Host smart-f1f32403-5fd6-4ce6-86b4-cb6ebf135455
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839104089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3839104089
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.260604972
Short name T297
Test name
Test status
Simulation time 16552055190 ps
CPU time 170.31 seconds
Started Aug 13 06:32:07 PM PDT 24
Finished Aug 13 06:34:58 PM PDT 24
Peak memory 200776 kb
Host smart-392342d5-38f3-4e3a-91cb-e7c04e537853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260604972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.260604972
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3170601700
Short name T363
Test name
Test status
Simulation time 4010704433 ps
CPU time 11.7 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:20 PM PDT 24
Peak memory 200736 kb
Host smart-d4a751c4-1915-4b0d-8089-85cf396f5d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170601700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3170601700
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2844434978
Short name T81
Test name
Test status
Simulation time 35510800112 ps
CPU time 755.52 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:44:46 PM PDT 24
Peak memory 529648 kb
Host smart-b78f914d-51b6-423d-a768-1a9a654332bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844434978 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2844434978
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3836915076
Short name T254
Test name
Test status
Simulation time 7149111522 ps
CPU time 82.54 seconds
Started Aug 13 06:32:21 PM PDT 24
Finished Aug 13 06:33:43 PM PDT 24
Peak memory 200752 kb
Host smart-3fd82ba9-61c1-4a58-b8e0-4923d1639bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836915076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3836915076
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.292813465
Short name T296
Test name
Test status
Simulation time 11904590 ps
CPU time 0.53 seconds
Started Aug 13 06:33:09 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 195256 kb
Host smart-480f7cb9-a08d-4035-bc7e-39b382089e49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292813465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.292813465
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3659614939
Short name T259
Test name
Test status
Simulation time 3311676918 ps
CPU time 49.13 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:33:05 PM PDT 24
Peak memory 200776 kb
Host smart-8bfdb90f-029d-4d23-8086-cb35008d6a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659614939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3659614939
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3699666050
Short name T288
Test name
Test status
Simulation time 723302551 ps
CPU time 10.17 seconds
Started Aug 13 06:32:18 PM PDT 24
Finished Aug 13 06:32:29 PM PDT 24
Peak memory 200656 kb
Host smart-df4ebca8-cc76-4c3a-b6c0-1f51a2e3fb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699666050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3699666050
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1541905820
Short name T197
Test name
Test status
Simulation time 8151226077 ps
CPU time 510.82 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:40:51 PM PDT 24
Peak memory 488968 kb
Host smart-adb27f25-fabd-467e-aec8-cf4b18ef89e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541905820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1541905820
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2323272487
Short name T185
Test name
Test status
Simulation time 2988940940 ps
CPU time 17.73 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:32:27 PM PDT 24
Peak memory 200720 kb
Host smart-b39e2bb1-458f-4a61-b12c-7a6d2afbd6fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323272487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2323272487
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3336430468
Short name T137
Test name
Test status
Simulation time 29917796899 ps
CPU time 137.9 seconds
Started Aug 13 06:32:38 PM PDT 24
Finished Aug 13 06:34:56 PM PDT 24
Peak memory 200904 kb
Host smart-dab9771d-51fe-4978-8595-f9c14773c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336430468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3336430468
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2337793219
Short name T479
Test name
Test status
Simulation time 5147329526 ps
CPU time 16.47 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:32:34 PM PDT 24
Peak memory 200760 kb
Host smart-3dd36560-d4e6-443f-a508-a336400b9a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337793219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2337793219
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2941828702
Short name T388
Test name
Test status
Simulation time 46753848971 ps
CPU time 674.42 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 662680 kb
Host smart-8ce73172-6f21-4598-90aa-2821b6df8d2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941828702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2941828702
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4262618023
Short name T85
Test name
Test status
Simulation time 1812612667 ps
CPU time 49.03 seconds
Started Aug 13 06:32:19 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 200676 kb
Host smart-860059be-1dcb-489e-bcd8-64785810673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262618023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4262618023
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4293462382
Short name T372
Test name
Test status
Simulation time 43415249 ps
CPU time 0.58 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:16 PM PDT 24
Peak memory 196740 kb
Host smart-55f3b5f9-728f-4da8-8295-0bbf23b57476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293462382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4293462382
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4277735479
Short name T269
Test name
Test status
Simulation time 6135643033 ps
CPU time 90.33 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:33:53 PM PDT 24
Peak memory 200768 kb
Host smart-daa17a0f-c382-47c3-8e71-9aed6d35b03b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277735479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4277735479
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1914978884
Short name T146
Test name
Test status
Simulation time 11983395623 ps
CPU time 76.08 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:33:24 PM PDT 24
Peak memory 208976 kb
Host smart-d8a625fa-8b33-471e-aa48-dfba46fa553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914978884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1914978884
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1660202312
Short name T385
Test name
Test status
Simulation time 560179623 ps
CPU time 90.54 seconds
Started Aug 13 06:32:18 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 473308 kb
Host smart-8b8011a5-e284-4ac3-b271-5b78cf32d9ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660202312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1660202312
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3212972257
Short name T2
Test name
Test status
Simulation time 1453022402 ps
CPU time 84.17 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 200700 kb
Host smart-49dd5b75-f6c3-4f5e-b9b3-08f17f19f44b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212972257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3212972257
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3913182615
Short name T446
Test name
Test status
Simulation time 8262264969 ps
CPU time 132.17 seconds
Started Aug 13 06:33:00 PM PDT 24
Finished Aug 13 06:35:13 PM PDT 24
Peak memory 199780 kb
Host smart-eac84834-b95e-4cc0-9ad8-c869880ec7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913182615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3913182615
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2761458061
Short name T408
Test name
Test status
Simulation time 839628750 ps
CPU time 7.12 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:32:19 PM PDT 24
Peak memory 200580 kb
Host smart-e2748726-bc1a-468d-b5b8-95ff8f49849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761458061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2761458061
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2444511106
Short name T465
Test name
Test status
Simulation time 29422411031 ps
CPU time 195.74 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 200744 kb
Host smart-774428aa-d0d0-46d8-b9f9-14a4a3dbfe17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444511106 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2444511106
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3672243016
Short name T353
Test name
Test status
Simulation time 14438651730 ps
CPU time 41 seconds
Started Aug 13 06:32:19 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 200752 kb
Host smart-e4ad20bc-47e9-413e-91a3-7be89d4fba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672243016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3672243016
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1106970930
Short name T217
Test name
Test status
Simulation time 516336287 ps
CPU time 31.51 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:46 PM PDT 24
Peak memory 200676 kb
Host smart-8c2e79ff-1bb2-4c80-9375-0955d82d4f30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106970930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1106970930
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.13429786
Short name T147
Test name
Test status
Simulation time 2036507598 ps
CPU time 29.87 seconds
Started Aug 13 06:32:14 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 200696 kb
Host smart-3bbdef46-b6bd-4e24-a29a-e2971c49cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13429786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.13429786
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2019987180
Short name T459
Test name
Test status
Simulation time 689438016 ps
CPU time 128.87 seconds
Started Aug 13 06:32:38 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 594544 kb
Host smart-055e497d-7f59-465c-9d43-57794a3973ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019987180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2019987180
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.741158846
Short name T198
Test name
Test status
Simulation time 2540164732 ps
CPU time 67.76 seconds
Started Aug 13 06:32:26 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 200700 kb
Host smart-3b5515fb-c7b9-4fdf-b8ac-8becb1311199
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741158846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.741158846
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2604996921
Short name T425
Test name
Test status
Simulation time 12507941187 ps
CPU time 101.94 seconds
Started Aug 13 06:32:37 PM PDT 24
Finished Aug 13 06:34:20 PM PDT 24
Peak memory 200764 kb
Host smart-4f2ede05-3747-4295-a65d-6405eb0b2850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604996921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2604996921
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3626581914
Short name T442
Test name
Test status
Simulation time 612867072 ps
CPU time 14.68 seconds
Started Aug 13 06:32:14 PM PDT 24
Finished Aug 13 06:32:29 PM PDT 24
Peak memory 200696 kb
Host smart-2936042b-e6fa-4469-94da-c8b1e097b20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626581914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3626581914
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.18860957
Short name T200
Test name
Test status
Simulation time 26892832126 ps
CPU time 540.01 seconds
Started Aug 13 06:32:29 PM PDT 24
Finished Aug 13 06:41:29 PM PDT 24
Peak memory 359328 kb
Host smart-18224d03-21a1-40b8-ac98-e794e6ab550d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860957 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.18860957
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1958104611
Short name T150
Test name
Test status
Simulation time 1326812893 ps
CPU time 6.52 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:32:30 PM PDT 24
Peak memory 200532 kb
Host smart-8c06ed11-f139-4943-83d0-8a4ff73f2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958104611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1958104611
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.497631896
Short name T161
Test name
Test status
Simulation time 16328791 ps
CPU time 0.62 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:32:20 PM PDT 24
Peak memory 196772 kb
Host smart-b23215d4-d6ba-4d12-a504-606984fd875c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497631896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.497631896
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1843222227
Short name T423
Test name
Test status
Simulation time 8046399055 ps
CPU time 84.44 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:33:33 PM PDT 24
Peak memory 208964 kb
Host smart-bce2702f-6f5c-4c67-bfd8-8f950d05b9ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843222227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1843222227
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.183042859
Short name T342
Test name
Test status
Simulation time 5089546772 ps
CPU time 66.89 seconds
Started Aug 13 06:32:06 PM PDT 24
Finished Aug 13 06:33:13 PM PDT 24
Peak memory 200720 kb
Host smart-f21ea6fe-e1e7-46d6-a96f-87cfe633e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183042859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.183042859
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.237705480
Short name T240
Test name
Test status
Simulation time 5818824180 ps
CPU time 240.19 seconds
Started Aug 13 06:32:18 PM PDT 24
Finished Aug 13 06:36:18 PM PDT 24
Peak memory 591656 kb
Host smart-466c2ee6-5da3-4bfe-91b0-411a79173143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237705480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.237705480
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3554667990
Short name T486
Test name
Test status
Simulation time 82444532 ps
CPU time 4.61 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:32:22 PM PDT 24
Peak memory 200632 kb
Host smart-6bac2eeb-a6f6-4d67-b255-733e314defad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554667990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3554667990
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.485625264
Short name T325
Test name
Test status
Simulation time 9594067809 ps
CPU time 104.19 seconds
Started Aug 13 06:32:25 PM PDT 24
Finished Aug 13 06:34:09 PM PDT 24
Peak memory 200756 kb
Host smart-7dcde691-b1d0-4a1d-87b3-2507f241c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485625264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.485625264
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3361449603
Short name T153
Test name
Test status
Simulation time 185460991 ps
CPU time 4.43 seconds
Started Aug 13 06:32:39 PM PDT 24
Finished Aug 13 06:32:43 PM PDT 24
Peak memory 200652 kb
Host smart-a403fee5-02ea-449c-b146-41f4ede504b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361449603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3361449603
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.680400374
Short name T64
Test name
Test status
Simulation time 44280841298 ps
CPU time 1159.77 seconds
Started Aug 13 06:32:18 PM PDT 24
Finished Aug 13 06:51:38 PM PDT 24
Peak memory 721744 kb
Host smart-b3731b4a-b72a-4bac-b123-6a6d43d882bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680400374 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.680400374
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4117846095
Short name T162
Test name
Test status
Simulation time 38980099422 ps
CPU time 121.52 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:34:17 PM PDT 24
Peak memory 200760 kb
Host smart-57cfe119-17be-43e1-b0e4-3a9e8956b12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117846095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4117846095
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2041456945
Short name T504
Test name
Test status
Simulation time 19641733 ps
CPU time 0.59 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:32:10 PM PDT 24
Peak memory 196424 kb
Host smart-97a70ea6-3572-4878-a562-8e2652be7106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041456945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2041456945
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2121512180
Short name T5
Test name
Test status
Simulation time 9966913064 ps
CPU time 45.81 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:33:02 PM PDT 24
Peak memory 200760 kb
Host smart-c274d8c7-351f-4104-a848-03614e970f0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121512180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2121512180
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1883951842
Short name T364
Test name
Test status
Simulation time 4186603897 ps
CPU time 27.74 seconds
Started Aug 13 06:32:18 PM PDT 24
Finished Aug 13 06:32:51 PM PDT 24
Peak memory 200768 kb
Host smart-e8a54a64-46b1-498d-ba1c-fdd05c5cff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883951842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1883951842
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.255890154
Short name T292
Test name
Test status
Simulation time 20011697052 ps
CPU time 587.93 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:41:57 PM PDT 24
Peak memory 636532 kb
Host smart-bb10ebc6-02b7-4d20-8006-f27e5d683b5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255890154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.255890154
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3668277548
Short name T244
Test name
Test status
Simulation time 9048965460 ps
CPU time 52.69 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:33:03 PM PDT 24
Peak memory 200768 kb
Host smart-43bf0697-a42f-4453-9004-cdf1be5e9bd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668277548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3668277548
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4262075946
Short name T227
Test name
Test status
Simulation time 2530270679 ps
CPU time 35.06 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 200764 kb
Host smart-3ab17bc9-86e9-456a-b469-691b97742f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262075946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4262075946
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2931252316
Short name T521
Test name
Test status
Simulation time 3907485389 ps
CPU time 5.49 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:32:28 PM PDT 24
Peak memory 200684 kb
Host smart-aee75026-ae24-4646-83e8-c969d27b9653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931252316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2931252316
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2285714179
Short name T443
Test name
Test status
Simulation time 81070996749 ps
CPU time 374.67 seconds
Started Aug 13 06:32:14 PM PDT 24
Finished Aug 13 06:38:29 PM PDT 24
Peak memory 442820 kb
Host smart-634e36f2-ce33-41dd-b67b-30546b3ac8f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285714179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2285714179
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3786518737
Short name T453
Test name
Test status
Simulation time 4270321072 ps
CPU time 71.55 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:33:20 PM PDT 24
Peak memory 200816 kb
Host smart-1f313b58-8716-427f-a5f1-02869e96b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786518737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3786518737
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3575319171
Short name T278
Test name
Test status
Simulation time 25831778 ps
CPU time 0.6 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:31:53 PM PDT 24
Peak memory 197460 kb
Host smart-aa965de9-bde3-4b37-8a12-cc4100f0102e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575319171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3575319171
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.855849771
Short name T180
Test name
Test status
Simulation time 1170995058 ps
CPU time 64.02 seconds
Started Aug 13 06:31:45 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 200656 kb
Host smart-f21843e7-e7e8-4fe2-8e55-e228ee38bcc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855849771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.855849771
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.4226192860
Short name T354
Test name
Test status
Simulation time 11624260774 ps
CPU time 42.37 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:32:38 PM PDT 24
Peak memory 216988 kb
Host smart-087dad5d-806d-4297-8cf3-3c4d3874044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226192860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4226192860
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1695566057
Short name T177
Test name
Test status
Simulation time 24890264687 ps
CPU time 520.59 seconds
Started Aug 13 06:31:45 PM PDT 24
Finished Aug 13 06:40:26 PM PDT 24
Peak memory 674040 kb
Host smart-ac559321-3afe-4028-8141-39868f59057c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695566057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1695566057
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2601762281
Short name T421
Test name
Test status
Simulation time 14479057874 ps
CPU time 169.28 seconds
Started Aug 13 06:31:47 PM PDT 24
Finished Aug 13 06:34:37 PM PDT 24
Peak memory 200752 kb
Host smart-0a98b767-13cf-49e3-9145-d267d6395382
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601762281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2601762281
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3488137388
Short name T525
Test name
Test status
Simulation time 42972247156 ps
CPU time 137.91 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:34:12 PM PDT 24
Peak memory 200772 kb
Host smart-a500c8e7-1fa9-404c-a586-ac4472bafab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488137388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3488137388
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1914559327
Short name T45
Test name
Test status
Simulation time 235627435 ps
CPU time 0.92 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:31:44 PM PDT 24
Peak memory 219052 kb
Host smart-e36cde25-c738-4b88-ad36-7d73377b1efc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914559327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1914559327
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1184768262
Short name T320
Test name
Test status
Simulation time 394416400 ps
CPU time 2.26 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:31:56 PM PDT 24
Peak memory 200604 kb
Host smart-79d27604-f9a7-4f01-9e8e-25b903599e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184768262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1184768262
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1222841461
Short name T40
Test name
Test status
Simulation time 31390410346 ps
CPU time 423.11 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:38:42 PM PDT 24
Peak memory 216996 kb
Host smart-e560ec18-29a1-4ed7-95ae-04eb57bc7dbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222841461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1222841461
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.3386239444
Short name T368
Test name
Test status
Simulation time 5845514059 ps
CPU time 72.16 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:32:55 PM PDT 24
Peak memory 200756 kb
Host smart-e031fabe-a8c2-4960-80c5-c62706ab4816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3386239444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3386239444
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2560326567
Short name T358
Test name
Test status
Simulation time 19468511886 ps
CPU time 69.99 seconds
Started Aug 13 06:31:35 PM PDT 24
Finished Aug 13 06:32:45 PM PDT 24
Peak memory 200712 kb
Host smart-0206b72d-440e-4715-a5a2-1afda0937542
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2560326567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2560326567
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1642452974
Short name T526
Test name
Test status
Simulation time 22518746013 ps
CPU time 127 seconds
Started Aug 13 06:31:38 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 200760 kb
Host smart-237eed57-5b1b-410a-952e-43e85b2a0477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1642452974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1642452974
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2923995032
Short name T237
Test name
Test status
Simulation time 21787066764 ps
CPU time 609.91 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:42:06 PM PDT 24
Peak memory 200740 kb
Host smart-af884fc1-94c9-47b9-9590-1b65e922d1ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2923995032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2923995032
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3400945779
Short name T516
Test name
Test status
Simulation time 135257155746 ps
CPU time 2390.53 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 07:11:44 PM PDT 24
Peak memory 216352 kb
Host smart-88abc02a-675e-4913-9fa0-57cdeb7209a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3400945779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3400945779
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2238468470
Short name T211
Test name
Test status
Simulation time 174623726206 ps
CPU time 2542.44 seconds
Started Aug 13 06:31:40 PM PDT 24
Finished Aug 13 07:14:04 PM PDT 24
Peak memory 216288 kb
Host smart-488e54dc-391c-4ca0-9686-1a312cb30cca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2238468470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2238468470
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3760075546
Short name T95
Test name
Test status
Simulation time 1717528015 ps
CPU time 91.12 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:33:27 PM PDT 24
Peak memory 200672 kb
Host smart-897ca386-df61-4e7e-a6be-920cb9254ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760075546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3760075546
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3130176926
Short name T265
Test name
Test status
Simulation time 72254281 ps
CPU time 0.64 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:32:13 PM PDT 24
Peak memory 197460 kb
Host smart-8065fb1d-bf8a-45c7-83b9-b287eda3ba3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130176926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3130176926
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1637051777
Short name T480
Test name
Test status
Simulation time 840180089 ps
CPU time 25.45 seconds
Started Aug 13 06:32:28 PM PDT 24
Finished Aug 13 06:32:54 PM PDT 24
Peak memory 200744 kb
Host smart-8981ee6f-c8f4-462a-91f4-fdefd91fc605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637051777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1637051777
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4158807800
Short name T282
Test name
Test status
Simulation time 3047040339 ps
CPU time 13.9 seconds
Started Aug 13 06:32:12 PM PDT 24
Finished Aug 13 06:32:26 PM PDT 24
Peak memory 200744 kb
Host smart-c6d4a446-81e5-43c2-bda4-c1f3724c6d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158807800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4158807800
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3116840827
Short name T235
Test name
Test status
Simulation time 16615539051 ps
CPU time 707.63 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:43:56 PM PDT 24
Peak memory 687200 kb
Host smart-b978d38d-636c-4a9d-8e28-34ca069dbf4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116840827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3116840827
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.506985273
Short name T178
Test name
Test status
Simulation time 7077486026 ps
CPU time 95.35 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:33:55 PM PDT 24
Peak memory 200780 kb
Host smart-eb04a7b9-5df1-4afe-b4aa-2abd4c107deb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506985273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.506985273
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2055063055
Short name T84
Test name
Test status
Simulation time 74901084 ps
CPU time 4.62 seconds
Started Aug 13 06:32:26 PM PDT 24
Finished Aug 13 06:32:31 PM PDT 24
Peak memory 200656 kb
Host smart-50231c74-9646-4413-9d54-d57cd72883e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055063055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2055063055
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2521339740
Short name T350
Test name
Test status
Simulation time 921153594 ps
CPU time 10.43 seconds
Started Aug 13 06:32:08 PM PDT 24
Finished Aug 13 06:32:19 PM PDT 24
Peak memory 200752 kb
Host smart-c5450491-f892-4f28-a963-509a12d23337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521339740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2521339740
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1249969275
Short name T485
Test name
Test status
Simulation time 8771092671 ps
CPU time 573.98 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:42:16 PM PDT 24
Peak memory 597784 kb
Host smart-3d66c409-0742-4d82-8654-74717ff06fe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249969275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1249969275
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.4026772320
Short name T359
Test name
Test status
Simulation time 6785818500 ps
CPU time 114.74 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 200768 kb
Host smart-c4fb2869-0534-47c7-9d8b-2fcadcd878e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026772320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.4026772320
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2906621318
Short name T332
Test name
Test status
Simulation time 12839662 ps
CPU time 0.62 seconds
Started Aug 13 06:32:37 PM PDT 24
Finished Aug 13 06:32:38 PM PDT 24
Peak memory 196332 kb
Host smart-be6d6285-4944-4038-ab93-255785690cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906621318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2906621318
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2937011153
Short name T428
Test name
Test status
Simulation time 891316559 ps
CPU time 53.51 seconds
Started Aug 13 06:32:11 PM PDT 24
Finished Aug 13 06:33:05 PM PDT 24
Peak memory 200696 kb
Host smart-09f2ea38-f5fc-4f62-8051-044ebb5aa061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937011153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2937011153
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3152736048
Short name T461
Test name
Test status
Simulation time 6431521162 ps
CPU time 42.12 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:33:02 PM PDT 24
Peak memory 217052 kb
Host smart-2565dbdf-a674-4858-aa20-45d80353b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152736048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3152736048
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2190215761
Short name T400
Test name
Test status
Simulation time 3577454814 ps
CPU time 618.02 seconds
Started Aug 13 06:32:17 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 522304 kb
Host smart-0bfe688d-80d5-48b5-bc80-31fac374f590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190215761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2190215761
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.154129706
Short name T511
Test name
Test status
Simulation time 6717225177 ps
CPU time 88.05 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:33:42 PM PDT 24
Peak memory 200692 kb
Host smart-3169ce8d-6c7c-4c36-9ce8-623d039b0a52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154129706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.154129706
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.758325007
Short name T230
Test name
Test status
Simulation time 11948109949 ps
CPU time 49.97 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:33:25 PM PDT 24
Peak memory 200964 kb
Host smart-823f46cf-5831-4461-8261-a41816132301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758325007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.758325007
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1283433821
Short name T515
Test name
Test status
Simulation time 509812904 ps
CPU time 4.92 seconds
Started Aug 13 06:32:19 PM PDT 24
Finished Aug 13 06:32:24 PM PDT 24
Peak memory 200656 kb
Host smart-0b6f780c-e1af-4726-af1a-57c877ed8d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283433821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1283433821
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1348436420
Short name T401
Test name
Test status
Simulation time 77915061177 ps
CPU time 1361.77 seconds
Started Aug 13 06:32:09 PM PDT 24
Finished Aug 13 06:54:51 PM PDT 24
Peak memory 698756 kb
Host smart-665b135c-c58f-4ee8-b09f-60254db2dba8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348436420 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1348436420
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3640770936
Short name T118
Test name
Test status
Simulation time 8855656048 ps
CPU time 128.66 seconds
Started Aug 13 06:32:10 PM PDT 24
Finished Aug 13 06:34:19 PM PDT 24
Peak memory 200720 kb
Host smart-9391fe1e-df3a-47d3-8c8f-049100abd49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640770936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3640770936
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2142056908
Short name T312
Test name
Test status
Simulation time 21333876 ps
CPU time 0.58 seconds
Started Aug 13 06:32:24 PM PDT 24
Finished Aug 13 06:32:25 PM PDT 24
Peak memory 195752 kb
Host smart-1b326bec-b73b-44fb-9108-c41f78a39037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142056908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2142056908
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.171871254
Short name T483
Test name
Test status
Simulation time 7733862131 ps
CPU time 34.88 seconds
Started Aug 13 06:32:14 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 200720 kb
Host smart-96818686-d134-4ce1-a747-1f324f8d605d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171871254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.171871254
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2050384980
Short name T79
Test name
Test status
Simulation time 3953175420 ps
CPU time 50.58 seconds
Started Aug 13 06:32:27 PM PDT 24
Finished Aug 13 06:33:17 PM PDT 24
Peak memory 200736 kb
Host smart-978b412a-6c18-4654-ae63-a4136bcbe5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050384980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2050384980
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.914845578
Short name T25
Test name
Test status
Simulation time 18541964944 ps
CPU time 884.29 seconds
Started Aug 13 06:32:19 PM PDT 24
Finished Aug 13 06:47:03 PM PDT 24
Peak memory 733280 kb
Host smart-137a2b94-a547-47f5-95e7-ac65e92e0193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914845578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.914845578
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2211710913
Short name T343
Test name
Test status
Simulation time 2509664605 ps
CPU time 32.69 seconds
Started Aug 13 06:32:27 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 200728 kb
Host smart-f5e49982-e06a-4faa-9bca-20c1334d2e98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211710913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2211710913
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4112151528
Short name T469
Test name
Test status
Simulation time 18440136 ps
CPU time 0.66 seconds
Started Aug 13 06:32:30 PM PDT 24
Finished Aug 13 06:32:31 PM PDT 24
Peak memory 197236 kb
Host smart-bc13f469-0d36-4bd4-bb24-573aee7ea924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112151528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4112151528
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2415379517
Short name T481
Test name
Test status
Simulation time 819404240 ps
CPU time 14.04 seconds
Started Aug 13 06:32:15 PM PDT 24
Finished Aug 13 06:32:29 PM PDT 24
Peak memory 200664 kb
Host smart-b1de8495-462e-49d9-a077-1b423f7d9551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415379517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2415379517
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.4275089221
Short name T203
Test name
Test status
Simulation time 199096122788 ps
CPU time 838.69 seconds
Started Aug 13 06:32:28 PM PDT 24
Finished Aug 13 06:46:27 PM PDT 24
Peak memory 623248 kb
Host smart-d30e56cb-3eb7-4dd6-8b8e-9f2ae4bce1a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275089221 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.4275089221
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.482921824
Short name T236
Test name
Test status
Simulation time 650712784 ps
CPU time 28.61 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:32:45 PM PDT 24
Peak memory 200636 kb
Host smart-41225f0c-b39d-4a5b-bfcc-e0ef82e2f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482921824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.482921824
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.32773828
Short name T247
Test name
Test status
Simulation time 21618250 ps
CPU time 0.59 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:32:22 PM PDT 24
Peak memory 196324 kb
Host smart-a6deba7d-c47e-4a29-918d-e3f3c1511e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.32773828
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3198267160
Short name T183
Test name
Test status
Simulation time 1061061924 ps
CPU time 65.95 seconds
Started Aug 13 06:32:22 PM PDT 24
Finished Aug 13 06:33:28 PM PDT 24
Peak memory 200672 kb
Host smart-f2eadf03-b6aa-4f8b-a1c1-0f9d9edd6545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198267160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3198267160
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1690318604
Short name T301
Test name
Test status
Simulation time 3315463965 ps
CPU time 24.51 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 200752 kb
Host smart-03e8c1ce-d18c-4745-a98b-a380d3a514ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690318604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1690318604
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.124680740
Short name T346
Test name
Test status
Simulation time 10014658706 ps
CPU time 686.05 seconds
Started Aug 13 06:32:24 PM PDT 24
Finished Aug 13 06:43:50 PM PDT 24
Peak memory 643288 kb
Host smart-1f92020e-1a5c-473a-b1f3-ee221ed8d90a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124680740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.124680740
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3227860129
Short name T52
Test name
Test status
Simulation time 2925499583 ps
CPU time 58.6 seconds
Started Aug 13 06:32:24 PM PDT 24
Finished Aug 13 06:33:22 PM PDT 24
Peak memory 200744 kb
Host smart-6d488bb5-edcc-4c7b-8e2e-f4f2291cb46f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227860129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3227860129
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1971560928
Short name T333
Test name
Test status
Simulation time 3705393315 ps
CPU time 17.47 seconds
Started Aug 13 06:32:32 PM PDT 24
Finished Aug 13 06:32:50 PM PDT 24
Peak memory 200720 kb
Host smart-9a129ff1-36b4-4504-a79e-8999566ffb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971560928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1971560928
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2694577260
Short name T266
Test name
Test status
Simulation time 73064995 ps
CPU time 1.83 seconds
Started Aug 13 06:32:36 PM PDT 24
Finished Aug 13 06:32:38 PM PDT 24
Peak memory 200692 kb
Host smart-872b03f0-3997-41b5-b86f-11b018879e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694577260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2694577260
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2186517467
Short name T142
Test name
Test status
Simulation time 67290207666 ps
CPU time 2857.95 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 07:19:59 PM PDT 24
Peak memory 788376 kb
Host smart-d1c7e02e-cfe6-496e-9bf1-64cda6e6b0f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186517467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2186517467
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4092044604
Short name T120
Test name
Test status
Simulation time 14278355406 ps
CPU time 150.64 seconds
Started Aug 13 06:32:38 PM PDT 24
Finished Aug 13 06:35:09 PM PDT 24
Peak memory 200756 kb
Host smart-b0de47f7-49f7-42aa-95c6-aa9d3c0cbd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092044604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4092044604
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1517811310
Short name T31
Test name
Test status
Simulation time 127276804 ps
CPU time 0.63 seconds
Started Aug 13 06:32:38 PM PDT 24
Finished Aug 13 06:32:39 PM PDT 24
Peak memory 197400 kb
Host smart-da4d6dd8-9181-4740-8db9-b4170ff8df1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517811310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1517811310
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1498378624
Short name T417
Test name
Test status
Simulation time 83776171 ps
CPU time 1.34 seconds
Started Aug 13 06:32:16 PM PDT 24
Finished Aug 13 06:32:18 PM PDT 24
Peak memory 200584 kb
Host smart-a2b2ff2c-88d8-43d0-8cdf-e69e7d11447a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498378624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1498378624
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1569587753
Short name T140
Test name
Test status
Simulation time 1984824205 ps
CPU time 28.65 seconds
Started Aug 13 06:32:20 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 200684 kb
Host smart-e6f9bd34-b9d0-445d-ab6e-5f02df1dffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569587753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1569587753
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.226321435
Short name T274
Test name
Test status
Simulation time 181941294 ps
CPU time 18.65 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:32:42 PM PDT 24
Peak memory 239004 kb
Host smart-4f601445-1039-4a60-b31f-cc9ed270d8c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226321435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.226321435
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3915498306
Short name T454
Test name
Test status
Simulation time 324046903 ps
CPU time 4.69 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:32:45 PM PDT 24
Peak memory 200540 kb
Host smart-2d372f4a-a7c5-43e7-9359-d967e00e31f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915498306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3915498306
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3944353168
Short name T209
Test name
Test status
Simulation time 19871005692 ps
CPU time 85.73 seconds
Started Aug 13 06:32:23 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 200816 kb
Host smart-1f35cb64-560e-49a8-a4b5-650248698c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944353168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3944353168
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1672289897
Short name T202
Test name
Test status
Simulation time 105365690 ps
CPU time 4.65 seconds
Started Aug 13 06:32:25 PM PDT 24
Finished Aug 13 06:32:30 PM PDT 24
Peak memory 200760 kb
Host smart-b52eae79-de8e-4664-9410-8164eab0865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672289897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1672289897
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.592870161
Short name T367
Test name
Test status
Simulation time 21716555801 ps
CPU time 388.5 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:39:10 PM PDT 24
Peak memory 208888 kb
Host smart-7188b610-c90d-452e-bfd9-2c23975011d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592870161 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.592870161
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3206108206
Short name T373
Test name
Test status
Simulation time 1949503213 ps
CPU time 36.36 seconds
Started Aug 13 06:32:27 PM PDT 24
Finished Aug 13 06:33:03 PM PDT 24
Peak memory 200600 kb
Host smart-6c82bd36-eabc-4d30-861b-a2378dc10292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206108206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3206108206
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3621782420
Short name T80
Test name
Test status
Simulation time 52966217 ps
CPU time 0.57 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 196340 kb
Host smart-bf23d30c-4015-4f1b-bc9b-9f0c80cc0cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621782420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3621782420
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2084859149
Short name T37
Test name
Test status
Simulation time 7352455544 ps
CPU time 102.43 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:34:17 PM PDT 24
Peak memory 208960 kb
Host smart-f2a64e65-4321-4b5a-8d7d-55a88b903ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084859149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2084859149
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2594912629
Short name T143
Test name
Test status
Simulation time 2272412458 ps
CPU time 30.56 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:33:04 PM PDT 24
Peak memory 200820 kb
Host smart-835f335f-286a-4d41-9042-3c7305073d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594912629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2594912629
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2024604651
Short name T174
Test name
Test status
Simulation time 10182624581 ps
CPU time 970.4 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:48:51 PM PDT 24
Peak memory 710748 kb
Host smart-b9eb5702-25dd-4146-a3be-8343d09a319f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024604651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2024604651
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.416760497
Short name T530
Test name
Test status
Simulation time 4494235919 ps
CPU time 77.92 seconds
Started Aug 13 06:32:31 PM PDT 24
Finished Aug 13 06:33:49 PM PDT 24
Peak memory 200648 kb
Host smart-37fd555a-ac99-4bba-a6ea-6ced2f9b1f52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416760497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.416760497
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2205788787
Short name T13
Test name
Test status
Simulation time 5101894410 ps
CPU time 102.43 seconds
Started Aug 13 06:32:28 PM PDT 24
Finished Aug 13 06:34:11 PM PDT 24
Peak memory 217020 kb
Host smart-c27d6dac-ecba-451a-a856-0433dc0ca40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205788787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2205788787
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3698166932
Short name T344
Test name
Test status
Simulation time 721929205 ps
CPU time 8.87 seconds
Started Aug 13 06:32:25 PM PDT 24
Finished Aug 13 06:32:34 PM PDT 24
Peak memory 200648 kb
Host smart-babd739d-2764-431e-ad0e-d1b49d5014f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698166932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3698166932
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2365804804
Short name T405
Test name
Test status
Simulation time 50061031194 ps
CPU time 365.02 seconds
Started Aug 13 06:32:29 PM PDT 24
Finished Aug 13 06:38:34 PM PDT 24
Peak memory 482908 kb
Host smart-ea4abb7d-3d1c-4eb6-bf96-b9d08173d2f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365804804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2365804804
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.400143842
Short name T464
Test name
Test status
Simulation time 10859377112 ps
CPU time 93.42 seconds
Started Aug 13 06:32:31 PM PDT 24
Finished Aug 13 06:34:05 PM PDT 24
Peak memory 200600 kb
Host smart-6e3dc09e-6406-4de3-854d-113ee38c12f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400143842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.400143842
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.712355737
Short name T156
Test name
Test status
Simulation time 80121351 ps
CPU time 0.6 seconds
Started Aug 13 06:32:36 PM PDT 24
Finished Aug 13 06:32:36 PM PDT 24
Peak memory 196772 kb
Host smart-309ba50d-b3c1-4d06-89b1-08ae26d37a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712355737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.712355737
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.52798876
Short name T456
Test name
Test status
Simulation time 1005663883 ps
CPU time 54.33 seconds
Started Aug 13 06:32:35 PM PDT 24
Finished Aug 13 06:33:29 PM PDT 24
Peak memory 200768 kb
Host smart-9c647c40-bdf8-4f93-9ca3-e4232bc0a61d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52798876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.52798876
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.724671651
Short name T326
Test name
Test status
Simulation time 227190236 ps
CPU time 3.06 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:32:38 PM PDT 24
Peak memory 200688 kb
Host smart-3da14fbf-f96d-4722-b359-81b40d60790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724671651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.724671651
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2969441909
Short name T318
Test name
Test status
Simulation time 6878118512 ps
CPU time 428.28 seconds
Started Aug 13 06:32:35 PM PDT 24
Finished Aug 13 06:39:43 PM PDT 24
Peak memory 612712 kb
Host smart-5e9bc5f0-3202-4d92-98c3-96d7027dbff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969441909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2969441909
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2667952316
Short name T381
Test name
Test status
Simulation time 48158672028 ps
CPU time 205.59 seconds
Started Aug 13 06:32:31 PM PDT 24
Finished Aug 13 06:35:57 PM PDT 24
Peak memory 200740 kb
Host smart-d507effe-c652-46f4-a2a5-ea526f24f1b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667952316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2667952316
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1342528068
Short name T78
Test name
Test status
Simulation time 19006337043 ps
CPU time 74.05 seconds
Started Aug 13 06:32:30 PM PDT 24
Finished Aug 13 06:33:45 PM PDT 24
Peak memory 200960 kb
Host smart-5390efba-9247-4d22-ae46-11b43a926def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342528068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1342528068
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3105946111
Short name T463
Test name
Test status
Simulation time 1946381961 ps
CPU time 11.79 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:53 PM PDT 24
Peak memory 200692 kb
Host smart-fd8e2faf-c61c-4c1c-bea9-9259bfd4adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105946111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3105946111
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1950469293
Short name T46
Test name
Test status
Simulation time 53349601773 ps
CPU time 1952.35 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 07:05:13 PM PDT 24
Peak memory 766000 kb
Host smart-756886e6-b120-46cb-a204-86e462d1967c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950469293 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1950469293
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1133969882
Short name T402
Test name
Test status
Simulation time 26884245822 ps
CPU time 124.78 seconds
Started Aug 13 06:32:35 PM PDT 24
Finished Aug 13 06:34:40 PM PDT 24
Peak memory 200768 kb
Host smart-e6cf5e56-bc98-443e-b5b7-bf2b78730cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133969882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1133969882
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.311279815
Short name T157
Test name
Test status
Simulation time 29302424 ps
CPU time 0.67 seconds
Started Aug 13 06:32:43 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 197460 kb
Host smart-85db278c-40f0-46d2-a1b6-ebf9d8983015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311279815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.311279815
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.58734754
Short name T474
Test name
Test status
Simulation time 376193476 ps
CPU time 7.2 seconds
Started Aug 13 06:32:35 PM PDT 24
Finished Aug 13 06:32:42 PM PDT 24
Peak memory 200576 kb
Host smart-9f3010aa-8302-4318-addf-083fe2cdda54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58734754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.58734754
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.112418144
Short name T291
Test name
Test status
Simulation time 7842435308 ps
CPU time 55.18 seconds
Started Aug 13 06:32:31 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 200504 kb
Host smart-fa0c555f-8893-4765-872b-cf3ca2a0df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112418144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.112418144
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2742030277
Short name T75
Test name
Test status
Simulation time 2259165269 ps
CPU time 258.93 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:36:59 PM PDT 24
Peak memory 618388 kb
Host smart-fe5c1101-37fe-43c3-ab9d-4162478a666f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742030277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2742030277
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2655874113
Short name T152
Test name
Test status
Simulation time 6734867020 ps
CPU time 31.86 seconds
Started Aug 13 06:32:40 PM PDT 24
Finished Aug 13 06:33:12 PM PDT 24
Peak memory 200660 kb
Host smart-f35b341a-fe7b-4d16-8676-16e77e10498e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655874113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2655874113
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3613074204
Short name T34
Test name
Test status
Simulation time 28646201206 ps
CPU time 91.35 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:34:24 PM PDT 24
Peak memory 200816 kb
Host smart-c67e0112-9c68-4adc-9a85-206166b266ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613074204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3613074204
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2403174729
Short name T26
Test name
Test status
Simulation time 7966127220 ps
CPU time 11.47 seconds
Started Aug 13 06:32:41 PM PDT 24
Finished Aug 13 06:32:52 PM PDT 24
Peak memory 200756 kb
Host smart-f073467b-1747-40ae-80ad-18b7d868e79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403174729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2403174729
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4247056273
Short name T499
Test name
Test status
Simulation time 533099586 ps
CPU time 8.28 seconds
Started Aug 13 06:32:37 PM PDT 24
Finished Aug 13 06:32:46 PM PDT 24
Peak memory 200724 kb
Host smart-bd6304a3-c628-406d-b7c0-841686739a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247056273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4247056273
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3149250625
Short name T32
Test name
Test status
Simulation time 24344239 ps
CPU time 0.58 seconds
Started Aug 13 06:32:39 PM PDT 24
Finished Aug 13 06:32:40 PM PDT 24
Peak memory 196348 kb
Host smart-173e93d5-f650-4e23-ac30-7be388d842ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149250625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3149250625
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3576177873
Short name T284
Test name
Test status
Simulation time 2083901736 ps
CPU time 6.75 seconds
Started Aug 13 06:32:44 PM PDT 24
Finished Aug 13 06:32:50 PM PDT 24
Peak memory 200580 kb
Host smart-1de0eaf6-5a80-47e3-b801-d294c0c2bb11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576177873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3576177873
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1243322930
Short name T138
Test name
Test status
Simulation time 990002669 ps
CPU time 51.12 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 200688 kb
Host smart-ae276e9f-e7c2-4f99-a2f3-1e2e1514ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243322930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1243322930
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1740786392
Short name T268
Test name
Test status
Simulation time 23366415570 ps
CPU time 1015.66 seconds
Started Aug 13 06:32:43 PM PDT 24
Finished Aug 13 06:49:39 PM PDT 24
Peak memory 743144 kb
Host smart-24eb6562-b084-497c-b8ff-c6970e9a169b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740786392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1740786392
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1837262051
Short name T48
Test name
Test status
Simulation time 33273119637 ps
CPU time 232.11 seconds
Started Aug 13 06:32:49 PM PDT 24
Finished Aug 13 06:36:41 PM PDT 24
Peak memory 200748 kb
Host smart-24bc666d-75f0-49cc-a952-6c1d326179ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837262051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1837262051
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3796765709
Short name T184
Test name
Test status
Simulation time 12740238366 ps
CPU time 78.7 seconds
Started Aug 13 06:32:44 PM PDT 24
Finished Aug 13 06:34:03 PM PDT 24
Peak memory 200784 kb
Host smart-da4f8cf8-6900-4d13-a27e-d7226000c4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796765709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3796765709
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.584161302
Short name T319
Test name
Test status
Simulation time 375022206 ps
CPU time 5.95 seconds
Started Aug 13 06:32:38 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 200680 kb
Host smart-0e536702-d2cd-4205-af37-639420afc0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584161302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.584161302
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.806622361
Short name T386
Test name
Test status
Simulation time 5923876420 ps
CPU time 156.92 seconds
Started Aug 13 06:32:34 PM PDT 24
Finished Aug 13 06:35:11 PM PDT 24
Peak memory 200796 kb
Host smart-ac0b61fc-e575-4b86-9ad4-ecee15aeb060
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806622361 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.806622361
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1025699471
Short name T317
Test name
Test status
Simulation time 5961045492 ps
CPU time 62.38 seconds
Started Aug 13 06:32:33 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 200760 kb
Host smart-0f8bc085-84ca-4e72-b8f6-c9f810273bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025699471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1025699471
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2771710784
Short name T441
Test name
Test status
Simulation time 15237082 ps
CPU time 0.58 seconds
Started Aug 13 06:32:48 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 196496 kb
Host smart-123a926d-446b-4792-854b-26480d0d479b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771710784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2771710784
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.742485611
Short name T159
Test name
Test status
Simulation time 2930762129 ps
CPU time 10.87 seconds
Started Aug 13 06:32:29 PM PDT 24
Finished Aug 13 06:32:40 PM PDT 24
Peak memory 200732 kb
Host smart-10a61156-942d-4d2f-bb3e-e3f1c9eec9c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742485611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.742485611
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2976540913
Short name T327
Test name
Test status
Simulation time 4368904238 ps
CPU time 6.3 seconds
Started Aug 13 06:32:31 PM PDT 24
Finished Aug 13 06:32:38 PM PDT 24
Peak memory 200672 kb
Host smart-3b16ef64-c10a-4717-9c84-af705c7b6ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976540913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2976540913
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.684863024
Short name T229
Test name
Test status
Simulation time 1370536956 ps
CPU time 203.84 seconds
Started Aug 13 06:32:32 PM PDT 24
Finished Aug 13 06:35:56 PM PDT 24
Peak memory 418560 kb
Host smart-6993f4ef-7a13-430f-a49e-2617cd19289e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684863024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.684863024
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4141663879
Short name T510
Test name
Test status
Simulation time 14171714122 ps
CPU time 114.75 seconds
Started Aug 13 06:32:51 PM PDT 24
Finished Aug 13 06:34:46 PM PDT 24
Peak memory 200736 kb
Host smart-d2800e83-d4cd-4d73-948f-95cbfadd973a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141663879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4141663879
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3683309549
Short name T148
Test name
Test status
Simulation time 2281465309 ps
CPU time 28.83 seconds
Started Aug 13 06:32:30 PM PDT 24
Finished Aug 13 06:32:59 PM PDT 24
Peak memory 200700 kb
Host smart-9b23edb9-1e5c-4a3d-9527-35505f80d828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683309549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3683309549
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1302191508
Short name T366
Test name
Test status
Simulation time 493200128 ps
CPU time 1.92 seconds
Started Aug 13 06:32:43 PM PDT 24
Finished Aug 13 06:32:45 PM PDT 24
Peak memory 200656 kb
Host smart-cf35fee4-245d-4b9d-98d7-f67ff2b0d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302191508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1302191508
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4191088101
Short name T67
Test name
Test status
Simulation time 35047886743 ps
CPU time 481.32 seconds
Started Aug 13 06:32:52 PM PDT 24
Finished Aug 13 06:40:53 PM PDT 24
Peak memory 200776 kb
Host smart-3a89a9a8-6dfd-4400-90f5-4ea4d4470f9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191088101 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4191088101
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.261740104
Short name T92
Test name
Test status
Simulation time 1119544222 ps
CPU time 34.26 seconds
Started Aug 13 06:32:35 PM PDT 24
Finished Aug 13 06:33:09 PM PDT 24
Peak memory 200692 kb
Host smart-c983a468-8bcb-4dd3-9950-5f07f3398656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261740104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.261740104
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.169908165
Short name T462
Test name
Test status
Simulation time 11830908 ps
CPU time 0.6 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:31:53 PM PDT 24
Peak memory 195608 kb
Host smart-aae05120-a3c6-4351-87e0-8fee5425139e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169908165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.169908165
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1540063012
Short name T88
Test name
Test status
Simulation time 139431741 ps
CPU time 4.18 seconds
Started Aug 13 06:31:37 PM PDT 24
Finished Aug 13 06:31:42 PM PDT 24
Peak memory 200676 kb
Host smart-fa911e70-b63e-49f6-8abe-2aae411dee3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540063012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1540063012
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.104120306
Short name T232
Test name
Test status
Simulation time 5113836275 ps
CPU time 22.91 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:32:18 PM PDT 24
Peak memory 200776 kb
Host smart-3ba256e9-fa90-4ad8-88dc-c8e9b2f6c08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104120306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.104120306
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.739686873
Short name T208
Test name
Test status
Simulation time 13414193787 ps
CPU time 1314.75 seconds
Started Aug 13 06:31:35 PM PDT 24
Finished Aug 13 06:53:30 PM PDT 24
Peak memory 793380 kb
Host smart-95f6b107-9d26-422b-90fd-906c2eb69d4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739686873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.739686873
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1888803777
Short name T303
Test name
Test status
Simulation time 45300931706 ps
CPU time 73.11 seconds
Started Aug 13 06:31:55 PM PDT 24
Finished Aug 13 06:33:08 PM PDT 24
Peak memory 200692 kb
Host smart-1e1770a5-43fe-407b-ad2b-9036783334dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888803777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1888803777
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1976120431
Short name T380
Test name
Test status
Simulation time 14543775009 ps
CPU time 64.73 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:32:58 PM PDT 24
Peak memory 216832 kb
Host smart-8c2236f0-93f9-4357-8331-b8683cf77433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976120431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1976120431
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4009619627
Short name T283
Test name
Test status
Simulation time 2628677934 ps
CPU time 5.58 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:31:58 PM PDT 24
Peak memory 200664 kb
Host smart-cacd7156-1b47-4f69-adc0-5a2e4c57c3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009619627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4009619627
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3153375667
Short name T482
Test name
Test status
Simulation time 26599092819 ps
CPU time 342.78 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:37:34 PM PDT 24
Peak memory 200752 kb
Host smart-6e85aaab-c26b-468c-a306-e725a743d072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153375667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3153375667
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3287497007
Short name T19
Test name
Test status
Simulation time 28366869866 ps
CPU time 557.3 seconds
Started Aug 13 06:31:40 PM PDT 24
Finished Aug 13 06:40:58 PM PDT 24
Peak memory 679380 kb
Host smart-9d8f15e2-dac4-4ef5-a9fb-435d07124dc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287497007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3287497007
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1968898268
Short name T257
Test name
Test status
Simulation time 2478470446 ps
CPU time 35.25 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:32:27 PM PDT 24
Peak memory 200764 kb
Host smart-46680890-1ffd-4b33-b74f-d7c53022a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968898268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1968898268
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1712844658
Short name T450
Test name
Test status
Simulation time 25516799 ps
CPU time 0.6 seconds
Started Aug 13 06:31:43 PM PDT 24
Finished Aug 13 06:31:44 PM PDT 24
Peak memory 196704 kb
Host smart-ad5098c0-988e-4995-8312-77790cf4fbeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712844658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1712844658
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3391311079
Short name T404
Test name
Test status
Simulation time 1130397228 ps
CPU time 64.28 seconds
Started Aug 13 06:31:50 PM PDT 24
Finished Aug 13 06:32:54 PM PDT 24
Peak memory 200760 kb
Host smart-ad319ad3-015b-435c-a025-4b03be105f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3391311079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3391311079
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.225181405
Short name T506
Test name
Test status
Simulation time 5564101436 ps
CPU time 34.63 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:32:26 PM PDT 24
Peak memory 200756 kb
Host smart-7b7f40eb-0348-44c2-a5b1-2c1e9c896e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225181405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.225181405
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.996288884
Short name T290
Test name
Test status
Simulation time 6088967672 ps
CPU time 560.65 seconds
Started Aug 13 06:31:50 PM PDT 24
Finished Aug 13 06:41:11 PM PDT 24
Peak memory 734492 kb
Host smart-b8faf955-47cb-4055-a076-b6aa5e07870f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996288884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.996288884
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3611772134
Short name T54
Test name
Test status
Simulation time 22705393702 ps
CPU time 92.34 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:33:23 PM PDT 24
Peak memory 200700 kb
Host smart-ca2c335c-eeb0-47a8-b24a-5ce8c5b4bca9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611772134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3611772134
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2686166133
Short name T484
Test name
Test status
Simulation time 29771379890 ps
CPU time 95.66 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:33:34 PM PDT 24
Peak memory 200736 kb
Host smart-f382743c-e032-4066-bd93-e5da205da3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686166133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2686166133
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.450894979
Short name T371
Test name
Test status
Simulation time 1510988184 ps
CPU time 10.83 seconds
Started Aug 13 06:31:48 PM PDT 24
Finished Aug 13 06:31:59 PM PDT 24
Peak memory 200676 kb
Host smart-53fd0042-97b3-4b4b-beb7-ed9a5d1e53dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450894979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.450894979
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2878304437
Short name T383
Test name
Test status
Simulation time 306863372164 ps
CPU time 1823.38 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 07:02:21 PM PDT 24
Peak memory 722084 kb
Host smart-544f0da8-c626-455e-95ed-3b234510cfc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878304437 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2878304437
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.839745793
Short name T251
Test name
Test status
Simulation time 1587398267 ps
CPU time 28.41 seconds
Started Aug 13 06:31:49 PM PDT 24
Finished Aug 13 06:32:17 PM PDT 24
Peak memory 200716 kb
Host smart-d3725673-2402-4391-9ed8-3f4446eea0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839745793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.839745793
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3883551147
Short name T196
Test name
Test status
Simulation time 11053528 ps
CPU time 0.59 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:31:57 PM PDT 24
Peak memory 196424 kb
Host smart-35b5c2c3-e08f-49d7-9236-e4b4e0660ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883551147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3883551147
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1805958812
Short name T496
Test name
Test status
Simulation time 1574458271 ps
CPU time 100.52 seconds
Started Aug 13 06:31:40 PM PDT 24
Finished Aug 13 06:33:21 PM PDT 24
Peak memory 200700 kb
Host smart-69968230-aa30-4043-acaf-f593e7449876
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805958812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1805958812
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1422371752
Short name T324
Test name
Test status
Simulation time 2749312703 ps
CPU time 36.66 seconds
Started Aug 13 06:31:48 PM PDT 24
Finished Aug 13 06:32:25 PM PDT 24
Peak memory 200768 kb
Host smart-c8b1fef9-2991-400c-b75c-242ccd051108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422371752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1422371752
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2978505630
Short name T204
Test name
Test status
Simulation time 5274622878 ps
CPU time 881.13 seconds
Started Aug 13 06:31:54 PM PDT 24
Finished Aug 13 06:46:35 PM PDT 24
Peak memory 724288 kb
Host smart-8a3cfc1e-592e-4543-8820-c40f4e0db2ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978505630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2978505630
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2337706257
Short name T349
Test name
Test status
Simulation time 1418333144 ps
CPU time 10.36 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:32:03 PM PDT 24
Peak memory 200572 kb
Host smart-303eef7a-dcc6-4755-b6ad-4f4e7e3b183b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337706257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2337706257
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2900451819
Short name T82
Test name
Test status
Simulation time 28709665922 ps
CPU time 95.35 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:33:27 PM PDT 24
Peak memory 200768 kb
Host smart-d1b98e0b-4229-4f63-8e9b-680cd3e2caeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900451819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2900451819
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1268296668
Short name T418
Test name
Test status
Simulation time 107310968 ps
CPU time 4.78 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:32:07 PM PDT 24
Peak memory 200680 kb
Host smart-27e3465f-f81a-40ed-93d7-97c2d2a1e79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268296668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1268296668
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1606481402
Short name T411
Test name
Test status
Simulation time 70936684216 ps
CPU time 1899.3 seconds
Started Aug 13 06:32:02 PM PDT 24
Finished Aug 13 07:03:42 PM PDT 24
Peak memory 716540 kb
Host smart-b3729428-ce78-4799-8e5d-231cd707763f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606481402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1606481402
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1971969849
Short name T524
Test name
Test status
Simulation time 15044543 ps
CPU time 0.79 seconds
Started Aug 13 06:31:46 PM PDT 24
Finished Aug 13 06:31:46 PM PDT 24
Peak memory 198264 kb
Host smart-70a44b7e-aead-4050-81ba-47910fdc80c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971969849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1971969849
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3604187503
Short name T435
Test name
Test status
Simulation time 14656729 ps
CPU time 0.58 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 06:31:52 PM PDT 24
Peak memory 197464 kb
Host smart-0a1e78e7-abfb-4dc5-8e9c-a0e27b530597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604187503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3604187503
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2807244643
Short name T314
Test name
Test status
Simulation time 1398805597 ps
CPU time 39.78 seconds
Started Aug 13 06:32:01 PM PDT 24
Finished Aug 13 06:32:41 PM PDT 24
Peak memory 200700 kb
Host smart-b6836baa-91e5-451d-a1d5-eccbec22ac31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807244643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2807244643
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3418522812
Short name T308
Test name
Test status
Simulation time 2052818213 ps
CPU time 39.95 seconds
Started Aug 13 06:31:53 PM PDT 24
Finished Aug 13 06:32:33 PM PDT 24
Peak memory 200680 kb
Host smart-5f7598c2-c230-46cd-8b50-71d8ac3069db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418522812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3418522812
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.167843784
Short name T416
Test name
Test status
Simulation time 4359047599 ps
CPU time 199.68 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:35:12 PM PDT 24
Peak memory 629284 kb
Host smart-034daac5-78b7-48ab-b2ab-3e19379b6ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167843784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.167843784
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1447433321
Short name T352
Test name
Test status
Simulation time 19917021002 ps
CPU time 61.82 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:32:57 PM PDT 24
Peak memory 200804 kb
Host smart-ab60cab4-97ff-431b-8272-ac597cbfe00b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447433321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1447433321
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.65318984
Short name T216
Test name
Test status
Simulation time 1192615358 ps
CPU time 69.24 seconds
Started Aug 13 06:31:39 PM PDT 24
Finished Aug 13 06:32:48 PM PDT 24
Peak memory 200688 kb
Host smart-e61de1a0-47ee-486d-847c-92b8bc2178fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65318984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.65318984
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3142554578
Short name T286
Test name
Test status
Simulation time 1702096188 ps
CPU time 8.52 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:32:12 PM PDT 24
Peak memory 200704 kb
Host smart-0ca022c9-be14-42c7-952e-c91dd96a4eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142554578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3142554578
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.317242633
Short name T144
Test name
Test status
Simulation time 43583025751 ps
CPU time 3507.07 seconds
Started Aug 13 06:31:51 PM PDT 24
Finished Aug 13 07:30:19 PM PDT 24
Peak memory 785976 kb
Host smart-5927a6b2-cd07-48e6-8b4c-14725cbf3aea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317242633 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.317242633
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2248923619
Short name T4
Test name
Test status
Simulation time 8885426646 ps
CPU time 69.19 seconds
Started Aug 13 06:31:47 PM PDT 24
Finished Aug 13 06:32:56 PM PDT 24
Peak memory 225464 kb
Host smart-6df404cf-3f8a-43ea-a08f-e2a7bfc00d8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248923619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2248923619
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1055933798
Short name T238
Test name
Test status
Simulation time 40269228324 ps
CPU time 106.85 seconds
Started Aug 13 06:31:39 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 200780 kb
Host smart-f3639728-679e-4b2d-a292-e3b03e263725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055933798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1055933798
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3517257852
Short name T313
Test name
Test status
Simulation time 16976823 ps
CPU time 0.58 seconds
Started Aug 13 06:31:56 PM PDT 24
Finished Aug 13 06:31:57 PM PDT 24
Peak memory 196740 kb
Host smart-622c0c8b-1669-4a94-b125-c76c0bd013a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517257852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3517257852
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1663983480
Short name T451
Test name
Test status
Simulation time 4664954228 ps
CPU time 64.09 seconds
Started Aug 13 06:31:45 PM PDT 24
Finished Aug 13 06:32:49 PM PDT 24
Peak memory 200740 kb
Host smart-55b5d3e9-b29c-4b39-af7d-420e109db38b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663983480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1663983480
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3714125883
Short name T86
Test name
Test status
Simulation time 22124839358 ps
CPU time 77.53 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:33:00 PM PDT 24
Peak memory 200712 kb
Host smart-ff967ba7-fbd4-486a-8552-0a39e719850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714125883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3714125883
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3361011840
Short name T494
Test name
Test status
Simulation time 5006094905 ps
CPU time 1006.67 seconds
Started Aug 13 06:31:41 PM PDT 24
Finished Aug 13 06:48:27 PM PDT 24
Peak memory 738408 kb
Host smart-16fdf8df-ac90-4a3d-a457-77bf7d97fd05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361011840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3361011840
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1637011051
Short name T214
Test name
Test status
Simulation time 161111217193 ps
CPU time 143.44 seconds
Started Aug 13 06:31:46 PM PDT 24
Finished Aug 13 06:34:10 PM PDT 24
Peak memory 200748 kb
Host smart-864e8361-1e87-475f-b75d-93823ba8710e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637011051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1637011051
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2245053232
Short name T243
Test name
Test status
Simulation time 28139184730 ps
CPU time 184.94 seconds
Started Aug 13 06:31:57 PM PDT 24
Finished Aug 13 06:35:02 PM PDT 24
Peak memory 200720 kb
Host smart-29617478-0a70-4895-be48-72f4e3491f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245053232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2245053232
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3794619685
Short name T488
Test name
Test status
Simulation time 152427420 ps
CPU time 3.71 seconds
Started Aug 13 06:31:58 PM PDT 24
Finished Aug 13 06:32:02 PM PDT 24
Peak memory 200596 kb
Host smart-25ca7f52-3273-4306-a85a-b169ad35f665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794619685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3794619685
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1116427596
Short name T63
Test name
Test status
Simulation time 78494368829 ps
CPU time 2830.86 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 07:18:54 PM PDT 24
Peak memory 790580 kb
Host smart-7b38d0e7-5aa5-4ef8-9e9d-145cb9526f6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116427596 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1116427596
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.343107922
Short name T321
Test name
Test status
Simulation time 3469532054 ps
CPU time 43.21 seconds
Started Aug 13 06:31:52 PM PDT 24
Finished Aug 13 06:32:35 PM PDT 24
Peak memory 200724 kb
Host smart-e996ab11-fe67-4f12-a964-aece1f329107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343107922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.343107922
Directory /workspace/9.hmac_wipe_secret/latest
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