Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17352656	1			T1	34201		T2	25739		T3	93160
all_values[1]	17352656	1			T1	34201		T2	25739		T3	93160
all_values[2]	17352656	1			T1	34201		T2	25739		T3	93160

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266837

1

T1

877

T3

6

T8

104

auto[1]

51791131

1

T1

101726

T2

77217

T3

279474

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44315962

1

T1

81792

T2

64864

T3

238606

auto[1]

7742006

1

T1

20811

T2

12353

T3

40874

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104046	1			T3	3		T8	102		T52	152
all_values[0]	auto[0]	auto[1]	325	1			T8	2		T52	2		T27	7
all_values[0]	auto[1]	auto[0]	17228880	1			T1	34187		T2	25720		T3	93137
all_values[0]	auto[1]	auto[1]	19405	1			T1	14		T2	19		T3	20
all_values[1]	auto[0]	auto[0]	58678	1			T1	877		T6	127		T5	105
all_values[1]	auto[0]	auto[1]	196	1			T52	4		T27	6		T89	3
all_values[1]	auto[1]	auto[0]	17293490	1			T1	33324		T2	25739		T3	93160
all_values[1]	auto[1]	auto[1]	292	1			T52	9		T24	1		T27	6
all_values[2]	auto[0]	auto[0]	58116	1			T3	1		T52	6		T27	3394
all_values[2]	auto[0]	auto[1]	45476	1			T3	2		T52	6		T27	548
all_values[2]	auto[1]	auto[0]	9572752	1			T1	13404		T2	13405		T3	52305
all_values[2]	auto[1]	auto[1]	7676312	1			T1	20797		T2	12334		T3	40852