Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118767

1

T1

38

T2

34

T4

12

auto[1]

122156

1

T1

42

T2

22

T3

58

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	92507	1			T1	40		T2	25		T3	16
len_1026_2046	4384	1			T2	1		T8	1		T12	2
len_514_1022	3721	1			T8	2		T12	6		T5	6
len_2_510	3478	1			T2	1		T5	2		T16	3
len_2056	174	1			T8	1		T53	1		T27	7
len_2048	296	1			T4	1		T16	4		T21	1
len_2040	349	1			T8	2		T27	2		T89	5
len_1032	415	1			T27	2		T89	6		T144	2
len_1024	1749	1			T5	1		T22	2		T51	1
len_1016	166	1			T16	2		T52	4		T27	2
len_520	149	1			T8	1		T104	2		T89	5
len_512	391	1			T8	1		T7	2		T5	2
len_504	168	1			T8	1		T27	1		T103	1
len_8	1303	1			T3	13		T157	16		T27	105
len_0	11211	1			T2	1		T4	1		T8	10

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

146

1

T21

2

T22

1

T52

4

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	45821	1			T1	19		T2	15		T4	4
auto[0]	len_1026_2046	2203	1			T8	1		T12	2		T7	2
auto[0]	len_514_1022	2574	1			T12	1		T21	2		T22	3
auto[0]	len_2_510	2363	1			T2	1		T16	1		T22	3
auto[0]	len_2056	98	1			T27	2		T89	4		T91	3
auto[0]	len_2048	170	1			T4	1		T16	3		T52	1
auto[0]	len_2040	239	1			T8	1		T27	1		T89	3
auto[0]	len_1032	344	1			T27	2		T89	3		T90	2
auto[0]	len_1024	254	1			T22	1		T51	1		T52	1
auto[0]	len_1016	93	1			T16	1		T52	3		T89	1
auto[0]	len_520	88	1			T104	1		T89	2		T109	1
auto[0]	len_512	227	1			T8	1		T16	2		T21	1
auto[0]	len_504	108	1			T103	1		T89	8		T108	2
auto[0]	len_8	26	1			T109	1		T68	2		T19	1
auto[0]	len_0	4775	1			T2	1		T4	1		T8	6
auto[1]	len_2050_plus	46686	1			T1	21		T2	10		T3	16
auto[1]	len_1026_2046	2181	1			T2	1		T5	6		T16	3
auto[1]	len_514_1022	1147	1			T8	2		T12	5		T5	6
auto[1]	len_2_510	1115	1			T5	2		T16	2		T21	5
auto[1]	len_2056	76	1			T8	1		T53	1		T27	5
auto[1]	len_2048	126	1			T16	1		T21	1		T27	7
auto[1]	len_2040	110	1			T8	1		T27	1		T89	2
auto[1]	len_1032	71	1			T89	3		T144	2		T90	1
auto[1]	len_1024	1495	1			T5	1		T22	1		T98	52
auto[1]	len_1016	73	1			T16	1		T52	1		T27	2
auto[1]	len_520	61	1			T8	1		T104	1		T89	3
auto[1]	len_512	164	1			T7	2		T5	2		T52	1
auto[1]	len_504	60	1			T8	1		T27	1		T89	8
auto[1]	len_8	1277	1			T3	13		T157	16		T27	105
auto[1]	len_0	6436	1			T8	4		T6	2		T7	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

84

1

T21

2

T22

1

T52

2

auto[1]

len_upper

62

1

T52

2

T157

2

T27

2